DE3012831C2 - Schaltung zum Nachweis kleiner Unterschiede zwischen der Größe erster und zweiter Eingangssignale - Google Patents

Schaltung zum Nachweis kleiner Unterschiede zwischen der Größe erster und zweiter Eingangssignale

Info

Publication number
DE3012831C2
DE3012831C2 DE3012831A DE3012831A DE3012831C2 DE 3012831 C2 DE3012831 C2 DE 3012831C2 DE 3012831 A DE3012831 A DE 3012831A DE 3012831 A DE3012831 A DE 3012831A DE 3012831 C2 DE3012831 C2 DE 3012831C2
Authority
DE
Germany
Prior art keywords
circuit
bistable
transistors
transistor
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3012831A
Other languages
German (de)
English (en)
Other versions
DE3012831A1 (de
Inventor
Kent F. Salt Lake City Utah Smith
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Arris Technology Inc
Original Assignee
General Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Instrument Corp filed Critical General Instrument Corp
Publication of DE3012831A1 publication Critical patent/DE3012831A1/de
Application granted granted Critical
Publication of DE3012831C2 publication Critical patent/DE3012831C2/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
    • H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Static Random-Access Memory (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Logic Circuits (AREA)
  • Read Only Memory (AREA)
DE3012831A 1979-04-05 1980-04-02 Schaltung zum Nachweis kleiner Unterschiede zwischen der Größe erster und zweiter Eingangssignale Expired DE3012831C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/027,507 US4297598A (en) 1979-04-05 1979-04-05 I2 L Sensing circuit with increased sensitivity

Publications (2)

Publication Number Publication Date
DE3012831A1 DE3012831A1 (de) 1980-10-16
DE3012831C2 true DE3012831C2 (de) 1984-08-02

Family

ID=21838117

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3012831A Expired DE3012831C2 (de) 1979-04-05 1980-04-02 Schaltung zum Nachweis kleiner Unterschiede zwischen der Größe erster und zweiter Eingangssignale

Country Status (6)

Country Link
US (1) US4297598A (OSRAM)
JP (1) JPS55135391A (OSRAM)
CA (1) CA1134464A (OSRAM)
DE (1) DE3012831C2 (OSRAM)
FR (1) FR2453414A1 (OSRAM)
GB (1) GB2047497B (OSRAM)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59914B2 (ja) * 1979-08-23 1984-01-09 富士通株式会社 半導体記憶装置
US4393473A (en) * 1981-07-13 1983-07-12 Fairchild Camera & Instrument Corp. Random access memory preset circuitry
GB2247550B (en) * 1990-06-29 1994-08-03 Digital Equipment Corp Bipolar transistor memory cell and method
US8780657B2 (en) * 2012-03-01 2014-07-15 Apple Inc. Memory with bit line current injection
US9201727B2 (en) 2013-01-15 2015-12-01 International Business Machines Corporation Error protection for a data bus
US9021328B2 (en) 2013-01-15 2015-04-28 International Business Machines Corporation Shared error protection for register banks
US9041428B2 (en) * 2013-01-15 2015-05-26 International Business Machines Corporation Placement of storage cells on an integrated circuit
US9043683B2 (en) 2013-01-23 2015-05-26 International Business Machines Corporation Error protection for integrated circuits

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3487376A (en) * 1965-12-29 1969-12-30 Honeywell Inc Plural emitter semiconductive storage device
GB1162109A (en) * 1966-12-22 1969-08-20 Ibm Semi Conductor Data and Storage Devices and Data Stores Employing Such Devices
DE1524873B2 (de) * 1967-10-05 1970-12-23 Ibm Deutschland Monolithische integrierte Speicherzelle mit kleiner Ruheleistung
US3986178A (en) * 1975-07-28 1976-10-12 Texas Instruments Integrated injection logic random access memory
US4006458A (en) * 1976-02-09 1977-02-01 Rockwell International Corporation Detector circuit

Also Published As

Publication number Publication date
CA1134464A (en) 1982-10-26
FR2453414A1 (fr) 1980-10-31
FR2453414B1 (OSRAM) 1983-04-08
GB2047497A (en) 1980-11-26
US4297598A (en) 1981-10-27
GB2047497B (en) 1983-03-30
DE3012831A1 (de) 1980-10-16
JPS55135391A (en) 1980-10-22

Similar Documents

Publication Publication Date Title
DE3751171T2 (de) Ferro-elektrischer Speicher mit automatischer Wiederherstellung.
DE2313917C3 (de) Speicher mit redundanten Speicherstellen
DE4128919C2 (de) Halbleiterspeichereinrichtung und Verfahren zum Betrieb derselben
DE69322237T2 (de) Leseverstärker für einen integrierten Speicher
DE69835399T2 (de) SRAM Zelle mit einzelem Lesetor und zwei Toren zum Schreiben
DE69120448T2 (de) Halbleiterspeicheranordnungen von dynamischem Typus
DE19833570A1 (de) Mehrfachanschluß-Speicher, der eine Mehrzahl von Gruppen von Bitleitungen hat
DE69023783T2 (de) Statischer BICMOS-Speicher mit Funktionsstabilität.
DE3919625A1 (de) Halbleiterspeichereinrichtung mit geteilten wort- oder bitleitungstreibern und betriebsverfahren dafuer
DE4040492C2 (OSRAM)
DE69119957T2 (de) CMOS-Speichereinrichtung mit verbesserter Leseverstärker-Steuerung
DE10303702A1 (de) Magnetische Dünnfilmspeichervorrichtung mit einem von einer Mehrzahl von Zellen gemeinsam genutzten Zugriffselement
DE69317944T2 (de) Integrierte Speicherschaltung
DE2925925C2 (de) Informationsspeicher
DE2156805A1 (de) Monolithischer Speicher mit bipolaren Transistoren
DE69120447T2 (de) Halbleiterspeicheranordnung von dynamischem Typus
DE3012831C2 (de) Schaltung zum Nachweis kleiner Unterschiede zwischen der Größe erster und zweiter Eingangssignale
DE69022475T2 (de) Halbleiterspeichereinrichtung mit hoher Datenlesegeschwindigkeit.
DE69909202T2 (de) Anordnung und Verfahren für statischen RAMspeicher
DE10038228A1 (de) Zellenblockstruktur eines nichtflüchtigen ferroelektrischen Speichers
DE19963417A1 (de) Nichtflüchtiger ferroelektrischer Speicher
EP0020995B1 (de) Verfahren und Schaltungsanordnung zur Selektion und Entladung der Bitleitungskapazitäten für einen hochintegrierten MTL Halbleiterspeicher
DE2456708A1 (de) Assoziativspeicheranordnung
DE1960598A1 (de) MOS-Schnellesespeicher
DE68925181T2 (de) Digitales Speichersystem

Legal Events

Date Code Title Description
OD Request for examination
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee