DE2933849C2 - - Google Patents

Info

Publication number
DE2933849C2
DE2933849C2 DE2933849A DE2933849A DE2933849C2 DE 2933849 C2 DE2933849 C2 DE 2933849C2 DE 2933849 A DE2933849 A DE 2933849A DE 2933849 A DE2933849 A DE 2933849A DE 2933849 C2 DE2933849 C2 DE 2933849C2
Authority
DE
Germany
Prior art keywords
film
substrate
sio2
type
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE2933849A
Other languages
German (de)
English (en)
Other versions
DE2933849A1 (de
Inventor
Satoshi Kodaira Tokio/Tokyo Jp Meguro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE2933849A1 publication Critical patent/DE2933849A1/de
Application granted granted Critical
Publication of DE2933849C2 publication Critical patent/DE2933849C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment
    • H10P76/40—
    • H10W10/0127—
    • H10W10/13—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/07—Guard rings and cmos

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
DE19792933849 1978-08-23 1979-08-21 Verfahren zur herstellung von halbleiteranordnungen Granted DE2933849A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10179178A JPS5529116A (en) 1978-08-23 1978-08-23 Manufacture of complementary misic

Publications (2)

Publication Number Publication Date
DE2933849A1 DE2933849A1 (de) 1980-03-13
DE2933849C2 true DE2933849C2 (enExample) 1991-03-21

Family

ID=14309981

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19792933849 Granted DE2933849A1 (de) 1978-08-23 1979-08-21 Verfahren zur herstellung von halbleiteranordnungen

Country Status (3)

Country Link
US (1) US4268321A (enExample)
JP (1) JPS5529116A (enExample)
DE (1) DE2933849A1 (enExample)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5252505A (en) * 1979-05-25 1993-10-12 Hitachi, Ltd. Method for manufacturing a semiconductor device
JPS55156370A (en) * 1979-05-25 1980-12-05 Hitachi Ltd Manufacture of semiconductor device
JPS5691461A (en) * 1979-12-25 1981-07-24 Fujitsu Ltd Manufacturing of complementary mos integrated circuit
EP0052475A3 (en) * 1980-11-19 1983-12-21 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US4391650A (en) * 1980-12-22 1983-07-05 Ncr Corporation Method for fabricating improved complementary metal oxide semiconductor devices
NL187328C (nl) * 1980-12-23 1991-08-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
AT387474B (de) * 1980-12-23 1989-01-25 Philips Nv Verfahren zur herstellung einer halbleitervorrichtung
US4382827A (en) * 1981-04-27 1983-05-10 Ncr Corporation Silicon nitride S/D ion implant mask in CMOS device fabrication
DE3133468A1 (de) * 1981-08-25 1983-03-17 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen in siliziumgate-technologie
US4411058A (en) * 1981-08-31 1983-10-25 Hughes Aircraft Company Process for fabricating CMOS devices with self-aligned channel stops
US4420344A (en) * 1981-10-15 1983-12-13 Texas Instruments Incorporated CMOS Source/drain implant process without compensation of polysilicon doping
US4435896A (en) 1981-12-07 1984-03-13 Bell Telephone Laboratories, Incorporated Method for fabricating complementary field effect transistor devices
DE3149185A1 (de) 1981-12-11 1983-06-23 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung benachbarter mit dotierstoffionen implantierter wannen bei der herstellung von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
US4450021A (en) * 1982-02-22 1984-05-22 American Microsystems, Incorporated Mask diffusion process for forming Zener diode or complementary field effect transistors
US4454648A (en) * 1982-03-08 1984-06-19 Mcdonnell Douglas Corporation Method of making integrated MNOS and CMOS devices in a bulk silicon wafer
IT1210872B (it) * 1982-04-08 1989-09-29 Ates Componenti Elettron Processo per la fabbricazione di transistori mos complementari in circuiti integrati ad alta densita' per tensioni elevate.
US4412375A (en) * 1982-06-10 1983-11-01 Intel Corporation Method for fabricating CMOS devices with guardband
US4474624A (en) * 1982-07-12 1984-10-02 Intel Corporation Process for forming self-aligned complementary source/drain regions for MOS transistors
US4462151A (en) * 1982-12-03 1984-07-31 International Business Machines Corporation Method of making high density complementary transistors
DE3314450A1 (de) * 1983-04-21 1984-10-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
US4471523A (en) * 1983-05-02 1984-09-18 International Business Machines Corporation Self-aligned field implant for oxide-isolated CMOS FET
NL8501720A (nl) * 1985-06-14 1987-01-02 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een siliciumplak plaatselijk wordt voorzien van veldoxide met kanaalonderbreker.
US4729006A (en) * 1986-03-17 1988-03-01 International Business Machines Corporation Sidewall spacers for CMOS circuit stress relief/isolation and method for making
US4925806A (en) * 1988-03-17 1990-05-15 Northern Telecom Limited Method for making a doped well in a semiconductor substrate
IT1217372B (it) * 1988-03-28 1990-03-22 Sgs Thomson Microelectronics Procedimento per la programmazione di memorie rom in tecnologia mos ecmos
US5126279A (en) * 1988-12-19 1992-06-30 Micron Technology, Inc. Single polysilicon cross-coupled resistor, six-transistor SRAM cell design technique
EP0637073A1 (en) * 1993-07-29 1995-02-01 STMicroelectronics S.r.l. Process for realizing low threshold P-channel MOS transistors for complementary devices (CMOS)
US5982020A (en) 1997-04-28 1999-11-09 Lucent Technologies Inc. Deuterated bipolar transistor and method of manufacture thereof
US6252270B1 (en) 1997-04-28 2001-06-26 Agere Systems Guardian Corp. Increased cycle specification for floating-gate and method of manufacture thereof
US6023093A (en) * 1997-04-28 2000-02-08 Lucent Technologies Inc. Deuterated direlectric and polysilicon film-based semiconductor devices and method of manufacture thereof
US6090686A (en) * 1997-06-18 2000-07-18 Lucent Technologies, Inc. Locos isolation process using a layered pad nitride and dry field oxidation stack and semiconductor device employing the same
US6365511B1 (en) 1999-06-03 2002-04-02 Agere Systems Guardian Corp. Tungsten silicide nitride as a barrier for high temperature anneals to improve hot carrier reliability
US6576522B2 (en) 2000-12-08 2003-06-10 Agere Systems Inc. Methods for deuterium sintering
JP2003257883A (ja) * 2002-03-06 2003-09-12 Seiko Epson Corp 半導体装置の製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3853633A (en) * 1972-12-04 1974-12-10 Motorola Inc Method of making a semi planar insulated gate field-effect transistor device with implanted field
CA1001771A (en) * 1973-01-15 1976-12-14 Fairchild Camera And Instrument Corporation Method of mos transistor manufacture and resulting structure
US4027380A (en) * 1974-06-03 1977-06-07 Fairchild Camera And Instrument Corporation Complementary insulated gate field effect transistor structure and process for fabricating the structure
US4047285A (en) * 1975-05-08 1977-09-13 National Semiconductor Corporation Self-aligned CMOS for bulk silicon and insulating substrate device
US3983620A (en) * 1975-05-08 1976-10-05 National Semiconductor Corporation Self-aligned CMOS process for bulk silicon and insulating substrate device
JPS5286083A (en) * 1976-01-12 1977-07-16 Hitachi Ltd Production of complimentary isolation gate field effect transistor
US4013484A (en) * 1976-02-25 1977-03-22 Intel Corporation High density CMOS process
US4081896A (en) * 1977-04-11 1978-04-04 Rca Corporation Method of making a substrate contact for an integrated circuit
US4170492A (en) * 1978-04-18 1979-10-09 Texas Instruments Incorporated Method of selective oxidation in manufacture of semiconductor devices

Also Published As

Publication number Publication date
JPS6115594B2 (enExample) 1986-04-24
JPS5529116A (en) 1980-03-01
US4268321A (en) 1981-05-19
DE2933849A1 (de) 1980-03-13

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Legal Events

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OC Search report available
8128 New person/name/address of the agent

Representative=s name: STREHL, P., DIPL.-ING. DIPL.-WIRTSCH.-ING. SCHUEBE

8110 Request for examination paragraph 44
8125 Change of the main classification

Ipc: H01L 27/10

D2 Grant after examination
8364 No opposition during term of opposition