DE2928923C2 - - Google Patents

Info

Publication number
DE2928923C2
DE2928923C2 DE2928923A DE2928923A DE2928923C2 DE 2928923 C2 DE2928923 C2 DE 2928923C2 DE 2928923 A DE2928923 A DE 2928923A DE 2928923 A DE2928923 A DE 2928923A DE 2928923 C2 DE2928923 C2 DE 2928923C2
Authority
DE
Germany
Prior art keywords
region
implanted
insulating
polycrystalline silicon
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2928923A
Other languages
German (de)
English (en)
Other versions
DE2928923A1 (de
Inventor
Tetsushi Sayama Saitama Jp Sakai
Yoshiji Tokio/Tokyo Jp Kobayasi
Yousuke Musashino Tokio/Tokyo Jp Yamamoto
Hironori Asaka Saitama Jp Yamauchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP8799678A external-priority patent/JPS5515230A/ja
Priority claimed from JP8799778A external-priority patent/JPS5515231A/ja
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Publication of DE2928923A1 publication Critical patent/DE2928923A1/de
Application granted granted Critical
Publication of DE2928923C2 publication Critical patent/DE2928923C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)
DE19792928923 1978-07-19 1979-07-18 Halbleitervorrichtung Granted DE2928923A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8799678A JPS5515230A (en) 1978-07-19 1978-07-19 Semiconductor device and its manufacturing method
JP8799778A JPS5515231A (en) 1978-07-19 1978-07-19 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
DE2928923A1 DE2928923A1 (de) 1980-02-07
DE2928923C2 true DE2928923C2 (en, 2012) 1989-04-06

Family

ID=26429214

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19792928923 Granted DE2928923A1 (de) 1978-07-19 1979-07-18 Halbleitervorrichtung

Country Status (6)

Country Link
US (1) US4379001A (en, 2012)
CA (1) CA1129118A (en, 2012)
DE (1) DE2928923A1 (en, 2012)
FR (1) FR2433833A1 (en, 2012)
GB (1) GB2030002B (en, 2012)
NL (1) NL189102C (en, 2012)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3064143D1 (en) * 1979-12-03 1983-08-18 Ibm Process for producing a vertical pnp transistor and transistor so produced
JPS56146246A (en) * 1980-04-14 1981-11-13 Toshiba Corp Manufacture of semiconductor integrated circuit
US4438556A (en) * 1981-01-12 1984-03-27 Tokyo Shibaura Denki Kabushiki Kaisha Method of forming doped polycrystalline silicon pattern by selective implantation and plasma etching of undoped regions
JPS57194572A (en) * 1981-05-27 1982-11-30 Clarion Co Ltd Semiconductor device and manufacture thereof
US4465528A (en) * 1981-07-15 1984-08-14 Fujitsu Limited Method of producing a walled emitter semiconductor device
US4503601A (en) * 1983-04-18 1985-03-12 Ncr Corporation Oxide trench structure for polysilicon gates and interconnects
US4546535A (en) * 1983-12-12 1985-10-15 International Business Machines Corporation Method of making submicron FET structure
US4636834A (en) * 1983-12-12 1987-01-13 International Business Machines Corporation Submicron FET structure and method of making
US4551906A (en) * 1983-12-12 1985-11-12 International Business Machines Corporation Method for making self-aligned lateral bipolar transistors
NL8402223A (nl) * 1984-07-13 1986-02-03 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting en inrichting, vervaardigd door toepassing daarvan.
NL8402859A (nl) * 1984-09-18 1986-04-16 Philips Nv Werkwijze voor het vervaardigen van submicrongroeven in bijvoorbeeld halfgeleidermateriaal en met deze werkwijze verkregen inrichtingen.
NL8700640A (nl) * 1987-03-18 1988-10-17 Philips Nv Halfgeleiderinrichting en werkwijze ter vervaardiging daarvan.
US4745079A (en) * 1987-03-30 1988-05-17 Motorola, Inc. Method for fabricating MOS transistors having gates with different work functions
US5675164A (en) * 1995-06-07 1997-10-07 International Business Machines Corporation High performance multi-mesa field effect transistor
KR100329605B1 (ko) * 1995-09-25 2002-11-04 주식회사 하이닉스반도체 반도체소자의금속배선제조방법
US6309975B1 (en) 1997-03-14 2001-10-30 Micron Technology, Inc. Methods of making implanted structures
US7247578B2 (en) * 2003-12-30 2007-07-24 Intel Corporation Method of varying etch selectivities of a film
US20090170331A1 (en) * 2007-12-27 2009-07-02 International Business Machines Corporation Method of forming a bottle-shaped trench by ion implantation
KR101631165B1 (ko) * 2009-12-14 2016-06-17 삼성전자주식회사 반도체 셀 구조체의 형성방법, 상기 반도체 셀 구조체를 포함하는 반도체 장치의 형성 방법 및 상기 반도체 장치를 포함하는 반도체 모듈의 형성방법
FR3051964B1 (fr) * 2016-05-27 2018-11-09 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de formation d’un motif de guidage fonctionnalise pour un procede de grapho-epitaxie
FR3051965A1 (fr) 2016-05-27 2017-12-01 Commissariat Energie Atomique Procede de formation d’un motif de guidage fonctionnalise pour un procede de grapho-epitaxie
FR3051966B1 (fr) 2016-05-27 2018-11-09 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de formation d’un motif de guidage fonctionnalise pour un procede de grapho-epitaxie
CN110471099B (zh) * 2019-06-28 2023-03-10 上海芬创信息科技有限公司 一种离子传感器及其制备方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1417170A (en) 1972-12-22 1975-12-10 Mullard Ltd Methods of manufacturing semiconductor devices
US4074304A (en) * 1974-10-04 1978-02-14 Nippon Electric Company, Ltd. Semiconductor device having a miniature junction area and process for fabricating same
JPS5928992B2 (ja) * 1975-02-14 1984-07-17 日本電信電話株式会社 Ｍｏｓトランジスタおよびその製造方法
JPS51127682A (en) * 1975-04-30 1976-11-06 Fujitsu Ltd Manufacturing process of semiconductor device
US4162506A (en) * 1976-04-27 1979-07-24 Tokyo Shibaura Electric Co., Ltd. Semiconductor integrated circuit device with dual thickness poly-silicon wiring
JPS539469A (en) * 1976-07-15 1978-01-27 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device having electrode of stepped structure and its production
NL7703941A (nl) * 1977-04-12 1978-10-16 Philips Nv Werkwijze ter vervaardiging van een halfgelei- derinrichting en inrichting, vervaardigd door toepassing van de werkwijze.
JPS53132275A (en) * 1977-04-25 1978-11-17 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and its production
FR2417853A1 (fr) * 1978-02-17 1979-09-14 Thomson Csf Procede de realisation d'un transistor de type mos et transistor realise selon ce procede
JPS54140483A (en) * 1978-04-21 1979-10-31 Nec Corp Semiconductor device
US4157269A (en) * 1978-06-06 1979-06-05 International Business Machines Corporation Utilizing polysilicon diffusion sources and special masking techniques
US4290185A (en) * 1978-11-03 1981-09-22 Mostek Corporation Method of making an extremely low current load device for integrated circuit
JPS5586151A (en) * 1978-12-23 1980-06-28 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor integrated circuit
US4274891A (en) * 1979-06-29 1981-06-23 International Business Machines Corporation Method of fabricating buried injector memory cell formed from vertical complementary bipolar transistor circuits utilizing mono-poly deposition
US4234357A (en) * 1979-07-16 1980-11-18 Trw Inc. Process for manufacturing emitters by diffusion from polysilicon
US4240845A (en) * 1980-02-04 1980-12-23 International Business Machines Corporation Method of fabricating random access memory device

Also Published As

Publication number Publication date
NL7905607A (nl) 1980-01-22
US4379001A (en) 1983-04-05
FR2433833B1 (en, 2012) 1984-01-13
DE2928923A1 (de) 1980-02-07
GB2030002A (en) 1980-03-26
CA1129118A (en) 1982-08-03
FR2433833A1 (fr) 1980-03-14
NL189102B (nl) 1992-08-03
GB2030002B (en) 1983-03-30
NL189102C (nl) 1993-01-04

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Legal Events

Date Code Title Description
OAP Request for examination filed
OD Request for examination
8127 New person/name/address of the applicant

Owner name: NIPPON TELEGRAPH AND TELEPHONE CORP., TOKIO/TOKYO,

D2 Grant after examination
8364 No opposition during term of opposition