DE2849373C2 - - Google Patents

Info

Publication number
DE2849373C2
DE2849373C2 DE2849373A DE2849373A DE2849373C2 DE 2849373 C2 DE2849373 C2 DE 2849373C2 DE 2849373 A DE2849373 A DE 2849373A DE 2849373 A DE2849373 A DE 2849373A DE 2849373 C2 DE2849373 C2 DE 2849373C2
Authority
DE
Germany
Prior art keywords
layer
insulating layer
semiconductor
silicon layer
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2849373A
Other languages
German (de)
English (en)
Other versions
DE2849373A1 (de
Inventor
Masashi Ikeda
Kazuo Tokio/Tokyo Jp Kihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP13575277A external-priority patent/JPS5469079A/ja
Priority claimed from JP52135754A external-priority patent/JPS6022829B2/ja
Priority claimed from JP52135753A external-priority patent/JPS6022828B2/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE2849373A1 publication Critical patent/DE2849373A1/de
Application granted granted Critical
Publication of DE2849373C2 publication Critical patent/DE2849373C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H10D10/054—Forming extrinsic base regions on silicon substrate after insulating device isolation in vertical BJTs having single crystalline emitter, collector or base regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/40—Vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10P14/24—
    • H10P14/271—
    • H10P14/2905—
    • H10P14/3211—
    • H10P14/3411—
    • H10P32/1414—
    • H10P32/171—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/124—Polycrystalline emitter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/969—Simultaneous formation of monocrystalline and polycrystalline regions

Landscapes

  • Bipolar Transistors (AREA)
DE19782849373 1977-11-14 1978-11-14 Verfahren zur herstellung einer halbleitervorrichtung Granted DE2849373A1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP13575277A JPS5469079A (en) 1977-11-14 1977-11-14 Manufacture of semiconductor device
JP52135754A JPS6022829B2 (ja) 1977-11-14 1977-11-14 半導体装置の製造方法
JP52135753A JPS6022828B2 (ja) 1977-11-14 1977-11-14 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE2849373A1 DE2849373A1 (de) 1979-05-17
DE2849373C2 true DE2849373C2 (cg-RX-API-DMAC10.html) 1988-11-17

Family

ID=27317143

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19782849373 Granted DE2849373A1 (de) 1977-11-14 1978-11-14 Verfahren zur herstellung einer halbleitervorrichtung

Country Status (3)

Country Link
US (1) US4190949A (cg-RX-API-DMAC10.html)
DE (1) DE2849373A1 (cg-RX-API-DMAC10.html)
GB (1) GB2010580B (cg-RX-API-DMAC10.html)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7900280A (nl) * 1979-01-15 1980-07-17 Philips Nv Halfgeleiderinrichting en werkwijze ter vervaardiging daarvan.
JPS561556A (en) * 1979-06-18 1981-01-09 Hitachi Ltd Semiconductor device
US4274891A (en) * 1979-06-29 1981-06-23 International Business Machines Corporation Method of fabricating buried injector memory cell formed from vertical complementary bipolar transistor circuits utilizing mono-poly deposition
DE3016553A1 (de) * 1980-04-29 1981-11-05 Siemens AG, 1000 Berlin und 8000 München Planartransistor, insbesondere fuer i(pfeil hoch)2(pfeil hoch) l-strukturen
US4418468A (en) * 1981-05-08 1983-12-06 Fairchild Camera & Instrument Corporation Process for fabricating a logic structure utilizing polycrystalline silicon Schottky diodes
JPS59186367A (ja) * 1983-04-06 1984-10-23 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US4523370A (en) * 1983-12-05 1985-06-18 Ncr Corporation Process for fabricating a bipolar transistor with a thin base and an abrupt base-collector junction
US4706378A (en) * 1985-01-30 1987-11-17 Texas Instruments Incorporated Method of making vertical bipolar transistor having base above buried nitride dielectric formed by deep implantation
US4644383A (en) * 1985-04-08 1987-02-17 Harris Corporation Subcollector for oxide and junction isolated IC's
JPH0719838B2 (ja) * 1985-07-19 1995-03-06 松下電器産業株式会社 半導体装置およびその製造方法
KR900007686B1 (ko) * 1986-10-08 1990-10-18 후지쓰 가부시끼가이샤 선택적으로 산화된 실리콘 기판상에 에피택셜 실리콘층과 다결정 실리콘층을 동시에 성장시키는 기상 증착방법
GB2243716B (en) * 1988-11-02 1993-05-05 Hughes Aircraft Co Self-aligned,planar heterojunction bipolar transistor and method of forming the same
US5159423A (en) * 1988-11-02 1992-10-27 Hughes Aircraft Company Self-aligned, planar heterojunction bipolar transistor
US5146304A (en) * 1988-12-22 1992-09-08 Honeywell Inc. Self-aligned semiconductor device
US5061644A (en) * 1988-12-22 1991-10-29 Honeywell Inc. Method for fabricating self-aligned semiconductor devices
JPH10303195A (ja) * 1997-04-23 1998-11-13 Toshiba Corp 半導体装置の製造方法
US8729662B2 (en) * 2008-09-12 2014-05-20 Semiconductor Components Industries, Llc Semiconductor device and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3796613A (en) * 1971-06-18 1974-03-12 Ibm Method of forming dielectric isolation for high density pedestal semiconductor devices

Also Published As

Publication number Publication date
GB2010580B (en) 1982-06-30
US4190949A (en) 1980-03-04
GB2010580A (en) 1979-06-27
DE2849373A1 (de) 1979-05-17

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Legal Events

Date Code Title Description
OAP Request for examination filed
OD Request for examination
8128 New person/name/address of the agent

Representative=s name: HENKEL, G., DR.PHIL. FEILER, L., DR.RER.NAT. HAENZ

8127 New person/name/address of the applicant

Owner name: KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee