DE69025899T2 - Verfahren zur Herstellung einer integrierten Halbleiterschaltung - Google Patents

Verfahren zur Herstellung einer integrierten Halbleiterschaltung

Info

Publication number
DE69025899T2
DE69025899T2 DE1990625899 DE69025899T DE69025899T2 DE 69025899 T2 DE69025899 T2 DE 69025899T2 DE 1990625899 DE1990625899 DE 1990625899 DE 69025899 T DE69025899 T DE 69025899T DE 69025899 T2 DE69025899 T2 DE 69025899T2
Authority
DE
Germany
Prior art keywords
manufacturing
integrated circuit
semiconductor integrated
semiconductor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE1990625899
Other languages
English (en)
Other versions
DE69025899D1 (de
Inventor
Kazuo Takeda
Nobuyuki Sekikawa
Teruo Tabata
Yoshiaki Sano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP1340810A external-priority patent/JP3036768B2/ja
Priority claimed from JP1340816A external-priority patent/JPH03201443A/ja
Priority claimed from JP1340813A external-priority patent/JP3036769B2/ja
Priority claimed from JP1340814A external-priority patent/JP3036770B2/ja
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of DE69025899D1 publication Critical patent/DE69025899D1/de
Application granted granted Critical
Publication of DE69025899T2 publication Critical patent/DE69025899T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8224—Bipolar technology comprising a combination of vertical and lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8226—Bipolar technology comprising merged transistor logic or integrated injection logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Bipolar Integrated Circuits (AREA)
DE1990625899 1989-12-28 1990-12-27 Verfahren zur Herstellung einer integrierten Halbleiterschaltung Expired - Lifetime DE69025899T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP1340810A JP3036768B2 (ja) 1989-12-28 1989-12-28 半導体集積回路の製造方法
JP1340816A JPH03201443A (ja) 1989-12-28 1989-12-28 半導体集積回路の製造方法
JP1340813A JP3036769B2 (ja) 1989-12-28 1989-12-28 半導体集積回路の製造方法
JP1340814A JP3036770B2 (ja) 1989-12-28 1989-12-28 半導体集積回路の製造方法

Publications (2)

Publication Number Publication Date
DE69025899D1 DE69025899D1 (de) 1996-04-18
DE69025899T2 true DE69025899T2 (de) 1996-09-19

Family

ID=27480593

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1990625899 Expired - Lifetime DE69025899T2 (de) 1989-12-28 1990-12-27 Verfahren zur Herstellung einer integrierten Halbleiterschaltung

Country Status (2)

Country Link
EP (1) EP0437834B1 (de)
DE (1) DE69025899T2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5254486A (en) * 1992-02-21 1993-10-19 Micrel, Incorporated Method for forming PNP and NPN bipolar transistors in the same substrate
FR2687843A1 (fr) * 1992-02-24 1993-08-27 Motorola Semiconducteurs Transistor bipolaire lateral pnp et procede de fabrication.

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3915766A (en) * 1972-05-31 1975-10-28 Texas Instruments Inc Composition for use in forming a doped oxide film
FR2260186A1 (en) * 1974-02-04 1975-08-29 Radiotechnique Compelec Semiconductor device mfr. with two or more zones - of different characteristics using successive masking and ion implantation technique
US3933528A (en) * 1974-07-02 1976-01-20 Texas Instruments Incorporated Process for fabricating integrated circuits utilizing ion implantation
US4110126A (en) * 1977-08-31 1978-08-29 International Business Machines Corporation NPN/PNP Fabrication process with improved alignment
US4201800A (en) * 1978-04-28 1980-05-06 International Business Machines Corp. Hardened photoresist master image mask process
CN1004456B (zh) * 1985-04-19 1989-06-07 三洋电机株式会社 半导体器件及其制造方法

Also Published As

Publication number Publication date
DE69025899D1 (de) 1996-04-18
EP0437834A1 (de) 1991-07-24
EP0437834B1 (de) 1996-03-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition