DE69015721D1 - Verfahren zur Herstellung einer supraleitenden Schaltung. - Google Patents

Verfahren zur Herstellung einer supraleitenden Schaltung.

Info

Publication number
DE69015721D1
DE69015721D1 DE69015721T DE69015721T DE69015721D1 DE 69015721 D1 DE69015721 D1 DE 69015721D1 DE 69015721 T DE69015721 T DE 69015721T DE 69015721 T DE69015721 T DE 69015721T DE 69015721 D1 DE69015721 D1 DE 69015721D1
Authority
DE
Germany
Prior art keywords
manufacturing
superconducting circuit
superconducting
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69015721T
Other languages
English (en)
Other versions
DE69015721T2 (de
Inventor
Shoji Shiga
Koki Sato
Nakahiro Harada
Kiyoshi Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Electric Co Ltd
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Publication of DE69015721D1 publication Critical patent/DE69015721D1/de
Application granted granted Critical
Publication of DE69015721T2 publication Critical patent/DE69015721T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/01Manufacture or treatment
    • H10N60/0268Manufacture or treatment of devices comprising copper oxide
    • H10N60/0661Processes performed after copper oxide formation, e.g. patterning
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Superconductors And Manufacturing Methods Therefor (AREA)
DE69015721T 1989-07-24 1990-07-24 Verfahren zur Herstellung einer supraleitenden Schaltung. Expired - Fee Related DE69015721T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1191019A JPH0354875A (ja) 1989-07-24 1989-07-24 超電導体回路の形成方法

Publications (2)

Publication Number Publication Date
DE69015721D1 true DE69015721D1 (de) 1995-02-16
DE69015721T2 DE69015721T2 (de) 1995-06-01

Family

ID=16267535

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69015721T Expired - Fee Related DE69015721T2 (de) 1989-07-24 1990-07-24 Verfahren zur Herstellung einer supraleitenden Schaltung.

Country Status (4)

Country Link
EP (1) EP0410373B1 (de)
JP (1) JPH0354875A (de)
KR (1) KR910003751A (de)
DE (1) DE69015721T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03166776A (ja) * 1989-11-27 1991-07-18 Sumitomo Electric Ind Ltd トンネル接合素子とその作製方法
KR930004024B1 (ko) * 1990-04-27 1993-05-19 삼성전기 주식회사 초전도 집적회로소자의 제조방법
EP0475838B1 (de) * 1990-09-10 1996-03-06 Sumitomo Electric Industries, Ltd. Supraleitende Einrichtung mit einer reduzierten Dicke der supraleitenden Schicht und Methode zu deren Herstellung
DE69219192T2 (de) * 1991-03-28 1997-09-11 Sumitomo Electric Industries Verfahren zur Herstellung einer Schichtstruktur mit mindestens einer dünnen Schicht aus Supraleiteroxyd
DE4120766A1 (de) * 1991-06-24 1993-01-14 Forschungszentrum Juelich Gmbh Verfahren zur herstellung von strukturierten leiterbahnen
US6027564A (en) * 1997-09-23 2000-02-22 American Superconductor Corporation Low vacuum vapor process for producing epitaxial layers
US6022832A (en) 1997-09-23 2000-02-08 American Superconductor Corporation Low vacuum vapor process for producing superconductor articles with epitaxial layers
US6428635B1 (en) 1997-10-01 2002-08-06 American Superconductor Corporation Substrates for superconductors
US6458223B1 (en) 1997-10-01 2002-10-01 American Superconductor Corporation Alloy materials
US6475311B1 (en) 1999-03-31 2002-11-05 American Superconductor Corporation Alloy materials
ES2374734T3 (es) 2005-12-09 2012-02-21 Federal-Mogul S.A. Dispositivo limpiaparabrisas.
JP5806302B2 (ja) * 2010-06-24 2015-11-10 ユニバーシティー オブ ヒューストン システム 交流損失を低減したマルチフィラメント超伝導体とその形成方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3850580T2 (de) * 1987-01-30 1994-10-27 Hitachi Ltd Supraleiteranordnung.
JPS63250880A (ja) * 1987-04-08 1988-10-18 Semiconductor Energy Lab Co Ltd 酸化物超電導材料
JPS63291485A (ja) * 1987-05-25 1988-11-29 Fujikura Ltd 酸化物超電導回路の製造方法
JPS6455880A (en) * 1987-08-27 1989-03-02 Fujitsu Ltd Manufacture of device having superconductive thin film
JPS6489342A (en) * 1987-09-29 1989-04-03 Sony Corp Manufacture of semiconductor device
JPH01102976A (ja) * 1987-10-15 1989-04-20 Nec Corp 酸化物高温超伝導体薄膜パターン形成方法
JPH02260676A (ja) * 1989-03-31 1990-10-23 Toshiba Corp 超電導体装置の製造方法

Also Published As

Publication number Publication date
JPH0354875A (ja) 1991-03-08
KR910003751A (ko) 1991-02-28
EP0410373A2 (de) 1991-01-30
DE69015721T2 (de) 1995-06-01
EP0410373B1 (de) 1995-01-04
EP0410373A3 (en) 1991-05-29

Similar Documents

Publication Publication Date Title
DE69015216D1 (de) Verfahren zur Herstellung einer Halbleitervorrichtung.
DE69032773T2 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE69023558T2 (de) Verfahren zur Herstellung einer Halbleitervorrichtung.
DE68924366T2 (de) Verfahren zur Herstellung einer Halbleitervorrichtung.
DE68907507T2 (de) Verfahren zur Herstellung einer Halbleitervorrichtung.
DE69016955D1 (de) Verfahren zur Herstellung einer Halbleiteranordnung.
DE3850609D1 (de) Methode zur Herstellung einer supraleitenden Schaltung.
DE69030709T2 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE3851248T2 (de) Verfahren zur Herstellung einer supraleitenden Schaltung.
DE3789369D1 (de) Verfahren zur Herstellung einer keramischen Schaltungsplatte.
DE69015721T2 (de) Verfahren zur Herstellung einer supraleitenden Schaltung.
DE69031702D1 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE68923730D1 (de) Verfahren zur Herstellung einer bipolaren integrierten Schaltung.
DE69015879D1 (de) Verfahren zur Herstellung einer oberflächenmontierbaren Leiterplatte.
DE68927376D1 (de) Verfahren zur Herstellung einer Buchse für eine integrierte Schaltung
DE69031153T2 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE69017245T2 (de) Verfahren zur Herstellung einer Verbundstruktur.
DE69033515D1 (de) Verfahren zur Herstellung einer integrierten Schaltung
DE3889015T2 (de) Verfahren zur Herstellung einer supraleitenden Schaltung.
DE69017803D1 (de) Verfahren zur Herstellung einer Halbleiterspeicheranordnung.
DE69013851D1 (de) Verfahren zur Herstellung einer keramischen Schaltungsplatte.
DE69024859D1 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE69108957D1 (de) Verfahren zur Herstellung einer Halbleitervorrichtung.
DE68911748D1 (de) Verfahren zur Herstellung einer Halbleitervorrichtung.
DE59003509D1 (de) Verfahren zur Herstellung einer Sintervorrichtung.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee