DE2647394C2 - MOS-Halbleiterspeicherbaustein - Google Patents

MOS-Halbleiterspeicherbaustein

Info

Publication number
DE2647394C2
DE2647394C2 DE2647394A DE2647394A DE2647394C2 DE 2647394 C2 DE2647394 C2 DE 2647394C2 DE 2647394 A DE2647394 A DE 2647394A DE 2647394 A DE2647394 A DE 2647394A DE 2647394 C2 DE2647394 C2 DE 2647394C2
Authority
DE
Germany
Prior art keywords
bit lines
memory
memory cell
evaluation circuit
evaluation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2647394A
Other languages
German (de)
English (en)
Other versions
DE2647394B1 (de
Inventor
Paul-Werner V. Dipl.-Ing. 8190 Wolfratshausen Basse
Ruediger Dr. 8000 Muenchen Hofmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE2647394A priority Critical patent/DE2647394C2/de
Priority to US05/837,201 priority patent/US4122546A/en
Priority to FR7731288A priority patent/FR2368783A1/fr
Priority to GB43446/77A priority patent/GB1593866A/en
Priority to JP52125635A priority patent/JPS6057159B2/ja
Publication of DE2647394B1 publication Critical patent/DE2647394B1/de
Application granted granted Critical
Publication of DE2647394C2 publication Critical patent/DE2647394C2/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE2647394A 1976-10-20 1976-10-20 MOS-Halbleiterspeicherbaustein Expired DE2647394C2 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE2647394A DE2647394C2 (de) 1976-10-20 1976-10-20 MOS-Halbleiterspeicherbaustein
US05/837,201 US4122546A (en) 1976-10-20 1977-09-27 MOS Semiconductor storage module
FR7731288A FR2368783A1 (fr) 1976-10-20 1977-10-18 Module de memoire a semiconducteurs mos
GB43446/77A GB1593866A (en) 1976-10-20 1977-10-19 Mos semiconductor storage modules
JP52125635A JPS6057159B2 (ja) 1976-10-20 1977-10-19 Ｍｏｓ半導体記憶器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2647394A DE2647394C2 (de) 1976-10-20 1976-10-20 MOS-Halbleiterspeicherbaustein

Publications (2)

Publication Number Publication Date
DE2647394B1 DE2647394B1 (de) 1978-03-16
DE2647394C2 true DE2647394C2 (de) 1978-11-16

Family

ID=5990933

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2647394A Expired DE2647394C2 (de) 1976-10-20 1976-10-20 MOS-Halbleiterspeicherbaustein

Country Status (5)

Country Link
US (1) US4122546A (show.php)
JP (1) JPS6057159B2 (show.php)
DE (1) DE2647394C2 (show.php)
FR (1) FR2368783A1 (show.php)
GB (1) GB1593866A (show.php)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2904994A1 (de) * 1979-02-09 1980-08-21 Siemens Ag Mos-halbleiterbaustein mit zwischen wort- und bitleitungen angeordneten mos- transistorspeicherzellen

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54148340A (en) * 1978-05-12 1979-11-20 Nec Corp Memory circuit
JPS5817998B2 (ja) * 1978-10-26 1983-04-11 富士通株式会社 半導体メモリ
JPS5558890A (en) * 1978-10-27 1980-05-01 Hitachi Ltd Reference voltage generation circuit
DE2855118C2 (de) * 1978-12-20 1981-03-26 IBM Deutschland GmbH, 70569 Stuttgart Dynamischer FET-Speicher
DE2926514A1 (de) * 1979-06-30 1981-01-15 Ibm Deutschland Elektrische speicheranordnung und verfahren zu ihrem betrieb
JPS5683891A (en) * 1979-12-13 1981-07-08 Fujitsu Ltd Semiconductor storage device
US4287576A (en) * 1980-03-26 1981-09-01 International Business Machines Corporation Sense amplifying system for memories with small cells
USRE32682E (en) * 1980-10-10 1988-05-31 Inmos Corporation Folded bit line-shared sense amplifiers
US4351034A (en) * 1980-10-10 1982-09-21 Inmos Corporation Folded bit line-shared sense amplifiers
DE3101802A1 (de) * 1981-01-21 1982-08-19 Siemens AG, 1000 Berlin und 8000 München Monolithisch integrierter halbleiterspeicher
JPS57198592A (en) * 1981-05-29 1982-12-06 Hitachi Ltd Semiconductor memory device
JPS58111183A (ja) * 1981-12-25 1983-07-02 Hitachi Ltd ダイナミツクｒａｍ集積回路装置
JPS60234295A (ja) * 1984-05-04 1985-11-20 Fujitsu Ltd 半導体記憶装置
KR900005667B1 (ko) * 1984-11-20 1990-08-03 후지쓰 가부시끼가이샤 반도체 기억장치
JPS61178795A (ja) * 1985-02-01 1986-08-11 Toshiba Corp ダイナミツク型半導体記憶装置
JPS61296598A (ja) * 1985-06-21 1986-12-27 Mitsubishi Electric Corp Ｍｏｓダイナミツクｒａｍのダミ−ワ−ド線駆動回路
JPS6282597A (ja) * 1985-10-08 1987-04-16 Fujitsu Ltd 半導体記憶装置
JPS62197992A (ja) * 1986-02-25 1987-09-01 Mitsubishi Electric Corp ダイナミツクｒａｍ
JPS62200596A (ja) * 1986-02-26 1987-09-04 Mitsubishi Electric Corp 半導体メモリ
JPH07111823B2 (ja) * 1986-03-18 1995-11-29 三菱電機株式会社 半導体記憶装置
US4731747A (en) * 1986-04-14 1988-03-15 American Telephone And Telegraph Company, At&T Bell Laboratories Highly parallel computation network with normalized speed of response
JPH07107797B2 (ja) * 1987-02-10 1995-11-15 三菱電機株式会社 ダイナミツクランダムアクセスメモリ
JPS63146295A (ja) * 1987-11-18 1988-06-18 Toshiba Corp 半導体メモリ
JP2566517B2 (ja) * 1993-04-28 1996-12-25 三菱電機株式会社 ダイナミック型半導体記憶装置
JP3025103U (ja) * 1995-11-22 1996-06-11 株式会社マックエイト 電子部品の印刷配線板への取付構造
TWI291699B (en) * 2005-05-26 2007-12-21 Macronix Int Co Ltd Method of reading the bits of nitride read-only memory cell
KR102160178B1 (ko) * 2016-08-31 2020-09-28 마이크론 테크놀로지, 인크 메모리 어레이

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3983545A (en) * 1975-06-30 1976-09-28 International Business Machines Corporation Random access memory employing single ended sense latch for one device cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2904994A1 (de) * 1979-02-09 1980-08-21 Siemens Ag Mos-halbleiterbaustein mit zwischen wort- und bitleitungen angeordneten mos- transistorspeicherzellen

Also Published As

Publication number Publication date
DE2647394B1 (de) 1978-03-16
FR2368783A1 (fr) 1978-05-19
FR2368783B1 (show.php) 1984-05-04
US4122546A (en) 1978-10-24
GB1593866A (en) 1981-07-22
JPS5350944A (en) 1978-05-09
JPS6057159B2 (ja) 1985-12-13

Similar Documents

Publication Publication Date Title
DE2647394C2 (de) MOS-Halbleiterspeicherbaustein
DE4308665B4 (de) DRAM mit einer bidirektionalen globalen Bitleitung
DE68919393T2 (de) Nichtflüchtige Speicherzelle und Verfahren zum Lesen.
DE4036091C2 (de) Dynamischer Halbleiterspeicher mit wahlfreiem Zugriff
DE3923629C2 (de) DRAM-Halbleiterbaustein
DE3932442A1 (de) Halbleiterspeicheranordnung
DE4138340C2 (de) Halbleiterspeichervorrichtung und Verfahren zum Betreiben einer solchen
DE2527486B2 (de) Verfahren zur Prüfung bistabiler Speicherzellen
EP0387379A1 (de) Integrierter Halbleiterspeicher vom Typ DRAM und Verfahren zu seinem Testen
DE2635028A1 (de) Auf einem halbleiterplaettchen integriertes speichersystem
DE19756929B4 (de) Zellenarray und Leseverstärkerstruktur mit verbesserten Rauscheigenschaften und verringerter Größe
DE3236729C2 (show.php)
DE2707456B2 (de) Dynamischer RAM-Speicher
DE3939849A1 (de) Halbleiterspeichereinrichtung mit einem geteilten leseverstaerker und verfahren zu deren betrieb
EP1099224B1 (de) Schaltungsanordnung zur generierung einer referenzspannung für das auslesen eines ferroelektrischen speichers
DE2041959A1 (de) Randomspeicher
EP0224887A1 (de) Gate Array Anordnung in CMOS-Technik
DE2101180C3 (show.php)
DE2022256C2 (de) Festwertspeicher- und Decoderanordnung
DE69615712T2 (de) Zellengegenplatteneinstellung für dram-leseoperation
DE1186509B (de) Magnetspeicher mit einem mit zueinander senkrechten Bohrungen versehenen Magnetkern
DE1449806A1 (de) Matrixspeicher
DE19952311B4 (de) Integrierter Speicher mit Speicherzellen vom 2-Transistor/2-Kondensator-Typ
DE10139724B4 (de) Integrierter dynamischer Speicher mit Speicherzellen in mehreren Speicherbänken und Verfahren zum Betrieb eines solchen Speichers
DE2946633C2 (show.php)

Legal Events

Date Code Title Description
B1 Publication of the examined application without previous publication of unexamined application
C2 Grant after previous publication (2nd publication)