DE2623219B2 - Verfahren zum Betreiben einer Leseverstärkerschaltung für einen dynamischen MOS-Speicher und Anordnung zur Durchführung dieses Verfahrens - Google Patents

Verfahren zum Betreiben einer Leseverstärkerschaltung für einen dynamischen MOS-Speicher und Anordnung zur Durchführung dieses Verfahrens

Info

Publication number
DE2623219B2
DE2623219B2 DE2623219A DE2623219A DE2623219B2 DE 2623219 B2 DE2623219 B2 DE 2623219B2 DE 2623219 A DE2623219 A DE 2623219A DE 2623219 A DE2623219 A DE 2623219A DE 2623219 B2 DE2623219 B2 DE 2623219B2
Authority
DE
Germany
Prior art keywords
transistor
node
voltage
switching
controlled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE2623219A
Other languages
German (de)
English (en)
Other versions
DE2623219A1 (de
DE2623219C3 (enrdf_load_stackoverflow
Inventor
Klaus Dipl.-Ing. Dr. 8021 Hohenschaeftlarn Zibert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE2623219A priority Critical patent/DE2623219B2/de
Priority to US05/798,431 priority patent/US4119870A/en
Priority to FR7715513A priority patent/FR2353116A1/fr
Priority to GB21585/77A priority patent/GB1587129A/en
Priority to JP52060391A priority patent/JPS6044748B2/ja
Publication of DE2623219A1 publication Critical patent/DE2623219A1/de
Publication of DE2623219B2 publication Critical patent/DE2623219B2/de
Application granted granted Critical
Publication of DE2623219C3 publication Critical patent/DE2623219C3/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356026—Bistable circuits using additional transistors in the input circuit with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356069—Bistable circuits using additional transistors in the feedback circuit
    • H03K3/356078—Bistable circuits using additional transistors in the feedback circuit with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356086—Bistable circuits with additional means for controlling the main nodes
    • H03K3/356095—Bistable circuits with additional means for controlling the main nodes with synchronous operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
DE2623219A 1976-05-24 1976-05-24 Verfahren zum Betreiben einer Leseverstärkerschaltung für einen dynamischen MOS-Speicher und Anordnung zur Durchführung dieses Verfahrens Granted DE2623219B2 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE2623219A DE2623219B2 (de) 1976-05-24 1976-05-24 Verfahren zum Betreiben einer Leseverstärkerschaltung für einen dynamischen MOS-Speicher und Anordnung zur Durchführung dieses Verfahrens
US05/798,431 US4119870A (en) 1976-05-24 1977-05-19 Read-out amplifier circuit for a dynamic MOS memory
FR7715513A FR2353116A1 (fr) 1976-05-24 1977-05-20 Circuit amplificateur de lecture pour une memoire mos dynamique
GB21585/77A GB1587129A (en) 1976-05-24 1977-05-23 Dynamic mos-store read-out circuits
JP52060391A JPS6044748B2 (ja) 1976-05-24 1977-05-24 ダイナミツクｍｏｓ記憶器に対する読出し増幅回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2623219A DE2623219B2 (de) 1976-05-24 1976-05-24 Verfahren zum Betreiben einer Leseverstärkerschaltung für einen dynamischen MOS-Speicher und Anordnung zur Durchführung dieses Verfahrens

Publications (3)

Publication Number Publication Date
DE2623219A1 DE2623219A1 (de) 1977-12-01
DE2623219B2 true DE2623219B2 (de) 1978-10-12
DE2623219C3 DE2623219C3 (enrdf_load_stackoverflow) 1979-06-13

Family

ID=5978869

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2623219A Granted DE2623219B2 (de) 1976-05-24 1976-05-24 Verfahren zum Betreiben einer Leseverstärkerschaltung für einen dynamischen MOS-Speicher und Anordnung zur Durchführung dieses Verfahrens

Country Status (5)

Country Link
US (1) US4119870A (enrdf_load_stackoverflow)
JP (1) JPS6044748B2 (enrdf_load_stackoverflow)
DE (1) DE2623219B2 (enrdf_load_stackoverflow)
FR (1) FR2353116A1 (enrdf_load_stackoverflow)
GB (1) GB1587129A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3710821A1 (de) * 1986-04-01 1987-10-15 Toshiba Kawasaki Kk Halbleiterspeichereinrichtung

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4286178A (en) * 1978-06-12 1981-08-25 Texas Instruments Incorporated Sense amplifier with dual parallel driver transistors in MOS random access memory
US4168490A (en) * 1978-06-26 1979-09-18 Fairchild Camera And Instrument Corporation Addressable word line pull-down circuit
DE2839073C2 (de) * 1978-09-07 1983-02-17 Siemens AG, 1000 Berlin und 8000 München Dynamische Stromquelle für Halbleiterbausteine und ihre Verwendung
US4543501A (en) * 1978-09-22 1985-09-24 Texas Instruments Incorporated High performance dynamic sense amplifier with dual channel grounding transistor
US4255679A (en) * 1978-10-30 1981-03-10 Texas Instruments Incorporated Depletion load dynamic sense amplifier for MOS random access memory
US4296335A (en) * 1979-06-29 1981-10-20 General Electric Company High voltage standoff MOS driver circuitry
JPS6014438B2 (ja) * 1979-08-29 1985-04-13 株式会社東芝 不揮発性半導体メモリ−
US4421996A (en) * 1981-10-09 1983-12-20 Advanced Micro Devices, Inc. Sense amplification scheme for random access memory
US4694205A (en) * 1985-06-03 1987-09-15 Advanced Micro Devices, Inc. Midpoint sense amplification scheme for a CMOS DRAM
ATE67891T1 (de) * 1986-07-24 1991-10-15 Siemens Ag Integrierbare bewerterschaltung.
US5519341A (en) * 1994-12-02 1996-05-21 Texas Instruments Incorporated Cross coupled quad comparator for current sensing independent of temperature
US6882209B1 (en) * 1997-09-09 2005-04-19 Intel Corporation Method and apparatus for interfacing mixed voltage signals

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE789500A (fr) * 1971-09-30 1973-03-29 Siemens Ag Memoire a semiconducteurs avec elements de memorisation a un seul transistor
US3959781A (en) * 1974-11-04 1976-05-25 Intel Corporation Semiconductor random access memory
US4004284A (en) * 1975-03-05 1977-01-18 Teletype Corporation Binary voltage-differential sensing circuits, and sense/refresh amplifier circuits for random-access memories
US3978459A (en) * 1975-04-21 1976-08-31 Intel Corporation High density mos memory array
US3993917A (en) * 1975-05-29 1976-11-23 International Business Machines Corporation Parameter independent FET sense amplifier
US4025907A (en) * 1975-07-10 1977-05-24 Burroughs Corporation Interlaced memory matrix array having single transistor cells
US4061999A (en) * 1975-12-29 1977-12-06 Mostek Corporation Dynamic random access memory system
US4028557A (en) * 1976-05-21 1977-06-07 Bell Telephone Laboratories, Incorporated Dynamic sense-refresh detector amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3710821A1 (de) * 1986-04-01 1987-10-15 Toshiba Kawasaki Kk Halbleiterspeichereinrichtung

Also Published As

Publication number Publication date
US4119870A (en) 1978-10-10
GB1587129A (en) 1981-04-01
JPS6044748B2 (ja) 1985-10-05
DE2623219A1 (de) 1977-12-01
JPS52144240A (en) 1977-12-01
FR2353116B1 (enrdf_load_stackoverflow) 1984-02-24
FR2353116A1 (fr) 1977-12-23
DE2623219C3 (enrdf_load_stackoverflow) 1979-06-13

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Legal Events

Date Code Title Description
OD Request for examination
C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee