DE19734512A1 - Halbleitereinrichtung mit entarteter Wannenstruktur und Verfahren zum Herstellen derselben - Google Patents
Halbleitereinrichtung mit entarteter Wannenstruktur und Verfahren zum Herstellen derselbenInfo
- Publication number
- DE19734512A1 DE19734512A1 DE19734512A DE19734512A DE19734512A1 DE 19734512 A1 DE19734512 A1 DE 19734512A1 DE 19734512 A DE19734512 A DE 19734512A DE 19734512 A DE19734512 A DE 19734512A DE 19734512 A1 DE19734512 A1 DE 19734512A1
- Authority
- DE
- Germany
- Prior art keywords
- degenerate
- well
- impurity layer
- semiconductor device
- concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
- H10B99/22—Subject matter not provided for in other groups of this subclass including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0191—Manufacturing their doped wells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
- Junction Field-Effect Transistors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22393996A JP3958388B2 (ja) | 1996-08-26 | 1996-08-26 | 半導体装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE19734512A1 true DE19734512A1 (de) | 1998-03-05 |
Family
ID=16806078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19734512A Ceased DE19734512A1 (de) | 1996-08-26 | 1997-08-08 | Halbleitereinrichtung mit entarteter Wannenstruktur und Verfahren zum Herstellen derselben |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6420763B1 (enExample) |
| JP (1) | JP3958388B2 (enExample) |
| KR (1) | KR19980018840A (enExample) |
| CN (2) | CN1306615C (enExample) |
| DE (1) | DE19734512A1 (enExample) |
| TW (1) | TW356597B (enExample) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6423615B1 (en) * | 1999-09-22 | 2002-07-23 | Intel Corporation | Silicon wafers for CMOS and other integrated circuits |
| US6440805B1 (en) * | 2000-02-29 | 2002-08-27 | Mototrola, Inc. | Method of forming a semiconductor device with isolation and well regions |
| US7145191B1 (en) * | 2000-03-31 | 2006-12-05 | National Semiconductor Corporation | P-channel field-effect transistor with reduced junction capacitance |
| JP2003078032A (ja) | 2001-09-05 | 2003-03-14 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
| JP2003158204A (ja) * | 2001-11-22 | 2003-05-30 | Mitsubishi Electric Corp | 半導体記憶装置およびその製造方法 |
| JP4232477B2 (ja) * | 2003-02-13 | 2009-03-04 | パナソニック株式会社 | 半導体集積回路の検証方法 |
| EP1683193A1 (en) * | 2003-10-22 | 2006-07-26 | Spinnaker Semiconductor, Inc. | Dynamic schottky barrier mosfet device and method of manufacture |
| JP2005142321A (ja) | 2003-11-06 | 2005-06-02 | Nec Electronics Corp | 半導体集積回路装置およびその製造方法 |
| EP1784869A1 (en) * | 2004-07-15 | 2007-05-16 | Spinnaker Semiconductor, Inc. | Metal source power transistor and method of manufacture |
| US20060049464A1 (en) * | 2004-09-03 | 2006-03-09 | Rao G R Mohan | Semiconductor devices with graded dopant regions |
| JP2006344735A (ja) * | 2005-06-08 | 2006-12-21 | Seiko Epson Corp | 半導体装置 |
| US7821075B2 (en) * | 2005-10-12 | 2010-10-26 | Avolare 2, Llc | CMOS device with zero soft error rate |
| DE102006023876A1 (de) * | 2006-05-19 | 2007-11-22 | Carl Zeiss Smt Ag | Optische Abbildungseinrichtung |
| US7872903B2 (en) | 2009-03-19 | 2011-01-18 | Altera Corporation | Volatile memory elements with soft error upset immunity |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4442591A (en) * | 1982-02-01 | 1984-04-17 | Texas Instruments Incorporated | High-voltage CMOS process |
| US4470191A (en) * | 1982-12-09 | 1984-09-11 | International Business Machines Corporation | Process for making complementary transistors by sequential implantations using oxidation barrier masking layer |
| US4633289A (en) | 1983-09-12 | 1986-12-30 | Hughes Aircraft Company | Latch-up immune, multiple retrograde well high density CMOS FET |
| US4710477A (en) | 1983-09-12 | 1987-12-01 | Hughes Aircraft Company | Method for forming latch-up immune, multiple retrograde well high density CMOS FET |
| DE3340560A1 (de) * | 1983-11-09 | 1985-05-15 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum gleichzeitigen herstellen von schnellen kurzkanal- und spannungsfesten mos-transistoren in vlsi-schaltungen |
| US4764482A (en) * | 1986-11-21 | 1988-08-16 | General Electric Company | Method of fabricating an integrated circuit containing bipolar and MOS transistors |
| JPS6410656A (en) * | 1987-07-03 | 1989-01-13 | Hitachi Ltd | Complementary type semiconductor device |
| CN1020028C (zh) * | 1987-08-18 | 1993-03-03 | 联邦德国Itt工业股份有限公司 | 制作cmos集成电路的注入井和岛的方法 |
| JPH0196962A (ja) * | 1987-10-08 | 1989-04-14 | Nissan Motor Co Ltd | 縦型mosトランジスタおよびその製造方法 |
| JP2660056B2 (ja) | 1989-09-12 | 1997-10-08 | 三菱電機株式会社 | 相補型mos半導体装置 |
| JP2523409B2 (ja) | 1990-05-02 | 1996-08-07 | 三菱電機株式会社 | 半導体記憶装置およびその製造方法 |
| KR950009893B1 (ko) * | 1990-06-28 | 1995-09-01 | 미쓰비시 뎅끼 가부시끼가이샤 | 반도체기억장치 |
| JP2978345B2 (ja) | 1992-11-26 | 1999-11-15 | 三菱電機株式会社 | 半導体装置の製造方法 |
| JPH0758212A (ja) * | 1993-08-19 | 1995-03-03 | Sony Corp | Cmos集積回路 |
| JP2682425B2 (ja) | 1993-12-24 | 1997-11-26 | 日本電気株式会社 | 半導体装置の製造方法 |
| US5393679A (en) | 1994-04-05 | 1995-02-28 | United Microelectronics Corporation | Use of double charge implant to improve retrograde process PMOS punch through voltage |
| JPH07312423A (ja) * | 1994-05-17 | 1995-11-28 | Hitachi Ltd | Mis型半導体装置 |
| US5654213A (en) * | 1995-10-03 | 1997-08-05 | Integrated Device Technology, Inc. | Method for fabricating a CMOS device |
| US5767556A (en) * | 1996-02-21 | 1998-06-16 | Nec Corporation | Field effect transistor |
-
1996
- 1996-08-26 JP JP22393996A patent/JP3958388B2/ja not_active Expired - Fee Related
-
1997
- 1997-07-31 TW TW086110966A patent/TW356597B/zh not_active IP Right Cessation
- 1997-08-08 DE DE19734512A patent/DE19734512A1/de not_active Ceased
- 1997-08-21 KR KR1019970039793A patent/KR19980018840A/ko not_active Withdrawn
- 1997-08-22 CN CNB2003101163756A patent/CN1306615C/zh not_active Expired - Fee Related
- 1997-08-22 CN CNB971186790A patent/CN1153295C/zh not_active Expired - Fee Related
- 1997-08-26 US US08/917,528 patent/US6420763B1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1153295C (zh) | 2004-06-09 |
| US6420763B1 (en) | 2002-07-16 |
| CN1306615C (zh) | 2007-03-21 |
| JPH1070250A (ja) | 1998-03-10 |
| US20020020888A1 (en) | 2002-02-21 |
| CN1185658A (zh) | 1998-06-24 |
| KR19980018840A (ko) | 1998-06-05 |
| JP3958388B2 (ja) | 2007-08-15 |
| TW356597B (en) | 1999-04-21 |
| CN1501504A (zh) | 2004-06-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| OP8 | Request for examination as to paragraph 44 patent law | ||
| 8131 | Rejection |