DE1966237C3 - Verfahren zur Erhöhung des Gradienten von elektrisch aktiven Störstellenkonzentrationen - Google Patents

Verfahren zur Erhöhung des Gradienten von elektrisch aktiven Störstellenkonzentrationen

Info

Publication number
DE1966237C3
DE1966237C3 DE1966237A DE1966237A DE1966237C3 DE 1966237 C3 DE1966237 C3 DE 1966237C3 DE 1966237 A DE1966237 A DE 1966237A DE 1966237 A DE1966237 A DE 1966237A DE 1966237 C3 DE1966237 C3 DE 1966237C3
Authority
DE
Germany
Prior art keywords
ion implantation
electrically active
gradient
increasing
impurities
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE1966237A
Other languages
German (de)
English (en)
Other versions
DE1966237B2 (de
DE1966237A1 (de
Inventor
Michael Charles Poughkeepsie Duffy
Paul August Wappingers Falls Schumann Jun.
Tsu-Hsing Poughkeepsie Yeh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE1966237A1 publication Critical patent/DE1966237A1/de
Publication of DE1966237B2 publication Critical patent/DE1966237B2/de
Application granted granted Critical
Publication of DE1966237C3 publication Critical patent/DE1966237C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137—Collector regions of BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/40—Treatments of semiconductor bodies to modify their internal properties, e.g. to produce internal imperfections
    • H10P95/402—Treatments of semiconductor bodies to modify their internal properties, e.g. to produce internal imperfections of silicon bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/30—Isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H10W15/01—Manufacture or treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/062—Gold diffusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/151—Simultaneous diffusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/904—Charge carrier lifetime control

Landscapes

  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Physical Vapour Deposition (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Thyristors (AREA)
DE1966237A 1968-08-06 1969-07-29 Verfahren zur Erhöhung des Gradienten von elektrisch aktiven Störstellenkonzentrationen Expired DE1966237C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US75065068A 1968-08-06 1968-08-06

Publications (3)

Publication Number Publication Date
DE1966237A1 DE1966237A1 (de) 1972-01-13
DE1966237B2 DE1966237B2 (de) 1975-07-17
DE1966237C3 true DE1966237C3 (de) 1979-07-12

Family

ID=25018702

Family Applications (3)

Application Number Title Priority Date Filing Date
DE1966237A Expired DE1966237C3 (de) 1968-08-06 1969-07-29 Verfahren zur Erhöhung des Gradienten von elektrisch aktiven Störstellenkonzentrationen
DE19691938365 Pending DE1938365B2 (de) 1968-08-06 1969-07-29 Verfahren zum herstellen eines transistors
DE1966236A Expired DE1966236C3 (de) 1968-08-06 1969-07-29 Verfahren zum Einbringen von Haftstellen in Transistorhalbleiterstrukturen

Family Applications After (2)

Application Number Title Priority Date Filing Date
DE19691938365 Pending DE1938365B2 (de) 1968-08-06 1969-07-29 Verfahren zum herstellen eines transistors
DE1966236A Expired DE1966236C3 (de) 1968-08-06 1969-07-29 Verfahren zum Einbringen von Haftstellen in Transistorhalbleiterstrukturen

Country Status (6)

Country Link
US (1) US3655457A (enExample)
JP (3) JPS501636B1 (enExample)
CA (1) CA922024A (enExample)
DE (3) DE1966237C3 (enExample)
FR (1) FR2015121A1 (enExample)
GB (3) GB1262705A (enExample)

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3919006A (en) * 1969-09-18 1975-11-11 Yasuo Tarui Method of manufacturing a lateral transistor
US3853644A (en) * 1969-09-18 1974-12-10 Kogyo Gijutsuin Transistor for super-high frequency and method of manufacturing it
BE759667A (fr) * 1969-12-01 1971-06-01 Philips Nv Procede permettant la fabrication d'un dispositif semiconducteur, et dispositif semiconducteur obtenu par la mise en oeuvre de ce procede
JPS4936514B1 (enExample) * 1970-05-13 1974-10-01
US3868722A (en) * 1970-06-20 1975-02-25 Philips Corp Semiconductor device having at least two transistors and method of manufacturing same
US3918996A (en) * 1970-11-02 1975-11-11 Texas Instruments Inc Formation of integrated circuits using proton enhanced diffusion
US3707765A (en) * 1970-11-19 1973-01-02 Motorola Inc Method of making isolated semiconductor devices
FR2123179B1 (enExample) * 1971-01-28 1974-02-15 Commissariat Energie Atomique
US3895965A (en) * 1971-05-24 1975-07-22 Bell Telephone Labor Inc Method of forming buried layers by ion implantation
US3897274A (en) * 1971-06-01 1975-07-29 Texas Instruments Inc Method of fabricating dielectrically isolated semiconductor structures
US3775191A (en) * 1971-06-28 1973-11-27 Bell Canada Northern Electric Modification of channel regions in insulated gate field effect transistors
US3737346A (en) * 1971-07-01 1973-06-05 Bell Telephone Labor Inc Semiconductor device fabrication using combination of energy beams for masking and impurity doping
US3841917A (en) * 1971-09-06 1974-10-15 Philips Nv Methods of manufacturing semiconductor devices
JPS4879585A (enExample) * 1972-01-24 1973-10-25
DE2235865A1 (de) * 1972-07-21 1974-01-31 Licentia Gmbh Halbleiteranordnung aus einer vielzahl von in einem gemeinsamen halbleiterkoerper untergebrachten halbleiterbauelementen
CH560463A5 (enExample) * 1972-09-26 1975-03-27 Siemens Ag
US3841918A (en) * 1972-12-01 1974-10-15 Bell Telephone Labor Inc Method of integrated circuit fabrication
US3981072A (en) * 1973-05-25 1976-09-21 Trw Inc. Bipolar transistor construction method
JPS5029186A (enExample) * 1973-07-17 1975-03-25
US3921199A (en) * 1973-07-31 1975-11-18 Texas Instruments Inc Junction breakdown voltage by means of ion implanted compensation guard ring
DE2341311C3 (de) * 1973-08-16 1981-07-09 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum Einstellen der Lebensdauer von Ladungsträgern in Halbleiterkörpern
FR2249491B1 (enExample) * 1973-10-30 1976-10-01 Thomson Csf
US3909304A (en) * 1974-05-03 1975-09-30 Western Electric Co Method of doping a semiconductor body
US3909807A (en) * 1974-09-03 1975-09-30 Bell Telephone Labor Inc Integrated circuit memory cell
JPS5138990A (en) * 1974-09-30 1976-03-31 Suwa Seikosha Kk Handotaisochino seizohoho
DE2453134C3 (de) * 1974-11-08 1983-02-10 Deutsche Itt Industries Gmbh, 7800 Freiburg Planardiffusionsverfahren
US4053924A (en) * 1975-02-07 1977-10-11 California Linear Circuits, Inc. Ion-implanted semiconductor abrupt junction
US3982967A (en) * 1975-03-26 1976-09-28 Ibm Corporation Method of proton-enhanced diffusion for simultaneously forming integrated circuit regions of varying depths
US4033787A (en) * 1975-10-06 1977-07-05 Honeywell Inc. Fabrication of semiconductor devices utilizing ion implantation
DE2554426C3 (de) * 1975-12-03 1979-06-21 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Erzeugung einer lokal hohen inversen Stromverstärkung bei einem Planartransistor sowie nach diesem Verfahren hergestellter invers betriebener Transistor
US4003759A (en) * 1976-03-01 1977-01-18 Honeywell Inc. Ion implantation of gold in mercury cadmium telluride
DE2627855A1 (de) * 1976-06-22 1977-12-29 Siemens Ag Halbleiterbauelement mit wenigstens zwei, einen pn-uebergang bildenden zonen unterschiedlichen leitungstyps sowie verfahren zu dessen herstellung
JPS5327110U (enExample) * 1976-08-13 1978-03-08
US4044371A (en) * 1976-09-29 1977-08-23 Honeywell Inc. Plurality of precise temperature resistors formed in monolithic integrated circuits
US4034395A (en) * 1976-09-29 1977-07-05 Honeywell Inc. Monolithic integrated circuit having a plurality of resistor regions electrically connected in series
US4111720A (en) * 1977-03-31 1978-09-05 International Business Machines Corporation Method for forming a non-epitaxial bipolar integrated circuit
US4157268A (en) * 1977-06-16 1979-06-05 International Business Machines Corporation Localized oxidation enhancement for an integrated injection logic circuit
FR2406301A1 (fr) * 1977-10-17 1979-05-11 Silicium Semiconducteur Ssc Procede de fabrication de dispositifs semi-conducteurs rapides
US4338138A (en) * 1980-03-03 1982-07-06 International Business Machines Corporation Process for fabricating a bipolar transistor
JPS56149473U (enExample) * 1981-03-26 1981-11-10
US4536945A (en) * 1983-11-02 1985-08-27 National Semiconductor Corporation Process for producing CMOS structures with Schottky bipolar transistors
US4727038A (en) * 1984-08-22 1988-02-23 Mitsubishi Denki Kabushiki Kaisha Method of fabricating semiconductor device
US4717588A (en) * 1985-12-23 1988-01-05 Motorola Inc. Metal redistribution by rapid thermal processing
US4910158A (en) * 1987-11-23 1990-03-20 Hughes Aircraft Company Zener diode emulation and method of forming the same
US4937756A (en) * 1988-01-15 1990-06-26 Industrial Technology Research Institute Gated isolated structure
DE59010851D1 (de) * 1989-04-27 1998-11-12 Max Planck Gesellschaft Halbleiterstruktur mit einer 2D-Ladungsträgerschicht und Herstellungsverfahren
EP0419898B1 (de) * 1989-09-28 2000-05-31 Siemens Aktiengesellschaft Verfahren zur Erhöhung der Spannungsfestigkeit eines mehrschichtigen Halbleiterbauelements
US5385865A (en) * 1990-04-26 1995-01-31 Max-Planck-Gesellschaft Zur Forderung Der Wissenschaften Method of generating active semiconductor structures by means of starting structures which have a 2D charge carrier layer parallel to the surface
US5108935A (en) * 1990-11-16 1992-04-28 Texas Instruments Incorporated Reduction of hot carrier effects in semiconductor devices by controlled scattering via the intentional introduction of impurities
US5179030A (en) * 1991-04-26 1993-01-12 Unitrode Corporation Method of fabricating a buried zener diode simultaneously with other semiconductor devices
GB2300753A (en) * 1995-05-06 1996-11-13 Atomic Energy Authority Uk Reducing the minority carrier lifetime of semiconductor devices
US20080087978A1 (en) * 2006-10-11 2008-04-17 Coolbaugh Douglas D Semiconductor structure and method of manufacture
US8178430B2 (en) 2009-04-08 2012-05-15 International Business Machines Corporation N-type carrier enhancement in semiconductors
WO2013099785A1 (ja) * 2011-12-26 2013-07-04 東レ株式会社 感光性樹脂組成物および半導体素子の製造方法
CN103426735B (zh) * 2012-05-24 2016-08-10 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法及mos晶体管的形成方法
US8999800B2 (en) * 2012-12-12 2015-04-07 Varian Semiconductor Equipment Associates, Inc. Method of reducing contact resistance

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2787564A (en) * 1954-10-28 1957-04-02 Bell Telephone Labor Inc Forming semiconductive devices by ionic bombardment
US3108914A (en) * 1959-06-30 1963-10-29 Fairchild Camera Instr Co Transistor manufacturing process
US3423647A (en) * 1964-07-30 1969-01-21 Nippon Electric Co Semiconductor device having regions with preselected different minority carrier lifetimes
US3388009A (en) * 1965-06-23 1968-06-11 Ion Physics Corp Method of forming a p-n junction by an ionic beam
US3434894A (en) * 1965-10-06 1969-03-25 Ion Physics Corp Fabricating solid state devices by ion implantation
US3341754A (en) * 1966-01-20 1967-09-12 Ion Physics Corp Semiconductor resistor containing interstitial and substitutional ions formed by an ion implantation method
US3448344A (en) * 1966-03-15 1969-06-03 Westinghouse Electric Corp Mosaic of semiconductor elements interconnected in an xy matrix
US3413531A (en) * 1966-09-06 1968-11-26 Ion Physics Corp High frequency field effect transistor
US3440113A (en) * 1966-09-19 1969-04-22 Westinghouse Electric Corp Process for diffusing gold into semiconductor material
US3431150A (en) * 1966-10-07 1969-03-04 Us Air Force Process for implanting grids in semiconductor devices
US3479233A (en) * 1967-01-16 1969-11-18 Ibm Method for simultaneously forming a buried layer and surface connection in semiconductor devices

Also Published As

Publication number Publication date
JPS501636B1 (enExample) 1975-01-20
GB1274725A (en) 1972-05-17
DE1966236A1 (de) 1971-12-16
DE1938365B2 (de) 1972-12-21
FR2015121A1 (enExample) 1970-04-24
DE1966236C3 (de) 1979-07-19
US3655457A (en) 1972-04-11
DE1938365A1 (de) 1970-02-12
JPS5125713B1 (enExample) 1976-08-02
GB1270170A (en) 1972-04-12
DE1966237B2 (de) 1975-07-17
JPS528673B1 (enExample) 1977-03-10
GB1262705A (en) 1972-02-02
DE1966236B2 (de) 1975-08-07
DE1966237A1 (de) 1972-01-13
CA922024A (en) 1973-02-27

Similar Documents

Publication Publication Date Title
DE1966237C3 (de) Verfahren zur Erhöhung des Gradienten von elektrisch aktiven Störstellenkonzentrationen
DE2652253C2 (de) Verfahren zur Steuerung der seitlichen Breite eines Dotierungsprofils in einem Halbleiterkörper eines Halbleiterbauelementes
DE2819698C2 (de) Verfahren zum Herstellen eines Festkörpermikrobauelementes und Vorrichtung zur Anwendung bei diesem Verfahren
DE2707693C3 (de) Verfahren zum Herstellen von dotierten Zonen einer bestimmten Leitungsart in einem Halbleitersubstrat mittels Ionenimplantation
DE2425382C2 (de) Verfahren zur Herstellung von Isolierschicht-Feldeffekttransistoren
EP0048288B1 (de) Verfahren zur Dotierung von Halbleiterbauelementen mittels Ionenimplantation
EP0018520A1 (de) Verfahren zur vollständigen Ausheilung von Gitterdefekten in durch Ionenimplantation von Phosphor erzeugten N-leitenden Zonen einer Siliciumhalbleitervorrichtung und zugehörige Siliciumhalbleitervorrichtung
DE2752439A1 (de) Verfahren zur herstellung von silicium-halbleiteranordnungen unter einsatz einer ionenimplantation und zugehoerige halbleiteranordnung
DE19534574C2 (de) Dotierverfahren zur Herstellung von Homoübergängen in Halbleitersubstraten
DE2422195A1 (de) Verfahren zur vermeidung von grenzschichtzustaenden bei der herstellung von halbleiteranordnungen
DE2752698A1 (de) Verfahren zur herstellung von halbleitervorrichtungen
DE1544275A1 (de) Herstellung von Halbleitervorrichtungen
DE1961634A1 (de) Verfahren zur Herstellung eines Misfet
DE2231891B2 (de) Verfahren zur herstellung einer wannenartigen, amorphen halbleiterschicht
DE2705468A1 (de) Verfahren zur herstellung von transistoren durch ionenimplantation
EP0028786B1 (de) Ionenimplantationsverfahren
DE69127028T2 (de) Verfahren der Herstellung lokalisierter vergrabener Isolationsstrukturen
DE2014797B2 (de) Verfahren zum Herstellen von Halbleiterschaltelementen jn einer integrierten Halbleiterschaltung
DE10207740B4 (de) Verfahren zur Herstellung eines p-Kanal-Feldeffekttransistors auf einem Halbleitersubstrat
EP0029887B1 (de) Verfahren zum Herstellen eines vertikalen PNP-Transistors und so hergestellter Transistor
DE2219696B2 (de) Verfahren zum Herstellen einer monolithisch integrierten Halbleiteranordnung
DE2650865A1 (de) Verfahren zur herstellung einer halbleitervorrichtung
EP0002797A1 (de) Verfahren zur Herstellung einer Halbleiteranordnung mit aktiven Bauelementen und Widerstandsgebieten
EP0270703A1 (de) Verfahren zum Herstellen einer monolithisch integrierten Schaltung mit mindestens einem bipolaren Planartransistor
EP0003733A1 (de) Verfahren zur Erzeugung abgestufter Fenster in Materialschichten aus Isolations- bzw. Elektrodenmaterial für die Herstellung einer integrierten Halbleiterschaltung und nach diesem Verfahren hergestellter MIS-Feldeffekttransistor mit kurzer Kanallänge

Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee