DE69127028T2 - Verfahren der Herstellung lokalisierter vergrabener Isolationsstrukturen - Google Patents

Verfahren der Herstellung lokalisierter vergrabener Isolationsstrukturen

Info

Publication number
DE69127028T2
DE69127028T2 DE69127028T DE69127028T DE69127028T2 DE 69127028 T2 DE69127028 T2 DE 69127028T2 DE 69127028 T DE69127028 T DE 69127028T DE 69127028 T DE69127028 T DE 69127028T DE 69127028 T2 DE69127028 T2 DE 69127028T2
Authority
DE
Germany
Prior art keywords
isolation structures
buried isolation
localized buried
making localized
making
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69127028T
Other languages
English (en)
Other versions
DE69127028D1 (de
Inventor
Sheldon Aronowitz
Courtney L Hart
Matthew Buynoski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of DE69127028D1 publication Critical patent/DE69127028D1/de
Application granted granted Critical
Publication of DE69127028T2 publication Critical patent/DE69127028T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/945—Special, e.g. metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/95—Multilayer mask including nonradiation sensitive layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/966—Selective oxidation of ion-amorphousized layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
DE69127028T 1990-05-31 1991-05-17 Verfahren der Herstellung lokalisierter vergrabener Isolationsstrukturen Expired - Fee Related DE69127028T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/531,509 US5043292A (en) 1990-05-31 1990-05-31 Self-aligned masking for ultra-high energy implants with application to localized buried implants and insolation structures

Publications (2)

Publication Number Publication Date
DE69127028D1 DE69127028D1 (de) 1997-09-04
DE69127028T2 true DE69127028T2 (de) 1998-03-05

Family

ID=24117919

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69127028T Expired - Fee Related DE69127028T2 (de) 1990-05-31 1991-05-17 Verfahren der Herstellung lokalisierter vergrabener Isolationsstrukturen

Country Status (5)

Country Link
US (1) US5043292A (de)
EP (1) EP0460440B1 (de)
JP (1) JP3459658B2 (de)
KR (1) KR100196087B1 (de)
DE (1) DE69127028T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0534530B1 (de) * 1991-09-23 2000-05-03 Koninklijke Philips Electronics N.V. Verfahren zum Herstellen einer Anordnung, bei dem ein Stoff in einen Körper implantiert wird
US5372952A (en) * 1992-04-03 1994-12-13 National Semiconductor Corporation Method for forming isolated semiconductor structures
EP0635884A1 (de) * 1993-07-13 1995-01-25 Siemens Aktiengesellschaft Verfahren zur Herstellung eines Grabens in einem Substrat und dessen Verwendung in der Smart-Power-Technologie
EP0703608B1 (de) * 1994-09-23 1998-02-25 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Verfahren zur Herstellung begrabener Oxidschichten in einem Silizium-Wafer
TW344897B (en) * 1994-11-30 1998-11-11 At&T Tcorporation A process for forming gate oxides possessing different thicknesses on a semiconductor substrate
US5880515A (en) 1996-09-30 1999-03-09 Lsi Logic Corporation Circuit isolation utilizing MeV implantation
JP3221376B2 (ja) * 1997-11-07 2001-10-22 日本電気株式会社 半導体装置の製造方法
JP2002217123A (ja) * 2001-01-18 2002-08-02 Sony Corp イオン注入方法
US6656815B2 (en) * 2001-04-04 2003-12-02 International Business Machines Corporation Process for implanting a deep subcollector with self-aligned photo registration marks
US20180175008A1 (en) * 2015-01-09 2018-06-21 Silicon Genesis Corporation Three dimensional integrated circuit

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3071288D1 (en) * 1980-09-19 1986-01-23 Ibm Deutschland Method of doping semiconductor devices by ion implantation
US4597163A (en) * 1984-12-21 1986-07-01 Zilog, Inc. Method of improving film adhesion between metallic silicide and polysilicon in thin film integrated circuit structures
JPS61191070A (ja) * 1985-02-20 1986-08-25 Toshiba Corp 半導体装置の製造方法
US4655875A (en) * 1985-03-04 1987-04-07 Hitachi, Ltd. Ion implantation process
JPS61288462A (ja) * 1985-06-17 1986-12-18 Hitachi Ltd 半導体装置の製造方法
JPS62122227A (ja) * 1985-11-22 1987-06-03 Hitachi Ltd 不純物ド−プ層の評価方法
US4735911A (en) * 1985-12-17 1988-04-05 Siemens Aktiengesellschaft Process for the simultaneous production of bipolar and complementary MOS transistors on a common silicon substrate
US4810667A (en) * 1987-04-28 1989-03-07 Texas Instruments Incorporated Dielectric isolation using isolated silicon by limited anodization of an N+ epitaxially defined sublayer in the presence of a diffusion under film layer
JPS6454764A (en) * 1987-06-11 1989-03-02 Gen Electric Manufacture of metal oxde semiconductor device
US4956306A (en) * 1988-11-03 1990-09-11 Harris Corporation Method for forming complementary patterns in a semiconductor material while using a single masking step
US4992390A (en) * 1989-07-06 1991-02-12 General Electric Company Trench gate structure with thick bottom oxide

Also Published As

Publication number Publication date
EP0460440A2 (de) 1991-12-11
JPH04253357A (ja) 1992-09-09
DE69127028D1 (de) 1997-09-04
EP0460440B1 (de) 1997-07-30
US5043292A (en) 1991-08-27
KR100196087B1 (ko) 1999-06-15
JP3459658B2 (ja) 2003-10-20
EP0460440A3 (en) 1994-05-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee