DE1963162C3 - Verfahren zur Herstellung mehrerer Halbleiterbauelemente aus einer einkristallinen Halbleiterscheibe - Google Patents

Verfahren zur Herstellung mehrerer Halbleiterbauelemente aus einer einkristallinen Halbleiterscheibe

Info

Publication number
DE1963162C3
DE1963162C3 DE1963162A DE1963162A DE1963162C3 DE 1963162 C3 DE1963162 C3 DE 1963162C3 DE 1963162 A DE1963162 A DE 1963162A DE 1963162 A DE1963162 A DE 1963162A DE 1963162 C3 DE1963162 C3 DE 1963162C3
Authority
DE
Germany
Prior art keywords
thickness
semiconductor
semiconductor wafer
grooves
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE1963162A
Other languages
German (de)
English (en)
Other versions
DE1963162A1 (de
DE1963162B2 (de
Inventor
Kenneth Elwood Richardson Tex. Bean (V.St.A.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE1963162A1 publication Critical patent/DE1963162A1/de
Publication of DE1963162B2 publication Critical patent/DE1963162B2/de
Application granted granted Critical
Publication of DE1963162C3 publication Critical patent/DE1963162C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/019—Manufacture or treatment of isolation regions comprising dielectric materials using epitaxial passivated integrated circuit [EPIC] processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/049—Equivalence and options
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/102—Mask alignment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/115—Orientation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Element Separation (AREA)
  • Weting (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
DE1963162A 1968-12-31 1969-12-17 Verfahren zur Herstellung mehrerer Halbleiterbauelemente aus einer einkristallinen Halbleiterscheibe Expired DE1963162C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00788167A US3844858A (en) 1968-12-31 1968-12-31 Process for controlling the thickness of a thin layer of semiconductor material and semiconductor substrate

Publications (3)

Publication Number Publication Date
DE1963162A1 DE1963162A1 (de) 1970-07-02
DE1963162B2 DE1963162B2 (de) 1974-08-08
DE1963162C3 true DE1963162C3 (de) 1975-04-10

Family

ID=25143652

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1963162A Expired DE1963162C3 (de) 1968-12-31 1969-12-17 Verfahren zur Herstellung mehrerer Halbleiterbauelemente aus einer einkristallinen Halbleiterscheibe

Country Status (7)

Country Link
US (1) US3844858A (https=)
JP (1) JPS4941956B1 (https=)
CA (1) CA949683A (https=)
DE (1) DE1963162C3 (https=)
FR (1) FR2030114B1 (https=)
GB (1) GB1288941A (https=)
NL (1) NL168997C (https=)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4063271A (en) * 1972-07-26 1977-12-13 Texas Instruments Incorporated FET and bipolar device and circuit process with maximum junction control
US3953264A (en) * 1974-08-29 1976-04-27 International Business Machines Corporation Integrated heater element array and fabrication method
US4338620A (en) * 1978-08-31 1982-07-06 Fujitsu Limited Semiconductor devices having improved alignment marks
US4670769A (en) * 1979-04-09 1987-06-02 Harris Corporation Fabrication of isolated regions for use in self-aligning device process utilizing selective oxidation
US4255207A (en) * 1979-04-09 1981-03-10 Harris Corporation Fabrication of isolated regions for use in self-aligning device process utilizing selective oxidation
US4309813A (en) * 1979-12-26 1982-01-12 Harris Corporation Mask alignment scheme for laterally and totally dielectrically isolated integrated circuits
JPS6088536U (ja) * 1983-11-24 1985-06-18 住友電気工業株式会社 化合物半導体ウエハ
US4652333A (en) * 1985-06-19 1987-03-24 Honeywell Inc. Etch process monitors for buried heterostructures
US5034347A (en) * 1987-10-05 1991-07-23 Menlo Industries Process for producing an integrated circuit device with substrate via hole and metallized backplane
US5051378A (en) * 1988-11-09 1991-09-24 Sony Corporation Method of thinning a semiconductor wafer
CH682528A5 (fr) * 1990-03-16 1993-09-30 Westonbridge Int Ltd Procédé de réalisation par attaque chimique d'au moins une cavité dans un substrat et substrat obtenu par ce procédé.
US5318663A (en) * 1992-12-23 1994-06-07 International Business Machines Corporation Method for thinning SOI films having improved thickness uniformity
US5589083A (en) * 1993-12-11 1996-12-31 Electronics And Telecommunications Research Institute Method of manufacturing microstructure by the anisotropic etching and bonding of substrates
US5534106A (en) * 1994-07-26 1996-07-09 Kabushiki Kaisha Toshiba Apparatus for processing semiconductor wafers
US5550399A (en) * 1994-11-03 1996-08-27 Kabushiki Kaisha Toshiba Integrated circuit with windowed fuse element and contact pad
US5851928A (en) * 1995-11-27 1998-12-22 Motorola, Inc. Method of etching a semiconductor substrate
KR100277968B1 (ko) * 1998-09-23 2001-03-02 구자홍 질화갈륨 기판 제조방법
US6333553B1 (en) 1999-05-21 2001-12-25 International Business Machines Corporation Wafer thickness compensation for interchip planarity
US8132775B2 (en) * 2008-04-29 2012-03-13 International Business Machines Corporation Solder mold plates used in packaging process and method of manufacturing solder mold plates

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL294124A (https=) * 1962-06-18
US3290753A (en) * 1963-08-19 1966-12-13 Bell Telephone Labor Inc Method of making semiconductor integrated circuit elements
FR1481283A (fr) * 1965-04-14 1967-05-19 Westinghouse Electric Corp Procédé de fabrication de circuits semiconducteurs intégrés
US3411200A (en) * 1965-04-14 1968-11-19 Westinghouse Electric Corp Fabrication of semiconductor integrated circuits
US3457123A (en) * 1965-06-28 1969-07-22 Motorola Inc Methods for making semiconductor structures having glass insulated islands
US3357871A (en) * 1966-01-12 1967-12-12 Ibm Method for fabricating integrated circuits
NL144778B (nl) * 1966-12-20 1975-01-15 Western Electric Co Werkwijze voor het vervaardigen van een halfgeleiderinrichting door anisotroop etsen alsmede aldus vervaardigde inrichting.

Also Published As

Publication number Publication date
FR2030114B1 (https=) 1975-01-10
FR2030114A1 (https=) 1970-10-30
US3844858A (en) 1974-10-29
GB1288941A (https=) 1972-09-13
NL168997B (nl) 1981-12-16
NL6919088A (https=) 1970-07-02
DE1963162A1 (de) 1970-07-02
NL168997C (nl) 1982-05-17
JPS4941956B1 (https=) 1974-11-12
CA949683A (en) 1974-06-18
DE1963162B2 (de) 1974-08-08

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
E77 Valid patent as to the heymanns-index 1977