JPS6088536U - 化合物半導体ウエハ - Google Patents

化合物半導体ウエハ

Info

Publication number
JPS6088536U
JPS6088536U JP1983181255U JP18125583U JPS6088536U JP S6088536 U JPS6088536 U JP S6088536U JP 1983181255 U JP1983181255 U JP 1983181255U JP 18125583 U JP18125583 U JP 18125583U JP S6088536 U JPS6088536 U JP S6088536U
Authority
JP
Japan
Prior art keywords
compound semiconductor
semiconductor wafer
wafer
corner
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1983181255U
Other languages
English (en)
Other versions
JPS6317244Y2 (ja
Inventor
鹿谷　修
山口　順
Original Assignee
住友電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 住友電気工業株式会社 filed Critical 住友電気工業株式会社
Priority to JP1983181255U priority Critical patent/JPS6088536U/ja
Priority to US06/672,882 priority patent/US4632884A/en
Publication of JPS6088536U publication Critical patent/JPS6088536U/ja
Application granted granted Critical
Publication of JPS6317244Y2 publication Critical patent/JPS6317244Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/102—Mask alignment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12681—Ga-, In-, Tl- or Group VA metal-base component

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は長方形ウェハに本考案を実施した例を示す平面
図。第２図は長方形ウエノ１の実施例であるが隅部に丸
みを形成した例を示す平面図。第３図は正方形ウェハに
本考案を実施した例を示す平面図。Ｃは切欠きの長辺、
Ｄは切欠きの短辺を示す。第４図は正方形ウェハの他の
実施例で、楕円の１／４部分に当る切欠きを一隅に形成
した例を示す平面図。第５図は角形ウェハの一隅に標識
を付した実施例を示す平面図。第６図はＩＩＩ−Ｖ族化
合物半導体単結晶ウェハの表面、裏面に於て、メサ方向
、逆メサ方向が互に直交するように発生している状態を
示す斜視図。 １・・・角形ウェハ、２・・・−隅に設けた切欠き、３
・・・−過の片面に付した標識。

Claims (1)

    【実用新案登録請求の範囲】
  1. ■−■族化合物半導体単結晶の角形ウエノ１に於て、ウ
    ェハの一隅を切欠き、或は−隅の面上に標識を付した事
    を特徴とする化合物半導体ウエノ１゜
JP1983181255U 1983-11-24 1983-11-24 化合物半導体ウエハ Granted JPS6088536U (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1983181255U JPS6088536U (ja) 1983-11-24 1983-11-24 化合物半導体ウエハ
US06/672,882 US4632884A (en) 1983-11-24 1984-11-19 Marked single-crystal III-V group compound semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983181255U JPS6088536U (ja) 1983-11-24 1983-11-24 化合物半導体ウエハ

Publications (2)

Publication Number Publication Date
JPS6088536U true JPS6088536U (ja) 1985-06-18
JPS6317244Y2 JPS6317244Y2 (ja) 1988-05-16

Family

ID=16097499

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983181255U Granted JPS6088536U (ja) 1983-11-24 1983-11-24 化合物半導体ウエハ

Country Status (2)

Country Link
US (1) US4632884A (ja)
JP (1) JPS6088536U (ja)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60125726U (ja) * 1984-02-02 1985-08-24 住友電気工業株式会社 化合物半導体ミラ−ウエハ
JPH07101679B2 (ja) * 1988-11-01 1995-11-01 三菱電機株式会社 電子デバイス用ウエハ，ウエハ用棒状基材および電子デバイス
US5593815A (en) * 1989-07-31 1997-01-14 Goldstar Co., Ltd. Cleaving process in manufacturing a semiconductor laser
US5792566A (en) * 1996-07-02 1998-08-11 American Xtal Technology Single crystal wafers
JP3580311B1 (ja) * 2003-03-28 2004-10-20 住友電気工業株式会社 表裏識別した矩形窒化物半導体基板
US8389099B1 (en) 2007-06-01 2013-03-05 Rubicon Technology, Inc. Asymmetrical wafer configurations and method for creating the same
EP2168158B1 (en) 2007-06-13 2013-06-05 Conergy AG Method for marking wafers
CN101354228B (zh) * 2008-09-24 2010-06-09 友达光电股份有限公司 基板辨识治具与基板的辨识方法
JP2010192697A (ja) * 2009-02-18 2010-09-02 Sumitomo Electric Ind Ltd 炭化珪素基板および炭化珪素基板の製造方法
US8128830B2 (en) * 2009-09-17 2012-03-06 Hitachi Global Storage Technologies Netherlands, B.V. Labeling an imprint lithography template
JP2012049285A (ja) 2010-08-26 2012-03-08 Shin Etsu Chem Co Ltd 太陽電池用基板及び太陽電池
CN103489752A (zh) * 2013-09-26 2014-01-01 中国科学院半导体研究所 截面为多边形的晶棒及衬底片表面取向的标识方法
JP6645502B2 (ja) * 2015-07-24 2020-02-14 Ａｇｃ株式会社 ガラス基板、積層基板、積層基板の製造方法、積層体、梱包体、およびガラス基板の製造方法
CN108074834A (zh) * 2018-01-08 2018-05-25 中国电子科技集团公司第四十六研究所 一种用于具有极性的异形晶片的极性面判定方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5123071A (en) * 1974-08-20 1976-02-24 Matsushita Electronics Corp Handotaisochino seizoho
JPS5562736A (en) * 1978-11-01 1980-05-12 Toshiba Corp Mask material for preparation of semiconductor device
JPS56131925A (en) * 1980-03-19 1981-10-15 Seiko Epson Corp Shape of semiconductor wafer
JPS57173931A (en) * 1981-04-17 1982-10-26 Toshiba Corp Substrate for semiconductor device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3844858A (en) * 1968-12-31 1974-10-29 Texas Instruments Inc Process for controlling the thickness of a thin layer of semiconductor material and semiconductor substrate
US3710101A (en) * 1970-10-06 1973-01-09 Westinghouse Electric Corp Apparatus and method for alignment of members to electron beams
US3783044A (en) * 1971-04-09 1974-01-01 Motorola Inc Photoresist keys and depth indicator
US3742315A (en) * 1971-10-18 1973-06-26 Matsushita Electronics Corp Schottky barrier type semiconductor device with improved backward breakdown voltage characteristic
CA1185013A (en) * 1981-01-14 1985-04-02 Kenji Ohta Magneto-optic memory medium
US4468857A (en) * 1983-06-27 1984-09-04 Teletype Corporation Method of manufacturing an integrated circuit device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5123071A (en) * 1974-08-20 1976-02-24 Matsushita Electronics Corp Handotaisochino seizoho
JPS5562736A (en) * 1978-11-01 1980-05-12 Toshiba Corp Mask material for preparation of semiconductor device
JPS56131925A (en) * 1980-03-19 1981-10-15 Seiko Epson Corp Shape of semiconductor wafer
JPS57173931A (en) * 1981-04-17 1982-10-26 Toshiba Corp Substrate for semiconductor device

Also Published As

Publication number Publication date
JPS6317244Y2 (ja) 1988-05-16
US4632884A (en) 1986-12-30

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