DE19519533B4 - Multi-Layer-Wafer mit einer Getterschicht und Verfahren zu dessen Herstellung - Google Patents

Multi-Layer-Wafer mit einer Getterschicht und Verfahren zu dessen Herstellung Download PDF

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Publication number
DE19519533B4
DE19519533B4 DE19519533A DE19519533A DE19519533B4 DE 19519533 B4 DE19519533 B4 DE 19519533B4 DE 19519533 A DE19519533 A DE 19519533A DE 19519533 A DE19519533 A DE 19519533A DE 19519533 B4 DE19519533 B4 DE 19519533B4
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DE
Germany
Prior art keywords
layer
polysilicon
wafer
recesses
working
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE19519533A
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German (de)
English (en)
Other versions
DE19519533A1 (de
Inventor
William Graham Faster
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agere Systems LLC
Original Assignee
Agere Systems LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems LLC filed Critical Agere Systems LLC
Publication of DE19519533A1 publication Critical patent/DE19519533A1/de
Application granted granted Critical
Publication of DE19519533B4 publication Critical patent/DE19519533B4/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/912—Charge transfer device using both electron and hole signal carriers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
DE19519533A 1994-06-03 1995-05-27 Multi-Layer-Wafer mit einer Getterschicht und Verfahren zu dessen Herstellung Expired - Lifetime DE19519533B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US253657 1988-10-05
US25365794A 1994-06-03 1994-06-03

Publications (2)

Publication Number Publication Date
DE19519533A1 DE19519533A1 (de) 1995-12-07
DE19519533B4 true DE19519533B4 (de) 2009-05-28

Family

ID=22961174

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19519533A Expired - Lifetime DE19519533B4 (de) 1994-06-03 1995-05-27 Multi-Layer-Wafer mit einer Getterschicht und Verfahren zu dessen Herstellung

Country Status (6)

Country Link
US (1) US5892292A (enrdf_load_stackoverflow)
JP (2) JPH07335654A (enrdf_load_stackoverflow)
KR (1) KR960002685A (enrdf_load_stackoverflow)
CN (1) CN1119341A (enrdf_load_stackoverflow)
DE (1) DE19519533B4 (enrdf_load_stackoverflow)
TW (1) TW274628B (enrdf_load_stackoverflow)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567644A (en) 1995-09-14 1996-10-22 Micron Technology, Inc. Method of making a resistor
US6008082A (en) 1995-09-14 1999-12-28 Micron Technology, Inc. Method of making a resistor, method of making a diode, and SRAM circuitry and other integrated circuitry
US6093624A (en) * 1997-12-23 2000-07-25 Philips Electronics North America Corporation Method of providing a gettering scheme in the manufacture of silicon-on-insulator (SOI) integrated circuits
JP2000323484A (ja) * 1999-05-07 2000-11-24 Mitsubishi Electric Corp 半導体装置及び半導体記憶装置
US6508363B1 (en) 2000-03-31 2003-01-21 Lucent Technologies Slurry container
US20020140030A1 (en) * 2001-03-30 2002-10-03 Mandelman Jack A. SOI devices with integrated gettering structure
US6958264B1 (en) * 2001-04-03 2005-10-25 Advanced Micro Devices, Inc. Scribe lane for gettering of contaminants on SOI wafers and gettering method
US7045885B1 (en) 2004-12-09 2006-05-16 Hewlett-Packard Development Company, L.P. Placement of absorbing material in a semiconductor device

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4178191A (en) * 1978-08-10 1979-12-11 Rca Corp. Process of making a planar MOS silicon-on-insulating substrate device
JPS57162444A (en) * 1981-03-31 1982-10-06 Fujitsu Ltd Manufacture of semiconductor device
US4498227A (en) * 1983-07-05 1985-02-12 Fairchild Camera & Instrument Corporation Wafer fabrication by implanting through protective layer
US4583282A (en) * 1984-09-14 1986-04-22 Motorola, Inc. Process for self-aligned buried layer, field guard, and isolation
DE2746700C2 (enrdf_load_stackoverflow) * 1976-10-28 1988-12-22 International Business Machines Corp., Armonk, N.Y., Us
US4805008A (en) * 1986-06-23 1989-02-14 Nissan Motor Co., Ltd. Semiconductor device having MOSFET and deep polycrystalline silicon region
US5001075A (en) * 1989-04-03 1991-03-19 Motorola Fabrication of dielectrically isolated semiconductor device
US5164218A (en) * 1989-05-12 1992-11-17 Nippon Soken, Inc. Semiconductor device and a method for producing the same
EP0537889A2 (en) * 1991-10-14 1993-04-21 Fujitsu Limited Quantum interference effect semiconductor device and method of producing the same
DE3784124T2 (de) * 1986-10-03 1993-09-16 Tektronix Inc Selbstjustierter, intern beweglicher ionengetter fuer mehrschichtmetallisierung auf integrierten schaltkreisen.

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3875657A (en) * 1973-09-04 1975-04-08 Trw Inc Dielectrically isolated semiconductor devices
JPS542657A (en) * 1977-06-08 1979-01-10 Mitsubishi Electric Corp Manufacture for semiconductor device
JPS574163A (en) * 1980-06-09 1982-01-09 Nec Corp Manufacture of sos/mos transistor
US4574209A (en) * 1982-06-21 1986-03-04 Eaton Corporation Split gate EFET and circuitry
US4661202A (en) * 1984-02-14 1987-04-28 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US4631804A (en) * 1984-12-10 1986-12-30 At&T Bell Laboratories Technique for reducing substrate warpage springback using a polysilicon subsurface strained layer
JPS61256740A (ja) * 1985-05-10 1986-11-14 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS6224854A (ja) * 1985-07-24 1987-02-02 Nippon Kokan Kk <Nkk> 真空ア−ク再溶解装置
JPS6276646A (ja) * 1985-09-30 1987-04-08 Toshiba Corp 半導体装置の製造方法
DD258681A1 (de) * 1986-04-02 1988-07-27 Erfurt Mikroelektronik Verfahren zum herstellen getterfaehiger und formstabiler halbleiterscheiben
JPS63237574A (ja) * 1987-03-26 1988-10-04 Nec Corp Ｍｉｓ型半導体装置の製造方法
JPS63310123A (ja) * 1987-06-12 1988-12-19 Kyushu Denshi Kinzoku Kk シリコン半導体基板
US4820653A (en) * 1988-02-12 1989-04-11 American Telephone And Telegraph Company Technique for fabricating complementary dielectrically isolated wafer
US5059550A (en) * 1988-10-25 1991-10-22 Sharp Kabushiki Kaisha Method of forming an element isolating portion in a semiconductor device
JPH02148855A (ja) * 1988-11-30 1990-06-07 Fujitsu Ltd 半導体装置及びその製造方法
US4883215A (en) * 1988-12-19 1989-11-28 Duke University Method for bubble-free bonding of silicon wafers
JPH02237120A (ja) * 1989-03-10 1990-09-19 Fujitsu Ltd 半導体装置とその製造方法
JP2597022B2 (ja) * 1990-02-23 1997-04-02 シャープ株式会社 素子分離領域の形成方法
US5318919A (en) * 1990-07-31 1994-06-07 Sanyo Electric Co., Ltd. Manufacturing method of thin film transistor
JPH04363025A (ja) * 1991-01-28 1992-12-15 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5218213A (en) * 1991-02-22 1993-06-08 Harris Corporation SOI wafer with sige
JPH05136153A (ja) * 1991-11-14 1993-06-01 Toshiba Corp 半導体装置及びその製造方法
JPH05291265A (ja) * 1992-04-13 1993-11-05 Sony Corp ウエハ裏面ゲッター層の形成方法
JP3297937B2 (ja) * 1992-10-16 2002-07-02 ソニー株式会社 半導体装置及びその製造方法
JPH06252153A (ja) * 1993-03-01 1994-09-09 Toshiba Corp 半導体装置の製造方法
US5272104A (en) * 1993-03-11 1993-12-21 Harris Corporation Bonded wafer process incorporating diamond insulator
JPH0722517A (ja) * 1993-06-22 1995-01-24 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5294562A (en) * 1993-09-27 1994-03-15 United Microelectronics Corporation Trench isolation with global planarization using flood exposure
JPH07106413A (ja) * 1993-10-08 1995-04-21 Nippondenso Co Ltd 溝分離半導体装置及びその製造方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2746700C2 (enrdf_load_stackoverflow) * 1976-10-28 1988-12-22 International Business Machines Corp., Armonk, N.Y., Us
US4178191A (en) * 1978-08-10 1979-12-11 Rca Corp. Process of making a planar MOS silicon-on-insulating substrate device
JPS57162444A (en) * 1981-03-31 1982-10-06 Fujitsu Ltd Manufacture of semiconductor device
US4498227A (en) * 1983-07-05 1985-02-12 Fairchild Camera & Instrument Corporation Wafer fabrication by implanting through protective layer
US4583282A (en) * 1984-09-14 1986-04-22 Motorola, Inc. Process for self-aligned buried layer, field guard, and isolation
US4805008A (en) * 1986-06-23 1989-02-14 Nissan Motor Co., Ltd. Semiconductor device having MOSFET and deep polycrystalline silicon region
DE3784124T2 (de) * 1986-10-03 1993-09-16 Tektronix Inc Selbstjustierter, intern beweglicher ionengetter fuer mehrschichtmetallisierung auf integrierten schaltkreisen.
US5001075A (en) * 1989-04-03 1991-03-19 Motorola Fabrication of dielectrically isolated semiconductor device
US5164218A (en) * 1989-05-12 1992-11-17 Nippon Soken, Inc. Semiconductor device and a method for producing the same
EP0537889A2 (en) * 1991-10-14 1993-04-21 Fujitsu Limited Quantum interference effect semiconductor device and method of producing the same

Also Published As

Publication number Publication date
TW274628B (enrdf_load_stackoverflow) 1996-04-21
JPH07335654A (ja) 1995-12-22
CN1119341A (zh) 1996-03-27
JP2006324688A (ja) 2006-11-30
US5892292A (en) 1999-04-06
DE19519533A1 (de) 1995-12-07
KR960002685A (ko) 1996-01-26

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8127 New person/name/address of the applicant

Owner name: AGERE SYSTEMS, INC., ALLENTOWN, PA., US

8364 No opposition during term of opposition
R082 Change of representative

Representative=s name: DILG HAEUSLER SCHINDELMANN PATENTANWALTSGESELL, DE

R071 Expiry of right