DE1621532B2 - Verfahren zum herstellen formgebender einaetzungen an einer monokristallinen halbleiterscheibe - Google Patents

Verfahren zum herstellen formgebender einaetzungen an einer monokristallinen halbleiterscheibe

Info

Publication number
DE1621532B2
DE1621532B2 DE19671621532 DE1621532A DE1621532B2 DE 1621532 B2 DE1621532 B2 DE 1621532B2 DE 19671621532 DE19671621532 DE 19671621532 DE 1621532 A DE1621532 A DE 1621532A DE 1621532 B2 DE1621532 B2 DE 1621532B2
Authority
DE
Germany
Prior art keywords
etching
etched
mask
solution
speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19671621532
Other languages
German (de)
English (en)
Other versions
DE1621532A1 (de
Inventor
Roger Clyde Bethlehem Waggener Herbert Atkin Allentown Pa Kragness (V St A)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of DE1621532A1 publication Critical patent/DE1621532A1/de
Publication of DE1621532B2 publication Critical patent/DE1621532B2/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/021—Manufacture or treatment of air gaps
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/10—Etching compositions
    • C23F1/14—Aqueous compositions
    • C23F1/32—Alkaline compositions
    • C23F1/40—Alkaline compositions for etching other metallic material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H10P50/644—Anisotropic liquid etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/20—Air gaps

Landscapes

  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Weting (AREA)
DE19671621532 1966-12-20 1967-12-19 Verfahren zum herstellen formgebender einaetzungen an einer monokristallinen halbleiterscheibe Withdrawn DE1621532B2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US60329266A 1966-12-20 1966-12-20

Publications (2)

Publication Number Publication Date
DE1621532A1 DE1621532A1 (de) 1970-10-22
DE1621532B2 true DE1621532B2 (de) 1971-10-07

Family

ID=24414811

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19671621532 Withdrawn DE1621532B2 (de) 1966-12-20 1967-12-19 Verfahren zum herstellen formgebender einaetzungen an einer monokristallinen halbleiterscheibe

Country Status (7)

Country Link
BE (1) BE708163A (https=)
DE (1) DE1621532B2 (https=)
FR (1) FR1548079A (https=)
GB (1) GB1212379A (https=)
MY (1) MY7300447A (https=)
NL (1) NL144778B (https=)
SE (1) SE342526B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0226451A3 (en) * 1985-12-13 1989-08-23 Xerox Corporation Sensor arrays

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1288278A (https=) * 1968-12-31 1972-09-06
US3844858A (en) * 1968-12-31 1974-10-29 Texas Instruments Inc Process for controlling the thickness of a thin layer of semiconductor material and semiconductor substrate
US3579057A (en) * 1969-08-18 1971-05-18 Rca Corp Method of making a semiconductor article and the article produced thereby
CA957782A (en) * 1970-01-26 1974-11-12 Theodore Kamprath Capacitor structure for integrated circuits
DE2106540A1 (de) * 1970-02-13 1971-08-19 Texas Instruments Inc Halbleiterschaltung und Verfahren zu ihrer Herstellung
EP0296348B1 (de) * 1987-05-27 1993-03-31 Siemens Aktiengesellschaft Ätzverfahren zum Erzeugen von Lochöffnungen oder Gräben in n-dotiertem Silizium
GB9204078D0 (en) * 1992-02-26 1992-04-08 Philips Electronics Uk Ltd Infrared detector manufacture
US5508231A (en) * 1994-03-07 1996-04-16 National Semiconductor Corporation Apparatus and method for achieving mechanical and thermal isolation of portions of integrated monolithic circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0226451A3 (en) * 1985-12-13 1989-08-23 Xerox Corporation Sensor arrays

Also Published As

Publication number Publication date
NL6716390A (https=) 1968-06-21
BE708163A (https=) 1968-05-02
SE342526B (https=) 1972-02-07
MY7300447A (en) 1973-12-31
GB1212379A (en) 1970-11-18
NL144778B (nl) 1975-01-15
FR1548079A (https=) 1968-11-29
DE1621532A1 (de) 1970-10-22

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Legal Events

Date Code Title Description
E77 Valid patent as to the heymanns-index 1977
8339 Ceased/non-payment of the annual fee