DE1621532B2 - PROCESS FOR PRODUCING SHAPING INSERTS ON A MONOCRYSTALLINE SEMICONDUCTOR DISC - Google Patents

Description

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The invention relates to a method for the method including the removal with air or

Manufacture of shaping etchings on a mono-ultrasonic cutting process available. On the

Crystalline semiconductor wafer with at least one area of chemical etching have the method

first, second and third crystallographic planes of the isotropic type found general application,

lower order, with the main surfaces of the half-5 at which the etching speeds in all directions

Conductor disk in the first crystallographic plane is practically uniform from the starting surface

lying, by etching one of those with an etching mask. As will be explained in more detail below,

provided main surfaces. this technique does not allow the control or

Semiconductor components, regardless of whether they have a degree of accuracy, are required for ongoing production

of the type of the single element or the integrated io of semiconductor components is advantageous.

Circuit are, generally made of single crystal material From the magazine "The Sylvania Technologist",

made in disc shape. Each disc provides a April 1958, pp. 50 to 58, it is known per se that

large number of components. Both in the case of individual alkaline etching solutions in different crystalloid

element as well as the component of the integrated graphic directions to different degrees.

The circuit is the precise design during manufacture

removal of parts of the material to separate properties

advise or for the production of insulating slots or production of semiconductor components to impair

Grooves are an important part of the manufacturing process. flow of the etching depth used.

In particular, it is important in this manufacture, but the purpose of the present invention is not

Minimum of material under precisely controlled 20 creating more even floors in the case of etched holes, but rather

To remove conditions in order to build components higher it is based on the task of being precise and material-

Quality, economical and compact etching for shaping purposes in one

to deliver. Manufacture semiconductor wafer.

For example, in the manufacture of semi-conductor components in certain integrated circuits it is assumed that the material used is contained the necessary electrical isolation between is crystalline, and the explanation of the invention will be Divide the circuit within the semiconductor by placing it on a silicon, which has a face-centered, Removal of the semiconductor material within the precubic crystal from the shape of the diamond lattice certain limits to the production of partial or has. It goes without saying that germanium and the semi-continuous Slots in the semiconductor material fully conductors of the AmBv group of compounds from im pulled. In the case of continuous slots through which are generally the same crystal structure and that Disc are the components of the integrated form- therefore the principle of the invention is not based on silicon either restricted by a predetermined arrangement.

strong metal feeds, including the supports, based on a method that was

the connection between connections or by a given type becomes a solution through the invention

Attachment of insulating auxiliary layers. Suggested for one of the tasks on which it is based,

other methods, where the grooves are only partial, that the semiconductor wafer is provided with an etching mask

they will be covered with a suitable dielectric, like will, whose edges are parallel to those of the first (100)

Silicon dioxide, filled in, the disk turned upside down and the second (111) crystallographic plane formed.

the material from the opposite surface to 4 ° deten cut lines run, and with one in itself

removed to a depth that the bottoms of the well-known way filled the semiconductor material in different

Cut the grooves. Examples of the aforementioned borrowed crystal directions vary in strength _a.n-

Types of manufacturing processes are in the US A.

tenten 3 287 612 and 3 290 753 and in French speed in the first level (100), a relative

U.S. Patent 1,417,760. 45 low etching speed in the second level (111)

In manufacturing processes of the type referred to below and one drawn between these two etching speeds, it is important and advantageous to reduce the average etching speed in the third of the isolation slots by a level (110) which is etched. In this way, a more compact structure and a smaller overall volume can achieve narrow, well-defined grooves and slots in the structural unit and thus increase economy and efficiency to the desired depth. In particular, simple treatment conditions are created, it is important to reduce the width of the slot on the device Angled mask edges on a limit on the device side allows. In this 55 larger area of a disk made of semiconductor material Description, the device side of the plate refers to arranged parallel to the (100) plane. In this case, the (100) -plane is the primary etched surface, ie it consists of the layer deposited on the surface - usually consisting of an epitak - on which has the highest etching speed for the particular circuit elements are produced, and on the the etchant. The orthogonally arranged boundaries of the metal patterns of the interconnecting circuit ⁶ ° mask are made parallel to the cutting lines of the (Hl) - is made. Typically, this switching plane with the primary etching plane, the (100) plane, elements are arranged by oxide-masked diffusion processes. Then, as the formation progresses, the effective device thickness etching down from the primary etching area is 1.0 x 10 ^-3 or 1.3 x 10 ^-3 cm. There is a number of practically no lateral etching available against the exposed of processes and has also been applied to the ⁶ 5 (lll) -plane occurrence in that the etchant has been so compounded to this type of material removal in half that it is practically one Carry out etching guide disks. In addition to the chemical speed zero on it. In the meantime, in the case of etching processes, there are certain mechanical cutting edges of the mask boundaries, which are effective

3 4

Form the same outer edges, planes exposed which are etched with The etch does not remove the layer 46 of silicon

one of the etching speed of the (HO) plane dioxide on the device side of the disk 44. The proximity

dependent speed can be etched. the switching element is through the adjacent zo-

This rate is determined, although slower than the 45 with p-type conductivity. Fig. 4,

of the (100) -plane, in a special version always 5, 5, 6 and 7 represent the etching of a groove of such geo-

still significant. This means an undercutting metry that they have the effects of the edges for

the mask in these places. Accordingly, the purpose of this investigation is to eliminate the isotropic

it in accordance with the invention also compares and anisotropic etching.

To change the size of the etching mask by changing a factor of importance in the present etching

Larger corner surfaces of a predetermined size and moved io is the speed of the edge 51 of the

Shape provides for the undercutting effect of the etching front 48 in its line of intersection with the surface 50

to compensate for the method described above. the device side of the pane. When these speeds

A more complete understanding of the invention is high, it is difficult to etch on a

gives out from the following, detailed desired position to be terminated by means of time control.

Description in conjunction with the drawings. 15 This problem is caused by the following

F i g. FIG. 1 is a plan view of an air-insulated drawing illustrated from the diagram of FIG

monolithic (AIM) semiconductor component in integrated Fig. 13:

grated circuit with rigid leads and explained _w ^ _{the slice thickness;}

tert em component that using the etching _χ ^ _{the ord} inate of the edge 51, which has been produced from the cutting method according to the invention and for the purpose of generating * ° _{edge of the Ätrfront with the} device side surface of an insulation; 50 is formed,

F 1 g. 2 is a perspective view of a critical _{f IGT the radius of the mask edge 42 with the etching.}

stallographic model of a silicon plant; front

F i g. 3 is a partial perspective view ₍ j _{st d} j ' _e etching time of special ^ crystallographic planes based on a * 5 _{R. The} etching speed. Partial view of the model according to F1 g. 2 and the °.' Etching mask orientation according to the present invention Equations are explained; the following are provided:

F i g. 4 and 5 are specific, partially cut r = Rt (D

Images of _d in a crystal isotropically etched Schiit- 3 °

^Ze c * α π <u c λ λ < a dr = Rdt + tdR . (2)

F 1 g. 6 and 7 correspond to F 1 g. 4 and 5, however

with anisotropically etched grooves according to the invention; ₂ _ ₂ 1 _W 2 ή \

F i g. 8 and 9 are graphs showing

Compare the degree of control of the etching fronts by isotropic and 35 By differentiation and division by the off-anisotropic etching; pressure x ² results

F i g. 10 is another, the F i g. 7 similar view that addresses the problem of "pyramid formation" er 2rdr _ 2xdx 2 wdw . purifies; ' x * x *. x * '

Figs. 11 and 12 are perspective views showing 4 °

Anisotropically etched mesa surfaces with a non-compensated. Simplification and substitution results show masked shape;

Fig. 13 is a diagram showing the difficulty ^rar _ i ^ _ ■ ^waw / ₅ \

the control of isotropic etching explained; _r a _ _w * _xr * _ _w ²

14 is a diagram of a mask shape showing 45

the limitation of compensating shapes explained. In the above equation (2), the expression di represents

An important feature of the invention is the Re- the time increment or the degree of temporal con-. The formulation of etchants that suitably differentiate the etching process. The term dR represents the etch rate required to provide the change in etch rate desired for the semiconductor device. In the general 5 ° ideal case, it is assumed that both dt and dÄ isotropic etching of semiconductor material is, for example, zero. Then dr also becomes zero and the left-hand side, the hydrofluoric acid-nitric acid side of equation (5) used as the etchant, also becomes zero, and the acidic mixture for silicon for a specific orientation cannot be made significant in absolute terms as follows Scope desirable. be written: As in Fig. 4, such an etchant has 55 _{dx w} a_ _w

the same etching speed in all directions =. (6)

and penetrates the semiconductor die 44 along a χ r ² - w ²

Thus, there is a considerable undercutting of the etched 6 ° of the edge 51 on the pane surface and has masked, which, for the purpose of the method, would desirably have a low value for the purpose of being good. However, the isotropic nature makes it in control. In the meantime, at the moment of "etching through, precise control of its termination" is difficult when the etching front 48 just accepts the wafer, if one has not cut through a substantial, almost pro-area 50, r approximately equal to w, hibitive overetching . This effect 65 _nd the right side of the equation (6) is infinite, in consideration of the F i g. 5, in which the isotropic etching masked only when r has become noticeably larger than w produces a groove, the value of the expression comes as a reasonable one that extends right through the semiconductor wafer 44. Size. A qualitative representation of this change

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is in the diagram of FIG. 8 shown. As of the can have an etching speed that is indicated by the curve, the edge speed (100) plane is comparable or less.
extremely high when χ is equal to w , ie in the eye. In FIG. 2, part of a (100) plane with a view of the "breakthrough" becomes. Then takes the edge-hypothetical section 41 shown. This speed out with increasing r decreases and approaches 5 section 41 can asymptotically be a constant value as a disk through the crystal underneath. One should consider, but think parallel to the (100) plane, that in all of the foregoing implicitly the cut, as contained on the upper surface of the crystal knowledge, is indicated by the slice thickness w model. The limits of the level weak changes shows how from the expression aw section 41 run parallel to the ■ cutting lines are reproduced. The current technology, also 10 (III) level with the (100) level.
the best educated, allows as an affair- In Fig. 3, the section 41 is moved to the side, meaning practical economy, the reduction in size and is shown with a partial adjoining (III) -plane fluctuations within a disk to less and indicates an ideal mesa figure, dated as a few tenths of a µ. Semiconductor material is accepted if it is aniso-

Accordingly, one must be etched when using the 15 trop according to the invention,
isotropic etching when a satisfactory control In Fig. 6 shows a mask 43 on the (100) plane of a silicon crystal 44 rapidly reached via the final layer (x) of the etch front 31, and a slot has been etched after, its refuge to the part of curve 8 below from the exposed part of the surface, take where χ is noticeably large. This results in a wider area which exposes the sides 49 of the groove and the (III) upper grooves and a consequently larger spacing 20 which is defined by the boundaries of the mask. As previously stated, the etching of the (III) plane lowing sides of the insulating grooves takes place, as in FIG. 5 at practically zero speed. The inclination of the sidewall forms an angle with the

In addition, the variation (dw) in the disk surface causes that of the crystallographic

Disk thickness (w) an etching tolerance around which the structure is determined. The value of the angle will be

break at the thickest points ensure what is expressed by the expression arc tang ψϊ and

a considerable overetching in the thinner areas corresponds to about 54.7 degrees of arc. Accordingly

causes. you can see that the etching down to the bottom of a

If one looks at Figs. 6, 7 and 9, the use of groove of decreasing width with constant Gsschwindig-

of the anisotropic etching according to the invention at the excess progresses through the etching rate

around this problem. It is known that the (100) -plane is determined, in contrast to that in

that certain chemical etchants with respect to certain- F i g. 4 and 5 for isotropic etching shown.

te crystal orientations preferred etching speed The advantage of this anisotropic etching is when

have opportunities. According to the invention, it was practically comparing FIGS. 7 with that of FIG. 5 honored,

found recipes for the special semiconductor material 35 which both involve etching a groove through a disk

and look for the shape you want. F i g. 2 shows show.

a model of a cubic silicon crystal showing the difficulties in controlling the position of the edge 51

three main crystallographic etch fronts of interest in the isotropic process are related

see planes, namely the (100) -, the (HO) - and those with F i g. 5 and 8. In the anisotropic

(lll) -plane represents. This designation corresponds to 40 procedures in FIG. 7 has the edge 51 of the etched front

the Miller index, and in the present description - at the moment of the breakthrough a speed

In practice, the designation system interprets an individuality component in the jc-direction and along the

duel level or a bevy of levels. The loading disk area 50 is zero. At this moment

clarity of these planes of low order, and hers is that. Etching ended, insofar as only the (IH) -

unique properties are exposed in relation to certain 45 surfaces on which the etching speed

Methods are known in crystallography. Monodiness is practically zero. So the point of

Crystalline semiconductor material in block form can create a »breakthrough« precisely the position of the mask edge

the previous three crystallographic orientations fixed on the back of the disk. Bsi this

owning. Accordingly, there is no risk of overetching and half-order

Conductor disks made transversely from such single crystal 50 despite no need for tolerance in the etching time

Blocks are cut, have larger areas that allow the change in thickness of the disc. The change in thickness

from one of the three levels (100), (110) and (111) requires only a slight deviation from the nominal

put together. Groove width to allow etching through at all etching

Secure in accordance with a preferred execution agency.

form of the invention it has been found advantageous to 55 F i g. 9 is a representation of the anisotropic

to provide monocrystalline silicon wafers, the driving of which corresponds to the isotropic in FIG. 8 shown image

larger surfaces run parallel to the (100) plane. corresponds to, and shows curves of the edge speed

The etchant of primary interest in connection speed for the etching process on the crystallographic

with this embodiment, namely the alkali levels of interest. For the anisotropic case is hydroxide, have a high etching speed to 60 the edge speed a constant that of

the (100) plane and its lowest etching speed - a straight line at the level of the corresponding etching

with respect to the (Hl) -plane. If a limiting speed of the relevant level

The area on the (100) level is presented to the etchant.

is bid, the downward attack runs parallel by avoiding the problem of over-zoing (100) -plane with high speed, but 65 etching, which exists with the isotropic technique,

laterally against the (Hl) surfaces with very little accordingly allows the anisotropic process

Speed that can be practically zero. Which have a considerably narrower spacing of the p-n over-

other levels of interest, such as the (HO) level, aisle 52, which is adjacent to the groove on the side of the device.

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The alkali hydroxides used as etchants, of course undesirable, insofar as the most useful

the device geometry borrowed in connection with this embodiment is rectangular or a

of the invention of interest are not just series of right angles.

with respect to the crystallographic orientation This effect can be compensated and so

of the monocrystalline silicon selectively, but also in 5 the right-angled geometry can be approximated

with respect to the silica. So silicon dioxide is one by having a compensation form in the

Standard masking material and is used in masking masks in the corners. This form can

shape using well-known photo-etching techniques, one of which is in

represents. Also consist in many integrated semi-FIG. 12 is shown. In Fig. 12, the sides of the

conductor circuits, especially in the above-mentioned io compensation form parallel to the section of the (Hl) -

air-insulated types layers of silicon dioxide levels and the starting level (100). The important one

especially on the device side of the circuit, and the consideration in relation to the compensation form for

Etching process does not allow the removal of this close fit to the rectangular geometry

Layers. is that the horizontally shaded areas 171 in

Therefore, in accordance with one embodiment, FIG. 14 will have to be masked and that no

form of the invention prohibits anisotropic etching outside of the vertically and horizontally shaded

relatively precise control at monocrystalline th region 172 is masked. Besides, each will

Silicon carried out by putting an etch mask to the best of your ability shape on the corners

aligns parallel to the (100) plane with the edges of the mask outside the limits of the initial

the mask mutually at right angles and parallel ao rectangle a certain compensation for the etching

to the intersection of the (III) -plane with the (100) -plane. of the edges. -.

This is an ideal configuration if the one used to achieve the rectangular geometry,

Etchant should have a high etching rate with respect to the dimension α in FIG. 14 be the same:
has the (100) plane and an etching speed of

practically zero in relation to the other two 35 ^a - * ^w / 2

Levels (HO) and (111). In the meantime it was established that ^wonn

that local disturbances and irregularities wäh- ^{k = R} iwl ^R iw> .

end of the etching process are sufficient to prevent the etching ^{and <} * ...

gang to prevent and the formation of pyramids. - . ^w ~ silicon thickness

cause the ^lst its peak in error or irregularity · 30

possess temperance. This effect is _{detected, for example, The} minimum average mask width on a polished surface that is scarred dimension:
and is etched. One can assume that a sufficient number of such pyramids have the practical / mm = 2 kw + b '
Interruption of the etching process in the (100) -plane 35 in which

^{he sides of the pyramids} b = the smallest non-zero groove

explains the effect of the pyramid width is that with the masking process

education. On the basis of any irregular- can be achieved,

speed in the top 201 , the pyramid 202 has grown 40 The minimum of the mesa dimension 63 on the

how the etching process progresses until finally your side is the device side:

intersect the (lll) plane and the groove walls 49 a, _ -, pr-,. ■

Leave part 203 to bridge the groove. ^ ¹ * ~ ** ^{w + Kw + 0-}

To exclude the formation of such pyramids, although the one described in the section above

the etchant is formulated in such a way that there is a 45 corner compensation especially for the crystallographic

The etching speed with respect to the (H0) plane, orientation is (100), the principle of corner

which lies between those of the (Hl) - and (100) -plane. Compensation through skillful application

This results in sufficient etching to create pyramids of special outlines on the mask on other crystal

to remove. Orientations as well as on specially shaped geo-

However, if the etchant is put together in such a way 5 ° metric dimensions are transferred,
is that this higher etch rate applies with respect to the (H0) plane application, the consideration of FIG. 11, as discussed herein, illustrates a consequent adverse effect a solution with 15g of potassium on the outer edges where the (Hl) planes intersect with hydroxide of commercial purity, 50 ml of water. · 55 and 15 ml of n-propanol. This special combination

F i g. 12 and 14 show a technique of compensating proved to be an etchant related to

sation by means of a mask in order to achieve this effect - ■ the (H0) plane an etching speed in the area

wind, and should therefore in connection with the three tenths to four tenths of the etching speed

the explanation below. with respect to the (100) -plane. The etching

F i g. 11 shows an etching mask 151 on which the speed to be etched is created by in the solution

the crystal 153. Influences potentials at the outer intersection of the (III) planes. The above-mentioned speed

If an undercut of the mask 151 occurs, which by three tenths to four tenths applies to the

the dashed line 152 is indicated. This un- etching of wired circuitry that de-

The intersection is related to the etching of the (H0) plane. The etch rate for pure silicon without

turns. This results in a deviation 65 existing metal is slightly less,

from the mask outline 151, as indicated by the dashed lines in a particular embodiment and below

Lines 152 to either side of the outer corners of the using the above composition in one

Crystal is reproduced. One such result is a temperature of around 85 ⁰ C, the etching speed

9 ίο

speeds of about 1.2 microns per minute at (100) - outlined. One can observe suitable crystallographic plane. In general, other techniques including goniometric methods employing alkali hydroxides, including those of sodium, can be used to determine the crystal orientation and the material used by cesium, lithium and rubidium alike by establishing a plane on it. To identify these different hydroxides in the ingot in a suitable manner, they differ primarily in the speed with which they attack silicon dioxide. It has been suggested that suitable standard etchants are used, handle speed of each of these etchants on silicon - for example, buffered hydrofluoric acid in aqueous solution, calcium dioxide can be reduced by the controlled addition of in order to remove the unmasked silicon dioxide. Far away the etching speed. Finally, the disk is immersed in the etchant speed on the (HO) level by changing the alkali hydroxide and anisotropic etching, by-product content of the etching solution and by the exact separation between parts of the same, the addition of lower alcohols such as methanol and such shown in the arrangement of Fig. 1, can be affected by too-ethanol instead of n-propanol. to lead. The rectangular platelets 112 to 123 will generally carry silicates that result from the etching 15 the isolated parts of the circuit. Each such flattening process can result, one or more switching elements can contain speed (110) to increase the etching rate. Other suitable etchants could be used. The structure in the assembly is applied by a plurality of wire leads 126 of a similar type employing organic reagents which are capable of creating free hydroxyl type of wiring connection 125 for ionization, including the amines, such as 20 bond supported outward. The pyramid sides ethylenediamine and water. of the different parts of the circuit, how to make them

In a special embodiment according to see from the rear etched surface, the

Invention is a disk made of semiconducting SiIi- anisotropic etching.

cium according to the teachings of the aforementioned French. As suggested below, the here See the anisotropic etching technique described in U.S. Patent 1,417,760 and U.S. Patent 35, respectively 3 287 612 for the purpose of making an air-insulated mono- a process can be used in which one lithen or the in F i g. 1, wishes to display only a predetermined depth of material. For this purpose, a disk is prepared instead of etching through the entire material. One or more masked diffusion techniques are useful in processes such as subjected to solid state treatments to the extent of that described in U.S. Patent 3,290,753 mentioned above one side of the body switching elements, such as transcriptions, which have been referred to as the EPIC process sistors, diodes and resistors. Is on. Such an EPIC procedure will be a mess Side of the disc are simplified according to the invention to an extent that wired metal connections are made, and they usually use a suitable thermal oxide film will eventually be available for the final cutting process 35, insofar as the grooving prepared according to the invention. is one of the first steps in manufacturing.

To this end, the wired side is mounted down under the anisotropic etch technique provides a simple way of creating fabrication using a suitable permanent material and typically from a number such as on the wafer 122 of FIG. 1 ge thickness from about 12.7 x 10 ^-3 cm to about 5.1 x 10 ^-3 cm 40. Such figures are machined down from unconnected or ³ inches by 3 inches. The surface made up of grooves and thus avoiding corners is then pulled over with a film of silicon dioxide and making the process self-terminating, which serves as a rear etch mask. at a depth that is fixed by the width of the groove. It

It will be noted that the semiconductor wafer through is of course important, the etching through the wafer

treatment with higher temperatures is disadvantageous while avoiding grooves that are too wide for this purpose

can be influenced, making the formation of a silicon impossible.

dioxide films are necessary. It is therefore important, although the procedure is carried out so far on the basis of a form

that an intimate, firmly adhering oxide layer has been described by environment technology, in the one

a comparatively lower temperature process of the lower order crystallographic planes

forms. In particular, it is important that the formation has an etching rate of practically zero,

Which intermediate layers of rapidly etchable material is understood that the shaping technology

to prevent the separation of the mask layer can be carried out controllably if this

from silicon. Speed sufficiently lower than that of the

One technique for obtaining a satisfactory two other levels is. Such a system, silicon dioxide layer on the backside of wafer 55, although useful, will not be so beneficial from the standpoint of self-finishing as a first step an anodic oxidation etch. In addition to the use of silicon dioxide as a mask for the purpose of forming a thin layer of silicon, dioxide. (Such a method is described, for example, in the earlier application W 43 825, which requires other materials than masks.) The anodic, including other dielectrically formed surface, is then 60 trica in a vacuum, such as silicon nitride,
sputtered back to clean them and then in situ The foregoing description is from the point of view of treating single crystal substrates to form an oxide layer of about 6,000 to conductors of silicon from an electron beam evaporation process. A person skilled in the art can form a thickness of 10 CCO Ae or with a thickness which is sufficient for whom it is clear that this method generally applies to other etching times. 65 monocrystalline semiconductor material of similar crystallo-

The next step is the photo-etching mask on the graphic structure, including the germanium,

Oxide area is formed and the boundaries of the mask with as well as the well-known semiconductor compounds

aligned with the cuts of the (III) plane, as can be applied above by the AmBv group. the

Etchant formulations will differ for the different Change connections. Meanwhile, according to the present invention, the precise etching is performed the knowledge and the application of different etching speeds, which under the three 5 crystallographic levels of low order prevail, which are characteristic for these substances.

In connection with such processes in compound semiconductors, it will be appreciated that a different etching success occurs, which depends on the two elements of the connection which prevail in the special layer. Specifically, for example, in the case of a gallium arsenide crystal when considering the model of FIG. 4 the (III) plane shown in the center of the model predominates of gallium atoms. On the other hand, this (lll) level, which is on the opposite underside of the model, arsenic atoms predominate. Accordingly The etchant can be selected so that not only can one take advantage of the primary crystallographic Orientation draws, but in the case of composite semiconductors also from the factor which of the levels is exposed.

The etchants that attack the (110) -plane can be formulated to work with a attack the (100) plane at a comparable etching speed. In such an arrangement in which the (110) plane is the primary etch plane, the mask edges become parallel to the cuts of the (HO) plane with the different (Hl) - and (110) planes arranged. The mask edges then do not stand necessarily at right angles to each other, and become different through the etching process Mesa configurations formed. It is important to do the 3s geometric effectiveness of the generated outlines from the standpoint of the compactness of the devices regard.

In any system, the considerations for obtaining a precise etch remain such that Interference effects of disturbances and irregularities are avoided, as well as the associated Undercutting at corners.

Accordingly, it is also understood that modifications of the preceding specific teaching can be made by those skilled in the art can be made, which, however, are still within the spirit and scope of the invention lie. For example, it is clear to those skilled in the art that systems of crystal planes other than those lower order can be used.

Claims (12)

Patent claims: 1. Method for producing shaping etchings on a monocrystalline semiconductor wafer with at least a first, second and third low-order crystallographic level, wherein the main surfaces of the semiconductor wafer lie in the first crystallographic plane, by etching one of the main surfaces provided with an etching mask, characterized in that that the semiconductor wafer is provided with an etching mask, the edges of which are parallel to the lines of intersection formed by the first (100) and second (111) crystallographic planes run, and in a manner known per se, the semiconductor material in different crystal directions different degrees of attacking etching solution, which has a relatively high etching speed in the first level (100), a relatively low etching speed in the second level (111) and an average etching rate lying between these two etching rates in the third level (110) is etched. 2. The method according to claim 1, characterized in that the semiconductor wafer with an etching solution is etched whose etching speed in the second plane (111) is practically zero. 3. The method according to claim 1 or 2, characterized in that the semiconductor wafer with a Etching mask is provided to compensate for the etching attack preferred at the outer corners is formed at these corners in a compensation shape, the dimensions of the compensation shape the ratio of the etching speed in the third level (HO) to the etching speed in the first level (100). 4. The method according to claims 1 to 3, characterized in that a semiconductor wafer made of silicon, germanium or an AniBv compound is etched. 5. The method according to claim 4, characterized in that that the silicon wafer is etched with an etching solution that is produced during the etching process supplies free hydroxyl ions. 6. The method according to claim 5, characterized in that the silicon wafer with an aqueous Solution of amines is etched. 7. The method according to claim 5, characterized in that the silicon wafer with a solution which contains a hydroxide of the alkali metals sodium, potassium, cesium and rubidium. 8. The method according to claim 7, characterized in that the silicon wafer with a solution which contains an alcohol. 9. The method according to claim 7, characterized in that that a silicon wafer is provided with an etching mask, the mask edges in are arranged at right angles to each other, and with a solution of potassium hydroxide, water and n-propanol is etched. 10. The method according to claim 9, characterized in that the masked silicon wafer is etched with a solution consisting of 15 g of potassium hydroxide (commercial grade), 50 ml of water and 15 ml of n-propanol. 11. The method according to claim 10, characterized in that the masked silicon wafer with the etching solution at a temperature of 85 ° C is etched. 12. The method according to claims 1 to -11, characterized in that the semiconductor wafer is provided with an etching mask, the adjacent Edges limit an unmasked part of the surface so that the etching process through the Wafer advances and comes to a standstill by itself. For this purpose 2 sheets of drawings