DE112020007758T5 - Halbleitereinheit und leistungswandlereinheit - Google Patents

Halbleitereinheit und leistungswandlereinheit Download PDF

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Publication number
DE112020007758T5
DE112020007758T5 DE112020007758.6T DE112020007758T DE112020007758T5 DE 112020007758 T5 DE112020007758 T5 DE 112020007758T5 DE 112020007758 T DE112020007758 T DE 112020007758T DE 112020007758 T5 DE112020007758 T5 DE 112020007758T5
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DE
Germany
Prior art keywords
outer peripheral
region
layer
insulating layer
end portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE112020007758.6T
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German (de)
English (en)
Inventor
Kohei Ebihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE112020007758T5 publication Critical patent/DE112020007758T5/de
Pending legal-status Critical Current

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/665Vertical DMOS [VDMOS] FETs having edge termination structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325Silicon carbide
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/111Field plates
    • H10D64/112Field plates comprising multiple field plate segments

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  • Electrodes Of Semiconductors (AREA)
DE112020007758.6T 2020-11-06 2020-11-06 Halbleitereinheit und leistungswandlereinheit Pending DE112020007758T5 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/041487 WO2022097262A1 (ja) 2020-11-06 2020-11-06 半導体装置および電力変換装置

Publications (1)

Publication Number Publication Date
DE112020007758T5 true DE112020007758T5 (de) 2023-08-17

Family

ID=81457053

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112020007758.6T Pending DE112020007758T5 (de) 2020-11-06 2020-11-06 Halbleitereinheit und leistungswandlereinheit

Country Status (5)

Country Link
US (1) US12464767B2 (https=)
JP (1) JP7459292B2 (https=)
CN (1) CN116368623B (https=)
DE (1) DE112020007758T5 (https=)
WO (1) WO2022097262A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025074874A1 (ja) * 2023-10-05 2025-04-10 ローム株式会社 半導体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014087600A1 (ja) 2012-12-04 2014-06-12 株式会社デンソー 半導体装置およびその製造方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5026019B2 (ja) * 2006-08-08 2012-09-12 三菱電機株式会社 薄膜トランジスタ基板、薄膜トランジスタの製造方法、及び表示装置
JP4793293B2 (ja) 2007-03-16 2011-10-12 日産自動車株式会社 炭化珪素半導体装置及びその製造方法
JP5370480B2 (ja) 2009-04-30 2013-12-18 三菱電機株式会社 半導体装置及びその製造方法
JP5751763B2 (ja) * 2010-06-07 2015-07-22 三菱電機株式会社 半導体装置
JP5687128B2 (ja) * 2011-05-06 2015-03-18 三菱電機株式会社 半導体装置およびその製造方法
JP5677222B2 (ja) 2011-07-25 2015-02-25 三菱電機株式会社 炭化珪素半導体装置
JP5640969B2 (ja) 2011-12-26 2014-12-17 三菱電機株式会社 半導体素子
JP6617292B2 (ja) * 2014-05-23 2019-12-11 パナソニックIpマネジメント株式会社 炭化珪素半導体装置
WO2018038133A1 (ja) 2016-08-25 2018-03-01 三菱電機株式会社 炭化珪素半導体装置
US11094790B2 (en) * 2016-09-23 2021-08-17 Mitsubishi Electric Corporation Silicon carbide semiconductor device
US9985125B1 (en) 2016-11-25 2018-05-29 Panasonic Intellectual Property Management Co., Ltd. Silicon carbide semiconductor device
CN110337725B (zh) 2017-02-24 2022-08-05 三菱电机株式会社 碳化硅半导体装置以及电力变换装置
US11355629B2 (en) 2017-03-07 2022-06-07 Mitsubishi Electric Corporation Semiconductor device and power converter
JP7013735B2 (ja) * 2017-09-05 2022-02-01 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
JP7000240B2 (ja) * 2018-04-18 2022-01-19 ルネサスエレクトロニクス株式会社 半導体装置
JP7085959B2 (ja) * 2018-10-22 2022-06-17 三菱電機株式会社 半導体装置
JP6870119B2 (ja) * 2019-04-11 2021-05-12 三菱電機株式会社 半導体装置および電力変換装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014087600A1 (ja) 2012-12-04 2014-06-12 株式会社デンソー 半導体装置およびその製造方法

Also Published As

Publication number Publication date
JPWO2022097262A1 (https=) 2022-05-12
US12464767B2 (en) 2025-11-04
WO2022097262A1 (ja) 2022-05-12
US20230378342A1 (en) 2023-11-23
JP7459292B2 (ja) 2024-04-01
CN116368623A (zh) 2023-06-30
CN116368623B (zh) 2025-07-29

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