DE112014001279B4 - Bearbeitungsverfahren einer Silizium-auf-Isolator-Struktur zur Verminderung von Licht-Punkt-Defekten und Oberflächenrauigkeit - Google Patents

Bearbeitungsverfahren einer Silizium-auf-Isolator-Struktur zur Verminderung von Licht-Punkt-Defekten und Oberflächenrauigkeit Download PDF

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Publication number
DE112014001279B4
DE112014001279B4 DE112014001279.3T DE112014001279T DE112014001279B4 DE 112014001279 B4 DE112014001279 B4 DE 112014001279B4 DE 112014001279 T DE112014001279 T DE 112014001279T DE 112014001279 B4 DE112014001279 B4 DE 112014001279B4
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silicon
insulator structure
silicon layer
layer
environment
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German (de)
English (en)
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DE112014001279T5 (de
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Qingmin Liu
Jeffrey Louis Libbert
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GlobalWafers Co Ltd
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GlobalWafers Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H10P95/906—Thermal treatments, e.g. annealing or sintering for altering the shape of semiconductors, e.g. smoothing the surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H10P36/07—Gettering within semiconductor bodies within silicon bodies of silicon-on-insulator structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Element Separation (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Recrystallisation Techniques (AREA)
DE112014001279.3T 2013-03-14 2014-03-14 Bearbeitungsverfahren einer Silizium-auf-Isolator-Struktur zur Verminderung von Licht-Punkt-Defekten und Oberflächenrauigkeit Active DE112014001279B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201361783928P 2013-03-14 2013-03-14
US61/783,928 2013-03-14
PCT/US2014/027418 WO2014152510A1 (en) 2013-03-14 2014-03-14 Semiconductor-on-insulator wafer manufacturing method for reducing light point defects and surface roughness

Publications (2)

Publication Number Publication Date
DE112014001279T5 DE112014001279T5 (de) 2015-11-26
DE112014001279B4 true DE112014001279B4 (de) 2019-01-24

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Country Status (7)

Country Link
US (1) US9202711B2 (https=)
JP (1) JP6373354B2 (https=)
KR (1) KR102027205B1 (https=)
CN (1) CN105431936B (https=)
DE (1) DE112014001279B4 (https=)
TW (1) TWI598961B (https=)
WO (1) WO2014152510A1 (https=)

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US9853133B2 (en) * 2014-09-04 2017-12-26 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity silicon-on-insulator substrate
US9899499B2 (en) 2014-09-04 2018-02-20 Sunedison Semiconductor Limited (Uen201334164H) High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss
EP3221885B1 (en) 2014-11-18 2019-10-23 GlobalWafers Co., Ltd. High resistivity semiconductor-on-insulator wafer and a method of manufacturing
WO2016081367A1 (en) 2014-11-18 2016-05-26 Sunedison Semiconductor Limited HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED BY He-N2 CO-IMPLANTATION
EP3221884B1 (en) 2014-11-18 2022-06-01 GlobalWafers Co., Ltd. High resistivity semiconductor-on-insulator wafers with charge trapping layers and method of manufacturing thereof
US10283402B2 (en) 2015-03-03 2019-05-07 Globalwafers Co., Ltd. Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
WO2016149113A1 (en) 2015-03-17 2016-09-22 Sunedison Semiconductor Limited Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures
US9881832B2 (en) 2015-03-17 2018-01-30 Sunedison Semiconductor Limited (Uen201334164H) Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof
JP2016201454A (ja) * 2015-04-09 2016-12-01 信越半導体株式会社 Ｓｏｉウェーハの製造方法
WO2016196060A1 (en) 2015-06-01 2016-12-08 Sunedison Semiconductor Limited A method of manufacturing semiconductor-on-insulator
EP3739620B1 (en) 2015-06-01 2022-02-16 GlobalWafers Co., Ltd. A silicon germanium-on-insulator structure
KR102424963B1 (ko) 2015-07-30 2022-07-25 삼성전자주식회사 집적회로 소자 및 그 제조 방법
JP6749394B2 (ja) 2015-11-20 2020-09-02 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． 滑らかな半導体表面の製造方法
FR3046877B1 (fr) 2016-01-14 2018-01-19 Soitec Procede de lissage de la surface d'une structure
WO2017142704A1 (en) 2016-02-19 2017-08-24 Sunedison Semiconductor Limited High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface
US9831115B2 (en) 2016-02-19 2017-11-28 Sunedison Semiconductor Limited (Uen201334164H) Process flow for manufacturing semiconductor on insulator structures in parallel
US10622247B2 (en) 2016-02-19 2020-04-14 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a buried high resistivity layer
WO2017155806A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof
US11114332B2 (en) 2016-03-07 2021-09-07 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof
EP3427293B1 (en) 2016-03-07 2021-05-05 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof
US11848227B2 (en) 2016-03-07 2023-12-19 Globalwafers Co., Ltd. Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment
EP3469120B1 (en) 2016-06-08 2022-02-02 GlobalWafers Co., Ltd. High resistivity single crystal silicon ingot and wafer having improved mechanical strength
US10269617B2 (en) 2016-06-22 2019-04-23 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising an isolation region
WO2018080772A1 (en) 2016-10-26 2018-05-03 Sunedison Semiconductor Limited High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency
US10468295B2 (en) 2016-12-05 2019-11-05 GlobalWafers Co. Ltd. High resistivity silicon-on-insulator structure and method of manufacture thereof
JP7110204B2 (ja) 2016-12-28 2022-08-01 サンエディソン・セミコンダクター・リミテッド イントリンシックゲッタリングおよびゲート酸化物完全性歩留まりを有するシリコンウエハを処理する方法
FR3061988B1 (fr) * 2017-01-13 2019-11-01 Soitec Procede de lissage de surface d'un substrat semiconducteur sur isolant
SG11201913769RA (en) 2017-07-14 2020-01-30 Sunedison Semiconductor Ltd Method of manufacture of a semiconductor on insulator structure
EP3728704B1 (en) * 2017-12-21 2023-02-01 GlobalWafers Co., Ltd. Method of treating a single crystal silicon ingot to improve the lls ring/core pattern
SG11202009989YA (en) 2018-04-27 2020-11-27 Globalwafers Co Ltd Light assisted platelet formation facilitating layer transfer from a semiconductor donor substrate
WO2019236320A1 (en) 2018-06-08 2019-12-12 Globalwafers Co., Ltd. Method for transfer of a thin layer of silicon
CN112420915B (zh) * 2020-11-23 2022-12-23 济南晶正电子科技有限公司 复合衬底的制备方法、复合薄膜及电子元器件
CN115884589A (zh) * 2021-09-27 2023-03-31 长鑫存储技术有限公司 一种半导体结构及其制备方法
US20250069945A1 (en) 2023-08-24 2025-02-27 Globalwafers Co., Ltd. Methods of preparing silicon-on-insulator structures using epitaxial wafers
FR3159469A1 (fr) * 2024-02-15 2025-08-22 Soitec Procédé de lissage des surfaces libres et rugueuses d’une pluralité de substrats de silicium sur isolant
US20250293073A1 (en) 2024-03-18 2025-09-18 Globalwafers Co., Ltd. Reclaimable donor substrates for use in preparing multiple silicon-on-insulator structures
US20260005066A1 (en) 2024-06-28 2026-01-01 Globalwafers Co., Ltd. Methods for controlling flatness of handle structures for use in semiconductor-on-insulator structures
US20260015728A1 (en) 2024-07-10 2026-01-15 Globalwafers Co., Ltd. Systems and methods for reactor apparatus control during semiconductor wafer processes
US20260018457A1 (en) 2024-07-10 2026-01-15 Globalwafers Co., Ltd. Methods of processing semiconductor-on-insulator structures using clean-and-etch operation

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US5436175A (en) 1993-10-04 1995-07-25 Sharp Microelectronics Technology, Inc. Shallow SIMOX processing method using molecular ion implantation
US20020174828A1 (en) * 2001-03-30 2002-11-28 Memc Electronic Materials, Inc. Thermal annealing process for producing silicon wafers with improved surface characteristics
US6790747B2 (en) 1997-05-12 2004-09-14 Silicon Genesis Corporation Method and device for controlled cleaving process
US20100130021A1 (en) * 2008-11-26 2010-05-27 Memc Electronic Materials, Inc. Method for processing a silicon-on-insulator structure

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US5189500A (en) 1989-09-22 1993-02-23 Mitsubishi Denki Kabushiki Kaisha Multi-layer type semiconductor device with semiconductor element layers stacked in opposite directions and manufacturing method thereof
US5436175A (en) 1993-10-04 1995-07-25 Sharp Microelectronics Technology, Inc. Shallow SIMOX processing method using molecular ion implantation
US6790747B2 (en) 1997-05-12 2004-09-14 Silicon Genesis Corporation Method and device for controlled cleaving process
US20020174828A1 (en) * 2001-03-30 2002-11-28 Memc Electronic Materials, Inc. Thermal annealing process for producing silicon wafers with improved surface characteristics
US20100130021A1 (en) * 2008-11-26 2010-05-27 Memc Electronic Materials, Inc. Method for processing a silicon-on-insulator structure

Also Published As

Publication number Publication date
US9202711B2 (en) 2015-12-01
WO2014152510A1 (en) 2014-09-25
US20140273405A1 (en) 2014-09-18
KR20150132383A (ko) 2015-11-25
CN105431936A (zh) 2016-03-23
JP2016516304A (ja) 2016-06-02
KR102027205B1 (ko) 2019-10-01
DE112014001279T5 (de) 2015-11-26
TWI598961B (zh) 2017-09-11
JP6373354B2 (ja) 2018-08-15
TW201448046A (zh) 2014-12-16
CN105431936B (zh) 2018-07-13

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