KR102027205B1 - 광점 결함들 및 표면 거칠기를 감소시키기 위한 반도체-온-인슐레이터 웨이퍼 제조 방법 - Google Patents

광점 결함들 및 표면 거칠기를 감소시키기 위한 반도체-온-인슐레이터 웨이퍼 제조 방법 Download PDF

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KR102027205B1
KR102027205B1 KR1020157029121A KR20157029121A KR102027205B1 KR 102027205 B1 KR102027205 B1 KR 102027205B1 KR 1020157029121 A KR1020157029121 A KR 1020157029121A KR 20157029121 A KR20157029121 A KR 20157029121A KR 102027205 B1 KR102027205 B1 KR 102027205B1
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silicon
silicon layer
dielectric layer
smoothing process
environment
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KR20150132383A (ko
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칭민 류
제프리 루이스 리버트
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글로벌웨이퍼스 씨오., 엘티디.
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    • H01L21/3247—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H10P95/906—Thermal treatments, e.g. annealing or sintering for altering the shape of semiconductors, e.g. smoothing the surface
    • H01L21/302—
    • H01L21/3065—
    • H01L21/3226—
    • H01L21/76254—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H10P36/07—Gettering within semiconductor bodies within silicon bodies of silicon-on-insulator structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Element Separation (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Recrystallisation Techniques (AREA)
KR1020157029121A 2013-03-14 2014-03-14 광점 결함들 및 표면 거칠기를 감소시키기 위한 반도체-온-인슐레이터 웨이퍼 제조 방법 Active KR102027205B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201361783928P 2013-03-14 2013-03-14
US61/783,928 2013-03-14
PCT/US2014/027418 WO2014152510A1 (en) 2013-03-14 2014-03-14 Semiconductor-on-insulator wafer manufacturing method for reducing light point defects and surface roughness

Publications (2)

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KR20150132383A KR20150132383A (ko) 2015-11-25
KR102027205B1 true KR102027205B1 (ko) 2019-10-01

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US (1) US9202711B2 (https=)
JP (1) JP6373354B2 (https=)
KR (1) KR102027205B1 (https=)
CN (1) CN105431936B (https=)
DE (1) DE112014001279B4 (https=)
TW (1) TWI598961B (https=)
WO (1) WO2014152510A1 (https=)

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WO2017142704A1 (en) 2016-02-19 2017-08-24 Sunedison Semiconductor Limited High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface
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WO2018080772A1 (en) 2016-10-26 2018-05-03 Sunedison Semiconductor Limited High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency
US10468295B2 (en) 2016-12-05 2019-11-05 GlobalWafers Co. Ltd. High resistivity silicon-on-insulator structure and method of manufacture thereof
JP7110204B2 (ja) 2016-12-28 2022-08-01 サンエディソン・セミコンダクター・リミテッド イントリンシックゲッタリングおよびゲート酸化物完全性歩留まりを有するシリコンウエハを処理する方法
FR3061988B1 (fr) * 2017-01-13 2019-11-01 Soitec Procede de lissage de surface d'un substrat semiconducteur sur isolant
SG11201913769RA (en) 2017-07-14 2020-01-30 Sunedison Semiconductor Ltd Method of manufacture of a semiconductor on insulator structure
EP3728704B1 (en) * 2017-12-21 2023-02-01 GlobalWafers Co., Ltd. Method of treating a single crystal silicon ingot to improve the lls ring/core pattern
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CN112420915B (zh) * 2020-11-23 2022-12-23 济南晶正电子科技有限公司 复合衬底的制备方法、复合薄膜及电子元器件
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Publication number Publication date
US9202711B2 (en) 2015-12-01
WO2014152510A1 (en) 2014-09-25
US20140273405A1 (en) 2014-09-18
DE112014001279B4 (de) 2019-01-24
KR20150132383A (ko) 2015-11-25
CN105431936A (zh) 2016-03-23
JP2016516304A (ja) 2016-06-02
DE112014001279T5 (de) 2015-11-26
TWI598961B (zh) 2017-09-11
JP6373354B2 (ja) 2018-08-15
TW201448046A (zh) 2014-12-16
CN105431936B (zh) 2018-07-13

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