TWI598961B - 用於減少光點缺陷及表面粗糙度之絕緣體上半導體晶圓的製造方法 - Google Patents
用於減少光點缺陷及表面粗糙度之絕緣體上半導體晶圓的製造方法 Download PDFInfo
- Publication number
- TWI598961B TWI598961B TW103109754A TW103109754A TWI598961B TW I598961 B TWI598961 B TW I598961B TW 103109754 A TW103109754 A TW 103109754A TW 103109754 A TW103109754 A TW 103109754A TW I598961 B TWI598961 B TW I598961B
- Authority
- TW
- Taiwan
- Prior art keywords
- wafer
- germanium
- germanium layer
- layer
- handle wafer
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/90—Thermal treatments, e.g. annealing or sintering
- H10P95/906—Thermal treatments, e.g. annealing or sintering for altering the shape of semiconductors, e.g. smoothing the surface
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P36/00—Gettering within semiconductor bodies
- H10P36/03—Gettering within semiconductor bodies within silicon bodies
- H10P36/07—Gettering within semiconductor bodies within silicon bodies of silicon-on-insulator structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
- H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Landscapes
- Element Separation (AREA)
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Plasma & Fusion (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361783928P | 2013-03-14 | 2013-03-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201448046A TW201448046A (zh) | 2014-12-16 |
| TWI598961B true TWI598961B (zh) | 2017-09-11 |
Family
ID=50440875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW103109754A TWI598961B (zh) | 2013-03-14 | 2014-03-14 | 用於減少光點缺陷及表面粗糙度之絕緣體上半導體晶圓的製造方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US9202711B2 (https=) |
| JP (1) | JP6373354B2 (https=) |
| KR (1) | KR102027205B1 (https=) |
| CN (1) | CN105431936B (https=) |
| DE (1) | DE112014001279B4 (https=) |
| TW (1) | TWI598961B (https=) |
| WO (1) | WO2014152510A1 (https=) |
Families Citing this family (40)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015112308A1 (en) | 2014-01-23 | 2015-07-30 | Sunedison Semiconductor Limited | High resistivity soi wafers and a method of manufacturing thereof |
| US9853133B2 (en) * | 2014-09-04 | 2017-12-26 | Sunedison Semiconductor Limited (Uen201334164H) | Method of manufacturing high resistivity silicon-on-insulator substrate |
| US9899499B2 (en) | 2014-09-04 | 2018-02-20 | Sunedison Semiconductor Limited (Uen201334164H) | High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss |
| EP3221885B1 (en) | 2014-11-18 | 2019-10-23 | GlobalWafers Co., Ltd. | High resistivity semiconductor-on-insulator wafer and a method of manufacturing |
| WO2016081367A1 (en) | 2014-11-18 | 2016-05-26 | Sunedison Semiconductor Limited | HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED BY He-N2 CO-IMPLANTATION |
| EP3221884B1 (en) | 2014-11-18 | 2022-06-01 | GlobalWafers Co., Ltd. | High resistivity semiconductor-on-insulator wafers with charge trapping layers and method of manufacturing thereof |
| US10283402B2 (en) | 2015-03-03 | 2019-05-07 | Globalwafers Co., Ltd. | Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress |
| WO2016149113A1 (en) | 2015-03-17 | 2016-09-22 | Sunedison Semiconductor Limited | Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures |
| US9881832B2 (en) | 2015-03-17 | 2018-01-30 | Sunedison Semiconductor Limited (Uen201334164H) | Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof |
| JP2016201454A (ja) * | 2015-04-09 | 2016-12-01 | 信越半導体株式会社 | Ｓｏｉウェーハの製造方法 |
| WO2016196060A1 (en) | 2015-06-01 | 2016-12-08 | Sunedison Semiconductor Limited | A method of manufacturing semiconductor-on-insulator |
| EP3739620B1 (en) | 2015-06-01 | 2022-02-16 | GlobalWafers Co., Ltd. | A silicon germanium-on-insulator structure |
| KR102424963B1 (ko) | 2015-07-30 | 2022-07-25 | 삼성전자주식회사 | 집적회로 소자 및 그 제조 방법 |
| JP6749394B2 (ja) | 2015-11-20 | 2020-09-02 | グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． | 滑らかな半導体表面の製造方法 |
| FR3046877B1 (fr) | 2016-01-14 | 2018-01-19 | Soitec | Procede de lissage de la surface d'une structure |
| WO2017142704A1 (en) | 2016-02-19 | 2017-08-24 | Sunedison Semiconductor Limited | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface |
| US9831115B2 (en) | 2016-02-19 | 2017-11-28 | Sunedison Semiconductor Limited (Uen201334164H) | Process flow for manufacturing semiconductor on insulator structures in parallel |
| US10622247B2 (en) | 2016-02-19 | 2020-04-14 | Globalwafers Co., Ltd. | Semiconductor on insulator structure comprising a buried high resistivity layer |
| WO2017155806A1 (en) | 2016-03-07 | 2017-09-14 | Sunedison Semiconductor Limited | Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof |
| US11114332B2 (en) | 2016-03-07 | 2021-09-07 | Globalwafers Co., Ltd. | Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof |
| EP3427293B1 (en) | 2016-03-07 | 2021-05-05 | Globalwafers Co., Ltd. | Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof |
| US11848227B2 (en) | 2016-03-07 | 2023-12-19 | Globalwafers Co., Ltd. | Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment |
| EP3469120B1 (en) | 2016-06-08 | 2022-02-02 | GlobalWafers Co., Ltd. | High resistivity single crystal silicon ingot and wafer having improved mechanical strength |
| US10269617B2 (en) | 2016-06-22 | 2019-04-23 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising an isolation region |
| WO2018080772A1 (en) | 2016-10-26 | 2018-05-03 | Sunedison Semiconductor Limited | High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency |
| US10468295B2 (en) | 2016-12-05 | 2019-11-05 | GlobalWafers Co. Ltd. | High resistivity silicon-on-insulator structure and method of manufacture thereof |
| JP7110204B2 (ja) | 2016-12-28 | 2022-08-01 | サンエディソン・セミコンダクター・リミテッド | イントリンシックゲッタリングおよびゲート酸化物完全性歩留まりを有するシリコンウエハを処理する方法 |
| FR3061988B1 (fr) * | 2017-01-13 | 2019-11-01 | Soitec | Procede de lissage de surface d'un substrat semiconducteur sur isolant |
| SG11201913769RA (en) | 2017-07-14 | 2020-01-30 | Sunedison Semiconductor Ltd | Method of manufacture of a semiconductor on insulator structure |
| EP3728704B1 (en) * | 2017-12-21 | 2023-02-01 | GlobalWafers Co., Ltd. | Method of treating a single crystal silicon ingot to improve the lls ring/core pattern |
| SG11202009989YA (en) | 2018-04-27 | 2020-11-27 | Globalwafers Co Ltd | Light assisted platelet formation facilitating layer transfer from a semiconductor donor substrate |
| WO2019236320A1 (en) | 2018-06-08 | 2019-12-12 | Globalwafers Co., Ltd. | Method for transfer of a thin layer of silicon |
| CN112420915B (zh) * | 2020-11-23 | 2022-12-23 | 济南晶正电子科技有限公司 | 复合衬底的制备方法、复合薄膜及电子元器件 |
| CN115884589A (zh) * | 2021-09-27 | 2023-03-31 | 长鑫存储技术有限公司 | 一种半导体结构及其制备方法 |
| US20250069945A1 (en) | 2023-08-24 | 2025-02-27 | Globalwafers Co., Ltd. | Methods of preparing silicon-on-insulator structures using epitaxial wafers |
| FR3159469A1 (fr) * | 2024-02-15 | 2025-08-22 | Soitec | Procédé de lissage des surfaces libres et rugueuses d’une pluralité de substrats de silicium sur isolant |
| US20250293073A1 (en) | 2024-03-18 | 2025-09-18 | Globalwafers Co., Ltd. | Reclaimable donor substrates for use in preparing multiple silicon-on-insulator structures |
| US20260005066A1 (en) | 2024-06-28 | 2026-01-01 | Globalwafers Co., Ltd. | Methods for controlling flatness of handle structures for use in semiconductor-on-insulator structures |
| US20260015728A1 (en) | 2024-07-10 | 2026-01-15 | Globalwafers Co., Ltd. | Systems and methods for reactor apparatus control during semiconductor wafer processes |
| US20260018457A1 (en) | 2024-07-10 | 2026-01-15 | Globalwafers Co., Ltd. | Methods of processing semiconductor-on-insulator structures using clean-and-etch operation |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2617798B2 (ja) | 1989-09-22 | 1997-06-04 | 三菱電機株式会社 | 積層型半導体装置およびその製造方法 |
| EP0553852B1 (en) * | 1992-01-30 | 2003-08-20 | Canon Kabushiki Kaisha | Process for producing semiconductor substrate |
| JPH07106512A (ja) | 1993-10-04 | 1995-04-21 | Sharp Corp | 分子イオン注入を用いたｓｉｍｏｘ処理方法 |
| US6033974A (en) | 1997-05-12 | 2000-03-07 | Silicon Genesis Corporation | Method for controlled cleaving process |
| FR2777115B1 (fr) | 1998-04-07 | 2001-07-13 | Commissariat Energie Atomique | Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede |
| JP3358550B2 (ja) * | 1998-07-07 | 2002-12-24 | 信越半導体株式会社 | Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ |
| JP2000124092A (ja) | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ |
| US6743495B2 (en) * | 2001-03-30 | 2004-06-01 | Memc Electronic Materials, Inc. | Thermal annealing process for producing silicon wafers with improved surface characteristics |
| TW550681B (en) * | 2001-06-22 | 2003-09-01 | Memc Electronic Materials | Process for producing silicon on insulator structure having intrinsic gettering by ion implantation |
| JPWO2003046993A1 (ja) * | 2001-11-29 | 2005-04-14 | 信越半導体株式会社 | Ｓｏｉウェーハの製造方法 |
| US20040060899A1 (en) * | 2002-10-01 | 2004-04-01 | Applied Materials, Inc. | Apparatuses and methods for treating a silicon film |
| JP2006210899A (ja) * | 2004-12-28 | 2006-08-10 | Shin Etsu Chem Co Ltd | Ｓｏｉウエーハの製造方法及びｓｏｉウェーハ |
| JP2006294737A (ja) * | 2005-04-07 | 2006-10-26 | Sumco Corp | Ｓｏｉ基板の製造方法及びその製造における剥離ウェーハの再生処理方法。 |
| JP2007059704A (ja) * | 2005-08-25 | 2007-03-08 | Sumco Corp | 貼合せ基板の製造方法及び貼合せ基板 |
| KR100972213B1 (ko) * | 2005-12-27 | 2010-07-26 | 신에쓰 가가꾸 고교 가부시끼가이샤 | Ｓｏｉ 웨이퍼의 제조 방법 및 ｓｏｉ 웨이퍼 |
| JP5082299B2 (ja) * | 2006-05-25 | 2012-11-28 | 株式会社Ｓｕｍｃｏ | 半導体基板の製造方法 |
| JP5143477B2 (ja) * | 2007-05-31 | 2013-02-13 | 信越化学工業株式会社 | Ｓｏｉウエーハの製造方法 |
| JP2010098167A (ja) * | 2008-10-17 | 2010-04-30 | Shin Etsu Handotai Co Ltd | 貼り合わせウェーハの製造方法 |
| WO2010062852A1 (en) * | 2008-11-26 | 2010-06-03 | Memc Electronic Materials, Inc. | Method for processing a silicon-on-insulator structure |
| JP5310004B2 (ja) * | 2009-01-07 | 2013-10-09 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
| US8080464B2 (en) * | 2009-12-29 | 2011-12-20 | MEMC Electronics Materials, Inc, | Methods for processing silicon on insulator wafers |
| JP5541136B2 (ja) * | 2010-12-15 | 2014-07-09 | 信越半導体株式会社 | 貼り合わせｓｏｉウエーハの製造方法 |
-
2014
- 2014-03-13 US US14/209,083 patent/US9202711B2/en active Active
- 2014-03-14 WO PCT/US2014/027418 patent/WO2014152510A1/en not_active Ceased
- 2014-03-14 KR KR1020157029121A patent/KR102027205B1/ko active Active
- 2014-03-14 TW TW103109754A patent/TWI598961B/zh active
- 2014-03-14 DE DE112014001279.3T patent/DE112014001279B4/de active Active
- 2014-03-14 CN CN201480026992.3A patent/CN105431936B/zh active Active
- 2014-03-14 JP JP2016502429A patent/JP6373354B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US9202711B2 (en) | 2015-12-01 |
| WO2014152510A1 (en) | 2014-09-25 |
| US20140273405A1 (en) | 2014-09-18 |
| DE112014001279B4 (de) | 2019-01-24 |
| KR20150132383A (ko) | 2015-11-25 |
| CN105431936A (zh) | 2016-03-23 |
| JP2016516304A (ja) | 2016-06-02 |
| KR102027205B1 (ko) | 2019-10-01 |
| DE112014001279T5 (de) | 2015-11-26 |
| JP6373354B2 (ja) | 2018-08-15 |
| TW201448046A (zh) | 2014-12-16 |
| CN105431936B (zh) | 2018-07-13 |
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