DE112012001089B4 - Herstellverfahren mit Erhalten von Vorteilen einer Verspannung beim UV-Härten bei der Fertigung von Ersatz-Gate-FET-Transistoren - Google Patents

Herstellverfahren mit Erhalten von Vorteilen einer Verspannung beim UV-Härten bei der Fertigung von Ersatz-Gate-FET-Transistoren Download PDF

Info

Publication number
DE112012001089B4
DE112012001089B4 DE112012001089.2T DE112012001089T DE112012001089B4 DE 112012001089 B4 DE112012001089 B4 DE 112012001089B4 DE 112012001089 T DE112012001089 T DE 112012001089T DE 112012001089 B4 DE112012001089 B4 DE 112012001089B4
Authority
DE
Germany
Prior art keywords
layer
stress
trenches
nitride
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE112012001089.2T
Other languages
German (de)
English (en)
Other versions
DE112012001089T5 (de
Inventor
Chun-Chen Yeh
Dechao Guo
Ming Cai
Pranita Kulkarni
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE112012001089T5 publication Critical patent/DE112012001089T5/de
Application granted granted Critical
Publication of DE112012001089B4 publication Critical patent/DE112012001089B4/de
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/791Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/791Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/791Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/798Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/013Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01324Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T or inverted-T
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/017Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128Manufacturing their channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H10D84/0133Manufacturing common source or drain regions between multiple IGFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135Manufacturing their gate conductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167Manufacturing their channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172Manufacturing their gate conductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/601Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/013Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6536Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to radiation, e.g. visible light
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69Inorganic materials
    • H10P14/694Inorganic materials composed of nitrides
    • H10P14/6943Inorganic materials composed of nitrides containing silicon
    • H10P14/69433Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)
DE112012001089.2T 2011-05-09 2012-02-24 Herstellverfahren mit Erhalten von Vorteilen einer Verspannung beim UV-Härten bei der Fertigung von Ersatz-Gate-FET-Transistoren Expired - Fee Related DE112012001089B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/103,149 US8421132B2 (en) 2011-05-09 2011-05-09 Post-planarization UV curing of stress inducing layers in replacement gate transistor fabrication
US13/103,149 2011-05-09
PCT/IB2012/050847 WO2012153201A1 (en) 2011-05-09 2012-02-24 Preserving stress benefits of uv curing in replacement gate transistor fabrication

Publications (2)

Publication Number Publication Date
DE112012001089T5 DE112012001089T5 (de) 2014-06-26
DE112012001089B4 true DE112012001089B4 (de) 2016-01-28

Family

ID=47138851

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112012001089.2T Expired - Fee Related DE112012001089B4 (de) 2011-05-09 2012-02-24 Herstellverfahren mit Erhalten von Vorteilen einer Verspannung beim UV-Härten bei der Fertigung von Ersatz-Gate-FET-Transistoren

Country Status (6)

Country Link
US (1) US8421132B2 (https=)
JP (1) JP5657176B2 (https=)
CN (1) CN103620748B (https=)
DE (1) DE112012001089B4 (https=)
GB (1) GB2503848B (https=)
WO (1) WO2012153201A1 (https=)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8765561B2 (en) * 2011-06-06 2014-07-01 United Microelectronics Corp. Method for fabricating semiconductor device
US8658487B2 (en) * 2011-11-17 2014-02-25 United Microelectronics Corp. Semiconductor device and fabrication method thereof
US8803249B2 (en) * 2012-08-09 2014-08-12 Taiwan Semiconductor Manufacturing Co., Ltd. Profile pre-shaping for replacement poly gate interlayer dielectric
US9293466B2 (en) 2013-06-19 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded SRAM and methods of forming the same
US9520474B2 (en) * 2013-09-12 2016-12-13 Taiwan Semiconductor Manufacturing Company Limited Methods of forming a semiconductor device with a gate stack having tapered sidewalls
CN104637797A (zh) * 2013-11-12 2015-05-20 中国科学院微电子研究所 一种后栅工艺中ild层的处理方法
CN104681597A (zh) * 2013-11-28 2015-06-03 中国科学院微电子研究所 半导体器件及其制造方法
US9312174B2 (en) * 2013-12-17 2016-04-12 United Microelectronics Corp. Method for manufacturing contact plugs for semiconductor devices
CN105225949B (zh) * 2014-05-26 2018-08-21 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法和电子装置
US10068982B2 (en) * 2014-05-29 2018-09-04 Taiwan Semiconductor Manufacturing Co., Ltd Structure and formation method of semiconductor device structure with metal gate
CN105336588B (zh) * 2014-05-29 2019-01-22 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
US10164049B2 (en) 2014-10-06 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method of semiconductor device with gate stack
KR102224386B1 (ko) * 2014-12-18 2021-03-08 삼성전자주식회사 집적 회로 장치의 제조 방법
KR101785803B1 (ko) 2015-05-29 2017-10-16 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 반도체 디바이스 구조체의 형성 방법
US9553090B2 (en) 2015-05-29 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method of semiconductor device structure
CN107170684B (zh) * 2016-03-08 2020-05-08 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法
US10147649B2 (en) 2016-05-27 2018-12-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with gate stack and method for forming the same
US10020401B2 (en) 2016-11-29 2018-07-10 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for straining a transistor gate through interlayer dielectric (ILD) doping schemes
US9786754B1 (en) * 2017-02-06 2017-10-10 Vanguard International Semiconductor Corporation Method for forming semiconductor device structure
CN109585293B (zh) * 2017-09-29 2021-12-24 台湾积体电路制造股份有限公司 切割金属工艺中的基脚去除
JP7837860B2 (ja) * 2019-08-09 2026-03-31 ヒタチ・エナジー・リミテッド 歪み強化型SiCパワー半導体デバイスおよび製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080305600A1 (en) * 2007-06-05 2008-12-11 Hsiu-Lien Liao Method and apparatus for fabricating high tensile stress film
DE102009039521A1 (de) * 2009-08-31 2011-03-10 Globalfoundries Dresden Module One Llc & Co. Kg Verbesserte Füllbedingungen in einem Austauschgateverfahren unter Anwendung einer zugverspannten Deckschicht

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6033963A (en) 1999-08-30 2000-03-07 Taiwan Semiconductor Manufacturing Company Method of forming a metal gate for CMOS devices using a replacement gate process
US6465309B1 (en) 2000-12-12 2002-10-15 Advanced Micro Devices, Inc. Silicide gate transistors
KR20030075745A (ko) 2002-03-20 2003-09-26 삼성전자주식회사 반도체 소자의 금속게이트 형성방법
JP2008518476A (ja) * 2004-10-29 2008-05-29 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 異なるように歪ませた歪みチャネル領域を有する半導体領域を含む、半導体デバイスおよびその製造方法
JP5091397B2 (ja) 2005-10-27 2012-12-05 パナソニック株式会社 半導体装置
US7510943B2 (en) * 2005-12-16 2009-03-31 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
US7678630B2 (en) * 2006-02-15 2010-03-16 Infineon Technologies Ag Strained semiconductor device and method of making same
JP2007324391A (ja) * 2006-06-01 2007-12-13 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US20070281405A1 (en) 2006-06-02 2007-12-06 International Business Machines Corporation Methods of stressing transistor channel with replaced gate and related structures
US7601574B2 (en) 2006-10-25 2009-10-13 Globalfoundries Inc. Methods for fabricating a stress enhanced MOS transistor
WO2008096587A1 (ja) 2007-02-07 2008-08-14 Nec Corporation 半導体装置
JP5003515B2 (ja) 2007-03-20 2012-08-15 ソニー株式会社 半導体装置
US7842592B2 (en) 2007-06-08 2010-11-30 International Business Machines Corporation Channel strain engineering in field-effect-transistor
JP2008306132A (ja) * 2007-06-11 2008-12-18 Renesas Technology Corp 半導体装置の製造方法
US7911001B2 (en) * 2007-07-15 2011-03-22 Samsung Electronics Co., Ltd. Methods for forming self-aligned dual stress liners for CMOS semiconductor devices
US20090035928A1 (en) * 2007-07-30 2009-02-05 Hegde Rama I Method of processing a high-k dielectric for cet scaling
DE102007046849B4 (de) 2007-09-29 2014-11-06 Advanced Micro Devices, Inc. Verfahren zur Herstellung von Gateelektrodenstrukturen mit großem ε nach der Transistorherstellung
US20090179308A1 (en) 2008-01-14 2009-07-16 Chris Stapelmann Method of Manufacturing a Semiconductor Device
JP5309619B2 (ja) * 2008-03-07 2013-10-09 ソニー株式会社 半導体装置およびその製造方法
JP5147471B2 (ja) * 2008-03-13 2013-02-20 パナソニック株式会社 半導体装置
JP2009277908A (ja) 2008-05-15 2009-11-26 Toshiba Corp 半導体装置の製造方法及び半導体装置
CN101866859B (zh) 2010-07-07 2012-07-04 北京大学 一种沟道应力引入方法及采用该方法制备的场效应晶体管
US8293605B2 (en) * 2011-02-25 2012-10-23 GlobalFoundries, Inc. Methods for fabricating a CMOS integrated circuit having a dual stress layer (DSL)

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080305600A1 (en) * 2007-06-05 2008-12-11 Hsiu-Lien Liao Method and apparatus for fabricating high tensile stress film
DE102009039521A1 (de) * 2009-08-31 2011-03-10 Globalfoundries Dresden Module One Llc & Co. Kg Verbesserte Füllbedingungen in einem Austauschgateverfahren unter Anwendung einer zugverspannten Deckschicht

Also Published As

Publication number Publication date
GB2503848B (en) 2015-07-29
US20120286375A1 (en) 2012-11-15
DE112012001089T5 (de) 2014-06-26
JP2014519192A (ja) 2014-08-07
JP5657176B2 (ja) 2015-01-21
GB2503848A (en) 2014-01-08
WO2012153201A1 (en) 2012-11-15
CN103620748B (zh) 2016-06-22
CN103620748A (zh) 2014-03-05
GB201318709D0 (en) 2013-12-04
US8421132B2 (en) 2013-04-16

Similar Documents

Publication Publication Date Title
DE112012001089B4 (de) Herstellverfahren mit Erhalten von Vorteilen einer Verspannung beim UV-Härten bei der Fertigung von Ersatz-Gate-FET-Transistoren
DE102008064928B4 (de) Halbleitereinrichtung
DE102015120488B4 (de) Verfahren zur Herstellung von zugverspannten Silizium-Rippen und druckverspannten Silizium-Germanium-Rippen für CMOS FinFET-Bauelemente
DE102005052054B4 (de) Halbleiterbauteil mit Transistoren mit verformten Kanalgebieten und Verfahren zu seiner Herstellung
DE60036410T2 (de) Methoden zur herstellung einer feldeffekttransistor-struktur mit teilweise isolierten source/drain-übergängen
DE102010030768B4 (de) Herstellverfahren für ein Halbleiterbauelement als Transistor mit eingebettetem Si/Ge-Material mit geringerem Abstand und besserer Gleichmäßigkeit und Transistor
DE102014109807B4 (de) Kanal-Verspannungssteuerung für nichtplanare Verbindungshalbleitervorrichtungen
DE102008035812B4 (de) Flacher pn-Übergang, der durch in-situ-Dotierung während des selektiven Aufwachsens einer eingebetteten Halbleiterlegierung mittels eines zyklischen Aufwachs-Ätz-Abscheideprozesses gebildet wird
DE112004002307T5 (de) Transistor mit Silizium- und Kohlenstoffschicht in dem Kanalbereich
DE102012205662B4 (de) MOS-Halbleitervorrichtung und Verfahren zu deren Herstellung
DE102013200543A1 (de) Verfahren zum Bilden von Austausch-Gate-Strukturen für Halbleitervorrichtungen
DE102006019937A1 (de) SOI-Transistor mit eingebetteter Verformungsschicht und einem reduzierten Effekt des potentialfreien Körpers und ein Verfahren zur Herstellung des Transistors
DE102008030852A1 (de) Kontaktgräben zur besseren Verspannungsübertragung in Transistoren mit geringem Abstand
DE112010000721T5 (de) Verfahren zur Herstellung von MOS-Bauelementen mit epitaktisch aufgewachsenen verspannungsinduzierenden Source- und Draingebieten
DE102007052053B4 (de) Eine Zugverformungsquelle unter Anwendung von Silizium/Germanium-Material in global verformtem Silizium
DE112006001979T5 (de) Verfahren zur Herstellung eines verformten MOS-Bauelements
DE102009039521A1 (de) Verbesserte Füllbedingungen in einem Austauschgateverfahren unter Anwendung einer zugverspannten Deckschicht
DE112011100975B4 (de) Verfahren zur Herstellung biaxial verspannter Feldeffekttransistor-Bauelemente
DE102008063432B4 (de) Verfahren zum Einstellen der Verformung, die in einem Transistorkanal eines FET hervorgerufen wird, durch für die Schwellwerteinstellung vorgesehenes Halbleitermaterial
DE102013100904B4 (de) Gestreckte Struktur einer Halbleitervorrichtung und Verfahren zur Herstellung der gestreckten Struktur
DE102007004862A1 (de) Verfahren zur Herstellung von Si-Ge enthaltenden Drain/Source-Gebieten in Transistoren mit geringerem Si/Ge-Verlust
DE102008044983B4 (de) Verfahren zum Herstellen eines strukturierten verformten Substrats, insbesondere zur Herstellung verformter Transistoren mit geringerer Dicke der aktiven Schicht
DE102010064284A1 (de) Transistor mit einer eingebetteten Sigma-förmigen Halbleiterlegierung mit erhöhter Gleichmäßigkeit
DE102009021480B4 (de) Reduzierte Siliziumdicke in n-Kanaltransistoren in SOI-CMOS Bauelementen
DE102006030264B4 (de) Verfahren zur Herstellung von Transistoren mit einem Kanal mit biaxialer Verformung, die durch Silizium/Germanium in der Gateelektrode hervorgerufen wird

Legal Events

Date Code Title Description
R012 Request for examination validly filed
R016 Response to examination communication
R016 Response to examination communication
R018 Grant decision by examination section/examining division
R084 Declaration of willingness to licence
R020 Patent grant now final
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee