CN103620748A - 保留替代栅极晶体管制造中的uv固化的应力益处 - Google Patents

保留替代栅极晶体管制造中的uv固化的应力益处 Download PDF

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CN103620748A
CN103620748A CN201280022389.9A CN201280022389A CN103620748A CN 103620748 A CN103620748 A CN 103620748A CN 201280022389 A CN201280022389 A CN 201280022389A CN 103620748 A CN103620748 A CN 103620748A
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layer
nitride
nitride layer
tensile
groove
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CN103620748B (zh
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叶俊呈
郭德超
蔡明�
P·库尔卡尼
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International Business Machines Corp
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Abstract

一种形成半导体结构的方法包括：在设置于衬底之上的一个或多个部分完成的场效应晶体管（FET）器件之上形成应力诱导层，所述一个或多个部分完成的FET器件包括牺牲伪栅极结构；对所述应力诱导层进行平面化并且去除所述牺牲伪栅极结构；以及在对所述应力诱导层进行平面化并且去除所述牺牲伪栅极结构之后，进行对所述应力诱导层的紫外（UV）固化，以增强由所述应力诱导层最初施加在所述一个或多个部分完成的FET器件的沟道区上的应力的值。

Description

保留替代栅极晶体管制造中的UV固化的应力益处
技术领域
本发明总体上涉及半导体器件制造，更具体地，涉及用于保留替代栅极晶体管制造中的紫外（UV）固化的拉伸应力益处的方法和结构。
背景技术
场效应晶体管（FET）广泛用在用于与模拟和数字电信号二者相关的开关、放大、过滤及其它任务的电子工业中。这些场效应晶体管中最常见的是金属氧化物半导体场效应晶体管（MOSFET或MOS），其中栅极结构被加电以在下面的半导体本体的沟道区中产生电场，由此允许电子行经该半导体本体的源极区和漏极区之间的沟道。互补MOS（CMOS）器件已经变得在半导体工业中广泛应用，其中n型和p型（NFET和PFET）FET二者都用于制造逻辑和其它电路。
典型地通过向沟道两侧的半导体本体的目标区域添加掺杂剂，形成FET的源极区和漏极区。栅极结构形成在沟道上方，其包括位于沟道之上的栅极电介质以及位于栅极电介质上方的栅极导体。栅极电介质是绝缘体材料，其在电压被施加到栅极导体时防止大的泄漏电流流入沟道，同时允许所施加的栅极电压以可控的方式在沟道区内建立横向电场。常规的MOS晶体管典型地包括通过在硅晶片表面之上沉积或者生长二氧化硅（SiO2）或氧氮化硅而形成的栅极电介质，其中掺杂的多晶硅形成在SiO2之上以用作栅极导体。
半导体器件制造中不断的趋势包括电器件特征尺寸的减小（即，按比例缩小），以及在器件开关速度和功耗方面器件性能的提高。可以通过减小器件的栅极导体下方的源极区与漏极区之间的距离（称为栅极或沟道长度），以及通过减小形成在半导体表面之上的栅极电介质层的厚度，来提高MOS晶体管性能。然而，SiO2栅极电介质的厚度能够减小的程度有着电学和物理极限。例如，薄的SiO2栅极电介质容易发生由于电子直接隧穿通过薄栅极电介质而导致的栅极隧穿泄漏电流。
因此，近来按比例缩小MOS和CMOS晶体管的努力已经关注于介电常数大于SiO2的介电常数（例如，大于约3.9）的高k电介质材料。与按比例缩小的SiO2相比，高k电介质材料可以以较厚的层形成，而仍产生等效的场效应性能。这种高k电介质材料的相关电性能经常以等效氧化物厚度（EOT）表达，这是因为高k材料层可以较厚，同时仍提供与薄得多的SiO2层等效的电效应。由于介电常数“k”高于二氧化硅，可以利用较厚的高k电介质层来减小隧穿泄漏电流，同时仍实现与较薄的热生长SiO2层等效的电学性能。
发明内容
在一个方面，一种形成半导体结构的方法包括：在设置于衬底之上的一个或多个部分完成的场效应晶体管（FET）器件之上形成应力诱导层，所述一个或多个部分完成的FET器件包括牺牲伪栅极结构；对所述应力诱导层进行平面化并且去除所述牺牲伪栅极结构；以及在对所述应力诱导层进行平面化并且去除所述牺牲伪栅极结构之后，进行对所述应力诱导层的紫外（UV）固化，以增强由所述应力诱导层最初施加在所述一个或多个部分完成的FET器件的沟道区上的应力的值。
在另一个方面，一种形成半导体结构的方法包括：在设置于衬底之上的一个或多个部分完成的n型场效应晶体管（NFET）器件之上形成拉伸氮化物层，所述一个或多个部分完成的NFET器件包括多晶硅牺牲伪栅极结构；对所述拉伸氮化物层进行平面化并且去除所述多晶硅牺牲伪栅极结构；用一个或多个金属栅极层填充通过去除所述多晶硅牺牲伪栅极结构而界定（define）的沟槽；对所述一个或多个金属栅极层进行平面化；以及进行对所述拉伸氮化物层的紫外（UV）固化，以增强由所述拉伸氮化物层最初施加在所述一个或多个部分完成的NFET器件的沟道区上的应力的值。
在又一个方面，一种形成半导体结构的方法包括：在设置于衬底之上的一个或多个部分完成的n型场效应晶体管（NFET）器件之上形成拉伸氮化物层，所述一个或多个部分完成的NFET器件包括多晶硅牺牲伪栅极结构；对所述拉伸氮化物层进行平面化并且去除所述多晶硅牺牲伪栅极结构；以及进行对所述拉伸氮化物层的紫外（UV）固化，以增强由所述拉伸氮化物层最初施加在所述一个或多个部分完成的NFET器件的沟道区上的应力的值；在所述UV固化之后，用一个或多个金属栅极层填充通过去除所述多晶硅牺牲伪栅极结构而界定的沟槽；以及对所述一个或多个金属栅极层进行平面化。
在再一个方面，一种半导体结构包括：设置于衬底之上的多个n型场效应晶体管（NFET）器件；形成在所述衬底之上并且位于所述NFET器件的栅极结构之间的紫外（UV）固化的拉伸氮化物层，其中部分所述UV固化的拉伸氮化物层具有梯形轮廓，该梯形轮廓的底端宽于该梯形轮廓的顶端；以及所述NFET器件的所述栅极结构，其也具有梯形轮廓，该梯形轮廓的顶端宽于该梯形轮廓的底端。
附图说明
参考示例性附图，其中在若干个图中相似的部件标以相似的附图标记：
图1至5是示例出用于替代金属栅极晶体管形成的工艺流程的横截面视图，该替代金属栅极晶体管形成包括对应力层的紫外（UV）固化，其中：
图1示例出在多个部分完成的NFET器件之上氮化硅应力层的形成；
图2示例出对图1的应力层的UV固化，由此增加了由应力层施加的拉伸应力；
图3示例出对图2的应力层的平面化以及NFET器件的伪栅极结构的去除，这减小了由应力层施加的拉伸应力；
图4示例出在由图3中伪栅极去除得到的沟槽内金属栅极材料的形成；
图5示例出图4的金属栅极材料的平面化；
图6至10是示例出根据示例性实施例用于替代金属栅极晶体管形成的工艺流程的横截面视图，该替代金属栅极晶体管形成包括对应力层的UV固化，其中：
图6示例出在多个部分完成的NFET器件之上氮化硅应力层的形成；
图7示例出对图6的应力层的平面化以及NFET器件的伪栅极结构的去除；
图8示例出在由图7中伪栅极去除得到的沟槽内金属栅极材料的形成；
图9示例出对图8的金属栅极材料的平面化；
图10示例出对图9的应力层的UV固化，由此增加了由应力层施加的拉伸应力；
图11至15是示例出根据另一示例性实施例的用于替代金属栅极晶体管形成的工艺流程的横截面视图，该替代金属栅极晶体管形成包括对应力层的UV固化，其中：
图11示例出在多个部分完成的NFET器件之上氮化硅应力层的形成；
图12示例出图11的应力层的平面化以及NFET器件的伪栅极结构的去除；
图13示例出在金属栅极填充之前对图12的应力层的UV固化，由此增加了由应力层施加的拉伸应力；
图14示例出在图13中的结构的沟槽内金属栅极材料的形成；以及
图15示例出对图14的金属栅极材料的平面化。
具体实施方式
就高k金属栅极（HKMG）技术而言，用于将金属栅引入标准CMOS工艺流程的两种主要方法是“先栅极（gate first）”工艺或“后栅极（gatelast）”工艺。后者也称为“替代栅极”或者替代金属栅极（RMG）工艺。在先栅极工艺中，在多晶硅栅极沉积之前完成高k电介质和金属工艺。在形成源极和漏极之前与多晶硅栅极材料一起减式蚀刻金属栅极材料。
另一方面，RMG工艺架构避免了在先栅极架构中遇到的功函数材料稳定性的问题。此处，伪栅极结构被用于自对准源极和漏极注入和退火，之后剥掉伪栅极材料并且用高k和金属栅极材料替代伪栅极材料。尽管该工艺比先栅极技术更复杂，但是替代栅极流程的优点包括使用分开的PMOS和NMOS金属，来进行功函数的最优化。此外，这两种金属不暴露于高温，简化了材料选择。另外，多晶硅栅极的去除实际上可用于增强应变技术，由此增加驱动电流。由于前述功函数限制，RMG工艺目前是22纳米（nm）CMOS技术的前沿途径。
如现有技术中已知的，应力衬里（liner）（例如，对于PFET器件，压缩衬里；对于NFET器件，拉伸衬里）在FET之上的形成增强了晶体管沟道中多数载流子的迁移率。在NFET器件的情况下，示例性应力衬里材料是氮化硅（SiN），其在NFET沟道上提供了在约1.6吉帕斯卡（GPa）范围内的拉伸应力。可以与氮化硅拉伸衬里形成结合使用的一种技术是诸如由例如激光产生的紫外（UV）固化的应用。对受到拉伸应力的氮化物膜的UV固化可以通过重新构造存在于该氮化物膜中的硅-氢（Si-H）/氮-氢（N-H）键来增强该氮化物膜中的拉伸应力。通过将氮化物暴露于UV辐射进行对氮化物的UV固化，所述UV辐射具有在约10纳米（nm）到约400nm的范围内的波长。氮化物膜中增强的应力在UV固化的氮化物膜位于其之上的FET沟道中诱导对应的增强的应力，这增加了FET沟道中的载流子迁移率。
典型地，氮化物层沉积和UV固化工艺组合在一起，使得氮化物层在其被平面化之前被固化。然而，在RMG工艺流程的情况下，UV固化所提供的附加益处可能由于与RMG技术相关联的化学机械抛光（CMP）和伪栅极去除工艺而被减少或中和。沿着沟道方向的单轴应力弛豫使由UV固化带来的益处无效。通过示例的方式，图1至5是示例出用于替代金属栅极晶体管形成的工艺流程的横截面视图，该替代金属栅极晶体管形成包括对应力层的紫外（UV）固化。
如图1所示，半导体结构100包括其中形成有浅沟槽隔离（STI）结构104的半导体衬底102。半导体衬底102包括半导体材料，该半导体材料可以选自但不限于硅、锗、硅锗合金、硅碳合金、硅锗碳合金、砷化镓、砷化铟、磷化铟、III-V化合物半导体材料、II-VI化合物半导体材料、有机半导体材料以及其它化合物半导体材料。当半导体衬底102的半导体材料是包含单晶硅的半导体材料时，该包含单晶硅的半导体材料可以选自单晶硅、单晶硅碳合金、单晶硅锗合金、以及单晶硅锗碳合金。
在CMOS器件中，半导体衬底102的半导体材料可以适当地掺有p型掺杂剂原子或掺有n型掺杂剂原子。在所示出的具体例子中，在STI结构104之间示出的部分完成的晶体管器件是NFET器件106，因此半导体102是用p型原子掺杂的。半导体衬底102的掺杂剂浓度的范围可以为约1.0x1015原子/cm3到约1.0x1019原子/cm3，更具体地为约1.0x1016原子/cm3到约3.0x1018原子/cm3，但本申请中也预期更小或更大的掺杂剂浓度。此外，半导体衬底102可以是体衬底、绝缘体上半导体或者绝缘体上硅（SOI）衬底或混合衬底。浅沟槽隔离结构104包括诸如氧化硅或氮化硅的电介质材料，并且可以通过本领域中公知的方法形成。
也如图1中所示，半导体结构100是替代栅极FET技术的一个例子。因此，该器件包括通过离子注入形成的源极延伸区和漏极延伸区108，其中伪栅极结构位于适当位置。伪栅极结构可以包括形成在栅极电介质层112上的牺牲多晶硅材料110。在一些实施例中，栅极电介质层112也可以是牺牲栅极电介质层并且因此形成伪栅极结构的一部分。或者，栅极电介质材料层112可以是永久栅极电介质层并且包括诸如氧化铪（HfO2）的高k材料，例如具有SiO2界面层。
源极延伸区和漏极延伸区108具有与衬底102的掺杂相反导电类型的掺杂。因此，在所示的NFET例子中，由于衬底102具有p型掺杂，因此源极延伸区和漏极延伸区108具有n型掺杂。也在图1中描绘了源极和漏极区114，它们是例如通过与延伸区106相同导电类型的离子注入形成的。在伪栅极结构和侧壁间隔物116处于适当位置的情况下注入源极和漏极区114。例如，通过沉积保形的（conformal）电介质材料层（例如，以及诸如氮化硅的不透氧材料）并且之后进行各向异性离子蚀刻，形成侧壁间隔物116。直接在伪栅极结构的侧壁上形成的电介质材料层的部分在各向异性蚀刻之后保留以构成侧壁间隔物116。也在牺牲多晶硅110的顶上示例出保护硬掩膜118，其为与侧壁间隔物116相同或不同的材料。
图1中还示出，诸如例如SiN的拉伸氮化物层120形成在整个结构100之上。例如，可通过物理气相沉积（PVD）、化学气相沉积（CVD）、等离子体增强的CVD（PECVD）、高密度等离子体CVD（HDPCVD）和旋涂技术形成所述拉伸氮化物层120。在最初沉积时，氮化物层120可以提供约0.7吉帕斯卡（GPa）量级的拉伸应力。然后，如图2所示，使用如由曲线箭头所指示的UV辐射固化氮化物层120，以增强其应力特性，其中增强的应力氮化物层用120'表示。借助于UV固化而增强的应力氮化物层120'可以提供约1.6GPa量级的增强的拉伸应力。
然后如图3所示，例如通过CMP平面化该增强的应力氮化物层120'，之后至少去除伪栅极结构的牺牲多晶硅110，以形成沟槽122。注意，现在在图3中再次用附图标记120表示氮化物层，这反映了由于固化之后的应力层的平面化导致的所得到的应力减小（例如，减小到约1.1Gpa或更低）。根据RMG处理，在器件之上形成一个或多个金属栅极层（一般由124示出），如图4所示。例如，对于NFET器件，金属栅极层124可以包括被选择为将功函数设定在硅导带边缘周围的功函数设定金属层，该功函数设定金属层诸如例如是：氮化钛、氮化钽、钛铝、氮化钛铝、钽铝、氮化钽铝、铪硅合金、氮化铪或碳化钽。同样，在栅极电介质层112是牺牲层的情况下，新的栅极电介质层（例如，高k）将在沉积金属栅极层124之前形成，之后进行600℃的退火用于高k电介质的致密化。
然后，如图5中所示，对金属栅极层124进行平面化，其后可以如现有技术中所示地继续CMOS器件处理。然而，应当理解，由于上述RMG工艺流程，氮化物层120的UV固化的益处可被有效中和。
因此，此处公开的是用于在替代栅极晶体管制造中保留紫外（UV）固化的应力益处的方法和结构。通过将氮化物沉积和UV固化工艺分开使得固化在氮化物层沉积和伪栅去除之后进行，可以完全保留UV固化的应力益处。在下文所述的一个具体实施例中，与UV工艺导致的膜收缩相关联的氮化物形态改变，相比于均匀的栅金属沉积，提供了额外的益处。随着栅极长度进一步按比例缩小，间隙填充变得越来越有挑战，该实施例提供了减轻这一问题的方案。
现在总体参考图6至10，示出了一系列横截面视图，其示例出根据示例性实施例的用于替代金属栅极晶体管形成的工艺流程，该替代金属栅极晶体管形成包括对应力层的UV固化。图6示例出与图1的处理点基本类似的处理点，其中诸如例如SiN的拉伸氮化物层120形成在具有伪栅极结构的部分形成的NFET器件106的整个结构100之上。然而，不是在此工艺点进行对氮化物层120的UV固化，而是替代地例如通过CMP来平面化氮化物层120，之后至少去除伪栅极结构的牺牲多晶硅110，如图7所示。
然后，如图8所示，在包括通过牺牲多晶硅去除而留下的沟槽112的器件100之上形成一个或多个金属栅极层（一般由124图示）。同样，在此点，尚未对氮化物层120进行UV固化。在图9中，金属栅极层124被平面化，由此界定RMG形成的NFET器件106。在金属栅极结构位于适当位置的情况下，然后对氮化物层120进行UV固化，如图10中所示。UV固化导致氮化物层的所施加的应力增强，该氮化物层现在在图10中用120'图示。同样，由于UV固化，由增强的氮化物层120'施加的单轴拉伸应力从约0.7GPa增加到约1.6GPa。此外，由于增强的氮化物层120'已经被平面化，因此器件100准备好用于进一步的CMOS处理步骤，所述进一步的CMOS处理步骤不影响增强的氮化物层120'的所施加的应力的完整性或有效性。
现在总体参考图11-15，示出了一系列横截面视图，其示例出根据示例性实施例的用于替代金属栅极晶体管形成的工艺流程，该替代金属栅极晶体管形成包括对应力层的UV固化。图6示例出与图1的处理点基本类似的处理点，其中诸如例如SiN的拉伸氮化物层120形成在具有伪栅极结构的部分形成的NFET器件106的整个结构100之上。图11示例出与图1的处理点基本类似的处理点，其中诸如例如SiN的拉伸氮化物层120形成在具有伪栅极结构的部分形成的NFET器件106的整个结构100之上。与之前描述的实施例的情况一样，不是在此工艺点进行对氮化物层120的UV固化，而是替代地例如通过CMP来平面化氮化物层120，之后至少去除伪栅极结构的牺牲多晶硅110，如图12所示。
然而，与图6-10的实施例形成对比，在该实施例中，在沟槽122的金属填充之前对氮化物层120进行UV固化，这在图13中反映。此处，注意除了增加增强的氮化物层120'的所施加的应力之外，UV固化也导致增强的氮化物层120'的体积收缩（例如约10%），这是因为膜变得更致密。特别地，在牺牲多晶硅去除之后且在替代栅金属沉积之前进行的UV固化导致增强的氮化物层120'以及所得到的经修改的沟槽122'轮廓的梯形轮廓。增强的氮化物层120'的梯形轮廓在基部较宽并且在顶部较窄，而经修改的沟槽122'的梯形轮廓在底端较窄并且在顶端较宽。
这种轮廓对于随后的金属栅极填充工艺而言是有利的，如图14所示。这里，在器件100（包括通过牺牲多晶硅去除和UV固化而界定的经修改的沟槽122'）之上形成一个或多个金属栅极层124。与基本垂直的沟槽轮廓或者在顶部较窄的沟槽轮廓相对照，其中氮化物层的体积收缩引起沟槽的顶部加宽的梯形沟槽轮廓通过避免了在金属栅极结构内的空隙形成以及层夹断（pinch-off），促进了经修改的沟槽122'内的更好的金属填充覆盖。最后，如图15所示，对金属栅极层124进行平面化，由此界定RMG形成的NFET器件106。
由此将理解，通过不与氮化物衬里的沉积同时进行UV固化也不在氮化物衬里的沉积之后立即进行UV固化，而是替代地首先至少进行氮化物层CMP和伪栅极去除，可以贯穿器件处理的剩余部分保持由UV固化提供的增强的应力益处。此外，通过在平面化/伪栅极去除之后并且在金属栅极填充之前进行UV固化，所得到的氮化物层和沟槽的体积收缩和梯形轮廓导致更好的金属填充条件。
尽管已经参考一个或多个优选实施例描述了本发明，但是本领域技术人员将理解，在不脱离本发明的范围的情况下，可以进行各种变换并且等效物可以用于替代其要素。此外，在不脱离本发明的实质范围的情况下，可以进行很多修改以使特定情况或材料适应本发明的教导。因此，本发明旨在不限于作为为了执行本发明而预期的最佳模式被公开的特定实施例，而是本发明将包括落入所附权利要求的范围内的所有实施例。

Claims (21)

1.一种形成半导体结构的方法，所述方法包括：
在设置于衬底之上的一个或多个部分完成的场效应晶体管（FET）器件之上形成应力诱导层，所述一个或多个部分完成的FET器件包括牺牲伪栅极结构；
对所述应力诱导层进行平面化并且去除所述牺牲伪栅极结构；以及
在对所述应力诱导层进行平面化并且去除所述牺牲伪栅极结构之后，进行对所述应力诱导层的紫外（UV）固化，以增强由所述应力诱导层最初施加在所述一个或多个部分完成的FET器件的沟道区上的应力的值。
2.权利要求1所述的方法，其中，所述应力诱导层包括拉伸氮化物层，并且所述一个或多个部分完成的FET器件包括n型FET（NFET）器件。
3.权利要求2所述的方法，还包括：用一个或多个金属栅极层填充通过去除所述牺牲伪栅极结构而界定的沟槽。
4.权利要求3所述的方法，还包括：对所述一个或多个金属栅极层进行平面化。
5.权利要求3所述的方法，其中，在填充所述沟槽并且对所述一个或多个金属栅极层进行平面化之后进行所述UV固化。
6.权利要求3所述的方法，其中，在用所述一个或多个金属栅极层填充所述沟槽之前进行所述UV固化，以使得所述应力诱导层和所述沟槽呈现梯形轮廓。
7.权利要求6所述的方法，其中，所述沟槽的所述梯形轮廓使得所述沟槽在其底端较窄并且在其顶端较宽。
8.权利要求3所述的方法，还包括：
在用所述一个或多个金属栅极层填充之前在所述沟槽中形成替代的高介电常数（高k）层。
9.权利要求1所述的方法，其中，所述应力诱导层是拉伸氮化物层，所述FET器件是n型场效应晶体管（NFET）器件，并且所述伪栅极结构是多晶硅牺牲伪栅极结构；
并且其中，所述方法还包括，在对所述拉伸氮化物层进行平面化并且去除所述伪栅极结构之后：
用一个或多个金属栅极层填充通过去除所述多晶硅牺牲伪栅极结构而界定的沟槽；以及
对所述一个或多个金属栅极层进行平面化。
10.权利要求9所述的方法，其中，所述拉伸氮化物层包括氮化硅层。
11.权利要求10所述的方法，其中，由所述拉伸氮化物层最初施加的应力在约0.7吉帕斯卡（GPa）的量级，并且增强的拉伸应力值在约1.6GPa的量级。
12.权利要求9所述的方法，其中，所述一个或多个金属栅极层包含氮化钛、氮化钽、钛铝、氮化钛铝、钽铝、氮化钽铝、铪硅合金、氮化铪以及碳化钽中的一种或多种。
13.权利要求9所述的方法，还包括：
在用所述一个或多个金属栅极层填充之前在所述沟槽中形成替代的高介电常数（高k）层，所述高k层包含具有SiO2界面层的氧化铪（HfO2）；以及
对所述高k层进行退火以使其致密化。
14.权利要求9所述的方法，其中在所述UV固化之后进行所述填充沟槽和对所述一个或多个金属栅极层的平面化。
15.权利要求14所述的方法，其中，所述UV固化导致所述拉伸氮化物层和所述沟槽呈现梯形轮廓。
16.权利要求15所述的方法，其中，所述沟槽的所述梯形轮廓使得所述沟槽在其底端较窄并且在其顶端较宽。
17.一种半导体结构，包括：
设置于衬底之上的多个n型场效应晶体管（NFET）器件；
形成在所述衬底之上并且位于所述NFET器件的栅极结构之间的紫外（UV）固化的拉伸氮化物层，其中部分所述UV固化的拉伸氮化物层具有梯形轮廓，该梯形轮廓的底端宽于该梯形轮廓的顶端；以及
所述NFET器件的所述栅极结构，其也具有梯形轮廓，该梯形轮廓的顶端宽于该梯形轮廓的底端。
18.权利要求17所述的结构，其中，所述拉伸氮化物层包括氮化硅层。
19.权利要求17所述的结构，其中，拉伸氮化物层提供约1.6吉帕斯卡（GPa）量级的拉伸应力。
20.权利要求17所述的结构，其中，所述栅极结构包括金属栅极结构。
21.权利要求20所述的结构，其中，所述金属栅极结构包含氮化钛、氮化钽、钛铝、氮化钛铝、钽铝、氮化钽铝、铪硅合金、氮化铪以及碳化钽中的一种或多种。
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DE112012001089B4 (de) 2016-01-28
US8421132B2 (en) 2013-04-16
GB201318709D0 (en) 2013-12-04
US20120286375A1 (en) 2012-11-15
GB2503848A (en) 2014-01-08
CN103620748B (zh) 2016-06-22
JP2014519192A (ja) 2014-08-07
WO2012153201A1 (en) 2012-11-15
GB2503848B (en) 2015-07-29

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