CN106328501A - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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CN106328501A
CN106328501A CN201510351481.5A CN201510351481A CN106328501A CN 106328501 A CN106328501 A CN 106328501A CN 201510351481 A CN201510351481 A CN 201510351481A CN 106328501 A CN106328501 A CN 106328501A
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layer
opening
manufacture method
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metallic
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CN106328501B (zh
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王桂磊
刘金彪
高建峰
李俊峰
赵超
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Institute of Microelectronics of CAS
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Abstract

本发明公开了一种半导体器件的制造方法，包括：提供半导体衬底，所述衬底上具有去除伪栅后形成的开口；在开口中填充顶层金属层，顶层金属层具有压应力；对PMOS器件区域的顶层金属层，进行非晶化注入。本发明有利于提高NMOS器件的载流子迁移率，并能减小PMOS器件区域的压应力，保证PMOS器件性能。

Description

半导体器件的制造方法
技术领域
本发明属于半导体制造领域，尤其涉及一种半导体器件的制造方法。
背景技术
目前，在先进的CMOS FET(互补金属氧化物半导体场效应晶体管)制造工艺的集成研究可大概分为两个方向，即前栅工艺和后栅工艺。
后栅工艺目前广泛应用于先进的集成电路工艺制造中，其通常是先形成伪栅和源漏区，而后去除伪栅并在栅沟槽中重新形成高k金属栅堆叠的替代栅极。由于栅极形成在源漏极之后，此工艺中栅极不需要承受很高的退火温度，对栅层材料选择更广泛并且更能体现材料本征的特性。
由于半导体器件尺寸不断缩小，对半导体器件的性能也提出了更高的要求，其中，应力工程是通过对NMOS和PMOS器件的沟道区域引入不同的应变力，从而改善沟道载流子的迁移率，进一步提高器件的性能。在后栅工艺中，通常需要填充金属材料到去除伪栅极的开口中作为顶层金属栅极，特别是在器件尺寸减小后，如何进一步改善器件沟道载流子迁移率的填充方法，是替代栅极填充需要解决的关键问题之一。
发明内容
本发明的目的在于克服现有技术中的不足，提供一种能引入器件所需应变力的器件的制造方法。
为实现上述目的，本发明的技术方案为：
一种半导体器件的制造方法，包括：
提供半导体衬底，所述衬底上具有去除伪栅后形成的开口；
在开口中填充顶层金属层，顶层金属层具有压应力；
对PMOS器件区域的顶层金属层，进行非晶化注入。
可选的，在开口中填充顶层金属层的步骤包括：
采用PVD工艺，在开口中填充金属氮化钨的顶层金属层，顶层金属层氮化钨具有压应力。
可选的，在开口中填充氮化钨的顶层金属层的步骤包括：
在PVD工艺中，以钨靶与氮气作为反应源，在开口中填充金属氮化钨的顶层金属层。
可选的，非晶化注入的粒子为Ge。
可选的，非晶化注入的工艺条件为：注入的能量为0.5-30keV，注入的剂量为5E14-5E16/cm2。
可选的，在开口中填充金属顶层金属层以及进行非晶化注入的步骤包括：
进行顶层金属的填充，顶层金属具有压应力；
进行平坦化工艺；
在NMOS器件区域上覆盖掩膜层；
进行非晶化注入；
去除掩膜层；
去除开口之外的顶层金属，以在开口内形成顶层金属层。
可选的，在开口中填充顶层金属层之前，还包括步骤：
在开口的内壁上形成高k栅介质层，并进行热退火。
可选的，热退火的温度为450℃，时间为15s。
可选的，在开口中填充顶层金属层之前，形成高k栅介质层之后还包括步骤：
在高k栅介质层上形成金属阻挡层；
在金属阻挡层上形成金属功函数层。
可选的，所述金属阻挡层为TiN或WN。
本发明实施例提供的半导体器件的制造方法，在后栅工艺中，对于填充的顶层金属层为具有压应力时，对PMOS器件区域的顶层金属层，进行非晶化注入，这样，仅通过一次顶层金属的填充，就可以在NMOS器件区域的顶层金属层为具有压应力，有利于提高NMOS器件的载流子迁移率，而PMOS器件区域由于进行了非晶化注入，有助于减小PMOS器件区域的压应力，从而，保证PMOS器件性能。
附图说明
为了更清楚地说明本发明实施的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了根据本发明实施例的半导体器件的制造方法的流程图；
图2-图9为根据本发明实施例制造半导体器件的各个制造过程中器件的剖面示意图，剖面为沿鳍方向。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是本发明还可以采用其他不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施例的限制。
其次，本发明结合示意图进行详细描述，在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
在本发明中，提供了一种半导体器件的制造方法，参考图图1所示，该方法包括：
步骤S01，提供半导体衬底，所述衬底上具有去除伪栅后形成的开口；
步骤S02，在开口中填充顶层金属，顶层金属具有压应力；
步骤S03，对PMOS器件区域的顶层金属，进行非晶化注入。
本发明的制造方法，应用于后栅工艺中，对于填充的顶层金属层为具有压应力时，对PMOS器件区域的顶层金属层，进行非晶化注入，这样，在NMOS器件区域的顶层金属层为具有压应力，有利于提高NMOS器件的载流子迁移率，而PMOS器件区域由于进行了非晶化注入，有助于减小PMOS器件区域的压应力，从而，保证PMOS器件性能。
在本发明中，该方法可以为应用于FinFET器件的后栅工艺中，也可以为应用于常规的平面器件的后栅工艺中。为了更好的理解本发明的技术方案和技术效果，以下将结合流程图图1对FinFET器件的制造方法的实施例进行详细的描述，该实施例的制造过程的示意图为沿鳍方向的剖面示意图。
首先，提供半导体衬底100，在半导体衬底上形成伪栅器件，参考图2所示。
在本发明实施例中，所述半导体衬底100可以为Si衬底、Ge衬底、SiGe衬底、SOI(绝缘体上硅，Silicon On Insulator)或GOI(绝缘体上锗，GermaniumOn Insulator)等，还可以为包括其他元素半导体或化合物半导体的衬底，例如GaAs、InP或SiC等，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
在本实施例中，所述半导体衬底100为体硅衬底，该衬底上具有PMOS器件区域1001和NMOS器件区域1002，以分别形成NMOS和PMOS器件。
在一个具体的实施例中，可以通过如下步骤提供伪栅器件。
首先，可以采用传统的方法进行阱掺杂，对于N型器件进行P型粒子的掺杂，对于P型器件，进行N型粒子的掺杂，在体硅的衬底100中形成阱区(图未示出)。
而后，采用刻蚀技术，例如RIE(反应离子刻蚀)的方法，刻蚀衬底100形成鳍102而后，进行二氧化硅的隔离材料的填充，并进行平坦化工艺，如进行化学机械平坦化，而后，可以使用湿法腐蚀，例如使用氢氟酸腐蚀去除一定厚度的二氧化硅的隔离材料，保留部分的隔离材料在鳍之间，从而形成了隔离(图未示出)。
而后，淀积伪栅介质层和伪栅极材料，并进行图案化，在鳍的表面上形成栅介质层104和伪栅极106，伪栅介质层可以为氧化硅，可以采用热氧化法形成，伪栅极材料可以为非晶硅、多晶硅等，本实施例中，伪栅极材料为非晶硅，而后，在伪栅极的侧壁形成侧墙108，侧墙可以为单层或多层结构，例如可以为氧化硅、氮氧化硅、氮化硅或他们的叠层。接着，在伪栅极两侧的鳍上形成源漏区，本实施例中，通过外延生长(EPI)同时进行掺杂，在鳍的两端形成源漏区110。而后，进行层间介质层的淀积，例如未掺杂的氧化硅(SiO2)、掺杂的氧化硅(如硼硅玻璃、硼磷硅玻璃等)、氮化硅(Si3N4)或其他低k介质材料，而后进行平坦化，例如CMP(化学机械抛光)，直至暴露伪栅极106，形成层间介质层109。至此，形成了后栅工艺中的伪栅器件。
接着，去除伪栅极，形成开口112，参考图3所示。
在本实施例中，可以采用湿法腐蚀去除伪栅极，在一个实施例中，可以通过一定配比浓度的四甲基氢氧化铵(TMAH)去除非晶硅的伪栅极106，并进一步去除伪栅介质层104，从而，形成开口112，进一步的，去除伪栅介质层后，可以重新形成所需的栅介质层，提高器件的界面特性，本实施例中，可以采用稀释的BOE去除伪栅介质层104，同时，在鳍的表面上形成一层界面氧化层114，如图3所示。
而后，重新淀积替代栅介质层116，如图4所示，替代栅介质层116可以为高k介质材料，(例如，和氧化硅相比，具有高介电常数的材料)或其他合适的介质材料，高k介质材料例如铪基氧化物，HFO2、HfSiO、HfSiON、HfTaO、HfTiO等，并进行PDA(Post Deposition Anneal)的热退火，退火温度可以为450℃，时间为15s。
接着，淀积金属栅极，金属栅极可以包括多层金属层，例如Ti、TiAlx、TiALC、TiN、TaNx、HfN、TiCx、TaCx、W等等，在本实施例中，金属栅极包括依次层叠的金属阻挡层和金属功函数层，对于NMOS器件和PMOS器件可以分别形成金属功函数层，以分别调节不同器件的功函数，提高器件的性能，具体的，首先，如图5所示，淀积金属阻挡层118，该金属阻挡层118可以为TiN或WN等，该金属阻挡层避免上层的金属扩散至栅介质层及沟道中，而后，如图6所示，分别在PMOS器件区域1001的金属阻挡层118上形成第一金属功函数层120，在NMOS器件区域1002的金属阻挡层118上形成第二金属功函数层122，第一金属功函数层120例如可以为Ti、TiN等，调节PMOS器件的有效功函数，第二金属功函数层122例如可以为TiAl、TiALC等，调节NMOS器件的有效功函数。
而后，参考图7所示，填充顶层金属层130，对于顶层金属层仅进行一次填充，在一些工艺中，填充后的顶层金属层具有压应力，例如利用PVD方法填充的AlN,TiN的金属层，或者利用PVD填充的WN的金属层等。
在本实施例中，采用PVD工艺，在开口中填充金属氮化钨的顶层金属层130，具体的，在该PVD工艺中，可以以高纯钨靶与氮气作为反应源，在开口中填充金属氮化钨的顶层金属层130，并进行平坦化，如图7所示，该方法形成的顶层金属层130具有较高的压应力。
在本实施例方法中，形成的氮化钨的顶层金属层在沟道垂直方向上具有压应力，该压应力有利于提高NMOS器件的载流子迁移率，而对于PMOS器件压应力却会带来性能退化的影响，对于PMOS器件不希望压应力的存在。
而后，对PMOS器件区域1001的顶层金属层130，进行非晶化注入。
具体的，首先，在NMOS器件区域1002上覆盖掩膜层134，如图8所示，掩膜层134可以为硬掩膜或光罩层，而后，对PMOS器件区域1001的顶层金属层130进行非晶化注入，非晶化注入的粒子可以为Ge、N、F等，非晶化注入并不改变PMOS器件区域1001的顶层金属层130的电学性能，仅改变其内部晶体的结构分布，从而释放PMOS器件区域1001的顶层金属层130的压应力，降低顶层金属层对PMOS器件的沟道影响较小。
在本实施例中，优选非晶注入的粒子为Ge，非晶化注入的工艺条件可以为：注入的能量为0.5-30keV，注入的剂量为5E14-5E16/cm2。
而后，去除掩膜层134，并进行平坦化工艺，直至暴露出金属功函数层，分别在NMOS器件区域和PMOS器件区域的开口中形成具有不同应力作用的氮化钨的顶层金属层130。
至此，形成了本发明实施例的半导体器件，之后，可以根据需要，完成后续器件的加工，例如形成接触及互联结构等。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制。
虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (10)

1.一种半导体器件的制造方法，其特征在于，包括：
提供半导体衬底，所述衬底上具有去除伪栅后形成的开口；
在开口中填充顶层金属层，顶层金属层具有压应力；
对PMOS器件区域的顶层金属层，进行非晶化注入。
2.根据权利要求1所述的制造方法，其特征在于，在开口中填充顶层金属层的步骤包括：
采用PVD工艺，在开口中填充金属氮化钨的顶层金属层，顶层金属层氮化钨具有压应力。
3.根据权利要求2所述的制造方法，其特征在于，在开口中填充氮化钨的顶层金属层的步骤包括：
在PVD工艺中，以钨靶与氮气作为反应源，在开口中填充金属氮化钨的顶层金属层。
4.根据权利要求2所述的制造方法，其特征在于，非晶化注入的粒子为Ge。
5.根据权利要求4所述的制造方法，其特征在于，非晶化注入的工艺条件为：注入的能量为0.5-30keV，注入的剂量为5E14-5E16/cm2。
6.根据权利要求1所述的制造方法，其特征在于，在开口中填充金属顶层金属层以及进行非晶化注入的步骤包括：
进行顶层金属的填充，顶层金属具有压应力；
进行平坦化工艺；
在NMOS器件区域上覆盖掩膜层；
进行非晶化注入；
去除掩膜层；
去除开口之外的顶层金属，以在开口内形成顶层金属层。
7.根据权利要求1所述的制造方法，其特征在于，在开口中填充顶层金属层之前，还包括步骤：
在开口的内壁上形成高k栅介质层，并进行热退火。
8.根据权利要求7所述的制造方法，其特征在于，热退火的温度为450℃，时间为15s。
9.根据权利要求7所述的制造方法，其特征在于，在开口中填充顶层金属层之前，形成高k栅介质层之后还包括步骤：
在高k栅介质层上形成金属阻挡层；
在金属阻挡层上形成金属功函数层。
10.根据权利要求9所述的制造方法，其特征在于，所述金属阻挡层为TiN或WN。
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