WO2008096587A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
WO2008096587A1
WO2008096587A1 PCT/JP2008/050686 JP2008050686W WO2008096587A1 WO 2008096587 A1 WO2008096587 A1 WO 2008096587A1 JP 2008050686 W JP2008050686 W JP 2008050686W WO 2008096587 A1 WO2008096587 A1 WO 2008096587A1
Authority
WO
WIPO (PCT)
Prior art keywords
stress film
gate electrode
side wall
source
drain region
Prior art date
Application number
PCT/JP2008/050686
Other languages
English (en)
French (fr)
Inventor
Kenzo Manabe
Hidetatsu Nakamura
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2008557050A priority Critical patent/JP5401991B2/ja
Publication of WO2008096587A1 publication Critical patent/WO2008096587A1/ja

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7845Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being a conductive material, e.g. silicided S/D or Gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

 チャネル領域に大きな応力(歪み)が加わるようにゲート電極周辺の膜の応力と配置を最適化する。これによりMOSFETのキャリア移動度を向上させる。  (1)ゲート電極上のみに圧縮応力膜を有する、(2)ゲートサイドウォール、ソース/ドレイン領域上にのみ引張応力膜を有する、又は(3)ゲート電極上に圧縮応力膜と、ゲートサイドウォールとソース/ドレイン領域上に引張応力膜とを有する、のように構成されたnチャネル型MOSFET。(A)ゲート電極上のみに引張応力膜を有する、(B)ゲートサイドウォール、ソース/ドレイン領域上にのみ圧縮応力膜を有する、又は(C)ゲート電極上に引張応力膜と、ゲートサイドウォール・ソース/ドレイン領域上に圧縮応力膜とを有する、のように構成されたpチャネル型MOSFET。
PCT/JP2008/050686 2007-02-07 2008-01-21 半導体装置 WO2008096587A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008557050A JP5401991B2 (ja) 2007-02-07 2008-01-21 半導体装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007027882 2007-02-07
JP2007-027882 2007-02-07

Publications (1)

Publication Number Publication Date
WO2008096587A1 true WO2008096587A1 (ja) 2008-08-14

Family

ID=39681498

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/050686 WO2008096587A1 (ja) 2007-02-07 2008-01-21 半導体装置

Country Status (2)

Country Link
JP (1) JP5401991B2 (ja)
WO (1) WO2008096587A1 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102446726A (zh) * 2010-10-13 2012-05-09 中芯国际集成电路制造(上海)有限公司 一种金属栅极的形成方法
CN102623405A (zh) * 2011-01-30 2012-08-01 中国科学院微电子研究所 一种形成半导体结构的方法
WO2012153201A1 (en) * 2011-05-09 2012-11-15 International Business Machines Corporation Preserving stress benefits of uv curing in replacement gate transistor fabrication
US10868177B2 (en) 2010-08-09 2020-12-15 Sony Corporation Semiconductor device and manufacturing method thereof

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08321612A (ja) * 1995-05-26 1996-12-03 Ricoh Co Ltd 半導体装置及びその製造方法
JP2002093921A (ja) * 2000-09-11 2002-03-29 Hitachi Ltd 半導体装置の製造方法
JP2005005633A (ja) * 2003-06-16 2005-01-06 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2005311058A (ja) * 2004-04-21 2005-11-04 Rohm Co Ltd 半導体装置及びその製造方法
JP2006059980A (ja) * 2004-08-19 2006-03-02 Renesas Technology Corp 半導体装置及びその製造方法
JP2006121074A (ja) * 2004-10-20 2006-05-11 Samsung Electronics Co Ltd 半導体素子及びその製造方法
JP2006120718A (ja) * 2004-10-19 2006-05-11 Toshiba Corp 半導体装置およびその製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006165335A (ja) * 2004-12-08 2006-06-22 Toshiba Corp 半導体装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08321612A (ja) * 1995-05-26 1996-12-03 Ricoh Co Ltd 半導体装置及びその製造方法
JP2002093921A (ja) * 2000-09-11 2002-03-29 Hitachi Ltd 半導体装置の製造方法
JP2005005633A (ja) * 2003-06-16 2005-01-06 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2005311058A (ja) * 2004-04-21 2005-11-04 Rohm Co Ltd 半導体装置及びその製造方法
JP2006059980A (ja) * 2004-08-19 2006-03-02 Renesas Technology Corp 半導体装置及びその製造方法
JP2006120718A (ja) * 2004-10-19 2006-05-11 Toshiba Corp 半導体装置およびその製造方法
JP2006121074A (ja) * 2004-10-20 2006-05-11 Samsung Electronics Co Ltd 半導体素子及びその製造方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10868177B2 (en) 2010-08-09 2020-12-15 Sony Corporation Semiconductor device and manufacturing method thereof
CN102446726A (zh) * 2010-10-13 2012-05-09 中芯国际集成电路制造(上海)有限公司 一种金属栅极的形成方法
CN102623405A (zh) * 2011-01-30 2012-08-01 中国科学院微电子研究所 一种形成半导体结构的方法
WO2012153201A1 (en) * 2011-05-09 2012-11-15 International Business Machines Corporation Preserving stress benefits of uv curing in replacement gate transistor fabrication
US8421132B2 (en) 2011-05-09 2013-04-16 International Business Machines Corporation Post-planarization UV curing of stress inducing layers in replacement gate transistor fabrication
GB2503848A (en) * 2011-05-09 2014-01-08 Ibm Preserving stress benefits of UV curing in replacement gate transistor fabrication
CN103620748A (zh) * 2011-05-09 2014-03-05 国际商业机器公司 保留替代栅极晶体管制造中的uv固化的应力益处
GB2503848B (en) * 2011-05-09 2015-07-29 Ibm Preserving stress benefits of UV curing in replacement gate transistor fabrication

Also Published As

Publication number Publication date
JPWO2008096587A1 (ja) 2010-05-20
JP5401991B2 (ja) 2014-01-29

Similar Documents

Publication Publication Date Title
TW200746313A (en) A tensile strained NMOS transistor using group III-N source/drain regions
WO2010030493A3 (en) Transistor with a passive gate and methods of fabricating the same
TW200746314A (en) High mobility P-channel trench power metal-oxide semiconductor field-effect transistors
TW200620479A (en) MOSFET device with localized stressor
TW200633219A (en) Device with stepped source/drain region profile
GB2448258A (en) Epitaxial silicon germanium for reduced contact resistance in field-effect transistors
WO2012119125A3 (en) High performance graphene transistors and fabrication processes thereof
GB2444681A (en) Multigate device with recessed strain regions
WO2009036266A3 (en) Iii-nitride bidirectional switches
WO2008002879A3 (en) Lateral trench gate fet with direct source-drain current path
GB2487846B (en) Field effect transistor having nanostructure channel
WO2005053032A3 (en) Trench insulated gate field effect transistor
WO2009120612A3 (en) Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure
TW200741976A (en) Methods for fabricating a stressed MOS device
TW200943540A (en) Semiconductor device
TW200723533A (en) Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device
TW200644224A (en) Semiconductor device and method for manufacturing the same
WO2006066194A3 (en) Strained nmos transistor featuring deep carbon doped regions and raised donor doped source and drain
SG150430A1 (en) Strained semiconductor device and method of making same
EP2036130A4 (en) N-CHANNEL MOSFETS COMPRISING DUAL STRAIN ELEMENTS AND METHODS OF MANUFACTURING THEREOF
WO2007075755A3 (en) Cmos device with asymmetric gate strain
TW200723409A (en) Power semiconductor device having improved performance and method
JP2010206100A5 (ja)
WO2009140224A3 (en) Power field effect transistor
SG165354A1 (en) Integrated circuit system employing stress memorization transfer

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08703536

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2008557050

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08703536

Country of ref document: EP

Kind code of ref document: A1