JP5657176B2 - 置換ゲート・トランジスタの作製におけるｕｖ硬化の応力利得の保持 - Google Patents

置換ゲート・トランジスタの作製におけるｕｖ硬化の応力利得の保持 Download PDF

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JP5657176B2
JP5657176B2 JP2014509858A JP2014509858A JP5657176B2 JP 5657176 B2 JP5657176 B2 JP 5657176B2 JP 2014509858 A JP2014509858 A JP 2014509858A JP 2014509858 A JP2014509858 A JP 2014509858A JP 5657176 B2 JP5657176 B2 JP 5657176B2
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nitride layer
layer
curing
stress
trench
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JP2014519192A (ja
JP2014519192A5 (https=
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イー、チュンチェン
グオ、デシャオ
カイ、ミング
クルカーニ、プラニタ
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International Business Machines Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01324—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T or inverted-T
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H10D84/0133—Manufacturing common source or drain regions between multiple IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6536—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to radiation, e.g. visible light
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)
JP2014509858A 2011-05-09 2012-02-24 置換ゲート・トランジスタの作製におけるｕｖ硬化の応力利得の保持 Expired - Fee Related JP5657176B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/103,149 US8421132B2 (en) 2011-05-09 2011-05-09 Post-planarization UV curing of stress inducing layers in replacement gate transistor fabrication
US13/103,149 2011-05-09
PCT/IB2012/050847 WO2012153201A1 (en) 2011-05-09 2012-02-24 Preserving stress benefits of uv curing in replacement gate transistor fabrication

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JP2014519192A JP2014519192A (ja) 2014-08-07
JP2014519192A5 JP2014519192A5 (https=) 2014-09-18
JP5657176B2 true JP5657176B2 (ja) 2015-01-21

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US (1) US8421132B2 (https=)
JP (1) JP5657176B2 (https=)
CN (1) CN103620748B (https=)
DE (1) DE112012001089B4 (https=)
GB (1) GB2503848B (https=)
WO (1) WO2012153201A1 (https=)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8765561B2 (en) * 2011-06-06 2014-07-01 United Microelectronics Corp. Method for fabricating semiconductor device
US8658487B2 (en) * 2011-11-17 2014-02-25 United Microelectronics Corp. Semiconductor device and fabrication method thereof
US8803249B2 (en) * 2012-08-09 2014-08-12 Taiwan Semiconductor Manufacturing Co., Ltd. Profile pre-shaping for replacement poly gate interlayer dielectric
US9293466B2 (en) 2013-06-19 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded SRAM and methods of forming the same
US9520474B2 (en) * 2013-09-12 2016-12-13 Taiwan Semiconductor Manufacturing Company Limited Methods of forming a semiconductor device with a gate stack having tapered sidewalls
CN104637797A (zh) * 2013-11-12 2015-05-20 中国科学院微电子研究所 一种后栅工艺中ild层的处理方法
CN104681597A (zh) * 2013-11-28 2015-06-03 中国科学院微电子研究所 半导体器件及其制造方法
US9312174B2 (en) * 2013-12-17 2016-04-12 United Microelectronics Corp. Method for manufacturing contact plugs for semiconductor devices
CN105225949B (zh) * 2014-05-26 2018-08-21 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法和电子装置
US10068982B2 (en) * 2014-05-29 2018-09-04 Taiwan Semiconductor Manufacturing Co., Ltd Structure and formation method of semiconductor device structure with metal gate
CN105336588B (zh) * 2014-05-29 2019-01-22 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
US10164049B2 (en) 2014-10-06 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method of semiconductor device with gate stack
KR102224386B1 (ko) * 2014-12-18 2021-03-08 삼성전자주식회사 집적 회로 장치의 제조 방법
KR101785803B1 (ko) 2015-05-29 2017-10-16 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 반도체 디바이스 구조체의 형성 방법
US9553090B2 (en) 2015-05-29 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method of semiconductor device structure
CN107170684B (zh) * 2016-03-08 2020-05-08 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法
US10147649B2 (en) 2016-05-27 2018-12-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with gate stack and method for forming the same
US10020401B2 (en) 2016-11-29 2018-07-10 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for straining a transistor gate through interlayer dielectric (ILD) doping schemes
US9786754B1 (en) * 2017-02-06 2017-10-10 Vanguard International Semiconductor Corporation Method for forming semiconductor device structure
CN109585293B (zh) * 2017-09-29 2021-12-24 台湾积体电路制造股份有限公司 切割金属工艺中的基脚去除
JP7837860B2 (ja) * 2019-08-09 2026-03-31 ヒタチ・エナジー・リミテッド 歪み強化型ＳｉＣパワー半導体デバイスおよび製造方法

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6033963A (en) 1999-08-30 2000-03-07 Taiwan Semiconductor Manufacturing Company Method of forming a metal gate for CMOS devices using a replacement gate process
US6465309B1 (en) 2000-12-12 2002-10-15 Advanced Micro Devices, Inc. Silicide gate transistors
KR20030075745A (ko) 2002-03-20 2003-09-26 삼성전자주식회사 반도체 소자의 금속게이트 형성방법
JP2008518476A (ja) * 2004-10-29 2008-05-29 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 異なるように歪ませた歪みチャネル領域を有する半導体領域を含む、半導体デバイスおよびその製造方法
JP5091397B2 (ja) 2005-10-27 2012-12-05 パナソニック株式会社 半導体装置
US7510943B2 (en) * 2005-12-16 2009-03-31 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
US7678630B2 (en) * 2006-02-15 2010-03-16 Infineon Technologies Ag Strained semiconductor device and method of making same
JP2007324391A (ja) * 2006-06-01 2007-12-13 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US20070281405A1 (en) 2006-06-02 2007-12-06 International Business Machines Corporation Methods of stressing transistor channel with replaced gate and related structures
US7601574B2 (en) 2006-10-25 2009-10-13 Globalfoundries Inc. Methods for fabricating a stress enhanced MOS transistor
WO2008096587A1 (ja) 2007-02-07 2008-08-14 Nec Corporation 半導体装置
JP5003515B2 (ja) 2007-03-20 2012-08-15 ソニー株式会社 半導体装置
US7846804B2 (en) * 2007-06-05 2010-12-07 United Microelectronics Corp. Method for fabricating high tensile stress film
US7842592B2 (en) 2007-06-08 2010-11-30 International Business Machines Corporation Channel strain engineering in field-effect-transistor
JP2008306132A (ja) * 2007-06-11 2008-12-18 Renesas Technology Corp 半導体装置の製造方法
US7911001B2 (en) * 2007-07-15 2011-03-22 Samsung Electronics Co., Ltd. Methods for forming self-aligned dual stress liners for CMOS semiconductor devices
US20090035928A1 (en) * 2007-07-30 2009-02-05 Hegde Rama I Method of processing a high-k dielectric for cet scaling
DE102007046849B4 (de) 2007-09-29 2014-11-06 Advanced Micro Devices, Inc. Verfahren zur Herstellung von Gateelektrodenstrukturen mit großem ε nach der Transistorherstellung
US20090179308A1 (en) 2008-01-14 2009-07-16 Chris Stapelmann Method of Manufacturing a Semiconductor Device
JP5309619B2 (ja) * 2008-03-07 2013-10-09 ソニー株式会社 半導体装置およびその製造方法
JP5147471B2 (ja) * 2008-03-13 2013-02-20 パナソニック株式会社 半導体装置
JP2009277908A (ja) 2008-05-15 2009-11-26 Toshiba Corp 半導体装置の製造方法及び半導体装置
DE102009039521B4 (de) 2009-08-31 2018-02-15 Globalfoundries Dresden Module One Llc & Co. Kg Verbesserte Füllbedingungen in einem Austauschgateverfahren unter Anwendung einer zugverspannten Deckschicht
CN101866859B (zh) 2010-07-07 2012-07-04 北京大学 一种沟道应力引入方法及采用该方法制备的场效应晶体管
US8293605B2 (en) * 2011-02-25 2012-10-23 GlobalFoundries, Inc. Methods for fabricating a CMOS integrated circuit having a dual stress layer (DSL)

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GB2503848B (en) 2015-07-29
US20120286375A1 (en) 2012-11-15
DE112012001089T5 (de) 2014-06-26
JP2014519192A (ja) 2014-08-07
DE112012001089B4 (de) 2016-01-28
GB2503848A (en) 2014-01-08
WO2012153201A1 (en) 2012-11-15
CN103620748B (zh) 2016-06-22
CN103620748A (zh) 2014-03-05
GB201318709D0 (en) 2013-12-04
US8421132B2 (en) 2013-04-16

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