DE112004001117B4 - Halbleiterbauelement und Verfahren zur Herstellung - Google Patents

Halbleiterbauelement und Verfahren zur Herstellung Download PDF

Info

Publication number
DE112004001117B4
DE112004001117B4 DE112004001117T DE112004001117T DE112004001117B4 DE 112004001117 B4 DE112004001117 B4 DE 112004001117B4 DE 112004001117 T DE112004001117 T DE 112004001117T DE 112004001117 T DE112004001117 T DE 112004001117T DE 112004001117 B4 DE112004001117 B4 DE 112004001117B4
Authority
DE
Germany
Prior art keywords
layer
gate
semiconductor
forming
dielectric material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE112004001117T
Other languages
German (de)
English (en)
Other versions
DE112004001117T5 (de
Inventor
Zoran Krivokapic
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
GlobalFoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries Inc filed Critical GlobalFoundries Inc
Publication of DE112004001117T5 publication Critical patent/DE112004001117T5/de
Application granted granted Critical
Publication of DE112004001117B4 publication Critical patent/DE112004001117B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6757Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00Bonding of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6729Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743Silicon
    • H10D30/6744Monocrystalline silicon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/751Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions

Landscapes

  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
  • Electrodes Of Semiconductors (AREA)
DE112004001117T 2003-06-23 2004-06-05 Halbleiterbauelement und Verfahren zur Herstellung Expired - Fee Related DE112004001117B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/601,401 US6913959B2 (en) 2003-06-23 2003-06-23 Method of manufacturing a semiconductor device having a MESA structure
US10/601,401 2003-06-23
PCT/US2004/017727 WO2005001908A2 (en) 2003-06-23 2004-06-05 Strained semiconductor device and method of manufacture

Publications (2)

Publication Number Publication Date
DE112004001117T5 DE112004001117T5 (de) 2006-06-29
DE112004001117B4 true DE112004001117B4 (de) 2011-12-01

Family

ID=33552165

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112004001117T Expired - Fee Related DE112004001117B4 (de) 2003-06-23 2004-06-05 Halbleiterbauelement und Verfahren zur Herstellung

Country Status (8)

Country Link
US (1) US6913959B2 (https=)
JP (1) JP2007519217A (https=)
KR (1) KR101065046B1 (https=)
CN (1) CN100521231C (https=)
DE (1) DE112004001117B4 (https=)
GB (1) GB2418533B (https=)
TW (1) TWI341546B (https=)
WO (1) WO2005001908A2 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100725112B1 (ko) * 2005-04-27 2007-06-04 한국과학기술원 백―바이어스를 이용하여 soi 기판에 형성된 플래시 블록을 소거하기 위한 플래시 메모리 소자의 제조 방법, 그 소거 방법 및 그 구조
JP4988217B2 (ja) * 2006-02-03 2012-08-01 株式会社日立製作所 Mems構造体の製造方法
US9184263B2 (en) * 2013-12-30 2015-11-10 Globalfoundries Inc. Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices
US10170332B2 (en) * 2014-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET thermal protection methods and related structures
US10014410B2 (en) 2014-12-02 2018-07-03 Renesas Electronics Corporation Method for producing semiconductor device and semiconductor device
US20170366965A1 (en) * 2016-06-21 2017-12-21 Chiun Mai Communication Systems, Inc. Communication device, communication system and method therefor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002078075A1 (en) * 2001-03-23 2002-10-03 Université Catholique de Louvain Fabrication method of so1 semiconductor devices

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0510667B1 (en) 1991-04-26 1996-09-11 Canon Kabushiki Kaisha Semiconductor device having an improved insulated gate transistor
US5397904A (en) * 1992-07-02 1995-03-14 Cornell Research Foundation, Inc. Transistor microstructure
DE4340967C1 (de) * 1993-12-01 1994-10-27 Siemens Ag Verfahren zur Herstellung einer integrierten Schaltungsanordnung mit mindestens einem MOS-Transistor
JP3078720B2 (ja) * 1994-11-02 2000-08-21 三菱電機株式会社 半導体装置およびその製造方法
DE19544721C1 (de) * 1995-11-30 1997-04-30 Siemens Ag Verfahren zur Herstellung einer integrierten Schaltungsanordnung mit mindestens einem MOS-Transistor
JP3472401B2 (ja) * 1996-01-17 2003-12-02 三菱電機株式会社 半導体装置の製造方法
DE19711482C2 (de) * 1997-03-19 1999-01-07 Siemens Ag Verfahren zur Herstellung eines vertikalen MOS-Transistors
US6118161A (en) 1997-04-30 2000-09-12 Texas Instruments Incorporated Self-aligned trenched-channel lateral-current-flow transistor
JPH1131659A (ja) * 1997-07-10 1999-02-02 Toshiba Corp 半導体装置の製造方法
US6200866B1 (en) * 1998-02-23 2001-03-13 Sharp Laboratories Of America, Inc. Use of silicon germanium and other alloys as the replacement gate for the fabrication of MOSFET
KR100280106B1 (ko) * 1998-04-16 2001-03-02 윤종용 트렌치 격리 형성 방법
US6080612A (en) * 1998-05-20 2000-06-27 Sharp Laboratories Of America, Inc. Method of forming an ultra-thin SOI electrostatic discharge protection device
US6339002B1 (en) * 1999-02-10 2002-01-15 International Business Machines Corporation Method utilizing CMP to fabricate double gate MOSFETS with conductive sidewall contacts
US6770689B1 (en) * 1999-03-19 2004-08-03 Sakura Color Products Corp. Aqueous glittering ink
US6252284B1 (en) 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
JP2002151688A (ja) * 2000-08-28 2002-05-24 Mitsubishi Electric Corp Mos型半導体装置およびその製造方法
US6495401B1 (en) 2000-10-12 2002-12-17 Sharp Laboratories Of America, Inc. Method of forming an ultra-thin SOI MOS transistor
KR100346845B1 (ko) * 2000-12-16 2002-08-03 삼성전자 주식회사 반도체 장치의 얕은 트렌치 아이솔레이션 형성방법
US6635923B2 (en) 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
KR100428768B1 (ko) * 2001-08-29 2004-04-30 삼성전자주식회사 트렌치 소자 분리형 반도체 장치 및 그 형성 방법
US6689650B2 (en) 2001-09-27 2004-02-10 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US6611029B1 (en) 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6872606B2 (en) * 2003-04-03 2005-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with raised segment

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002078075A1 (en) * 2001-03-23 2002-10-03 Université Catholique de Louvain Fabrication method of so1 semiconductor devices

Also Published As

Publication number Publication date
TWI341546B (en) 2011-05-01
GB2418533A (en) 2006-03-29
WO2005001908A2 (en) 2005-01-06
GB0523869D0 (en) 2006-01-04
JP2007519217A (ja) 2007-07-12
US20050003593A1 (en) 2005-01-06
KR20060062035A (ko) 2006-06-09
CN100521231C (zh) 2009-07-29
DE112004001117T5 (de) 2006-06-29
US6913959B2 (en) 2005-07-05
CN1809927A (zh) 2006-07-26
KR101065046B1 (ko) 2011-09-19
WO2005001908A3 (en) 2005-06-02
TW200507030A (en) 2005-02-16
GB2418533B (en) 2007-03-28

Similar Documents

Publication Publication Date Title
DE112007002306B4 (de) Verspannter Feldeffekttransistor und Verfahren zu dessen Herstellung
DE102009055392B4 (de) Halbleiterbauelement und Verfahren zur Herstellung des Halbleiterbauelements
DE60001601T2 (de) Fertigungsverfahren zur Herstellung eines CMOS integrieten Schaltkreises mit vertikalen Transistoren
DE102008063427B4 (de) Verfahren zum selektiven Herstellen eines Transistors mit einem eingebetteten verformungsinduzierenden Material mit einer graduell geformten Gestaltung
DE112006001169B4 (de) Verfahren zur Herstellung eines SOI-Bauelements
DE10323013B4 (de) Verfahren zur Herstellung eines Halbleiterbauelementes mit PMOS- und NMOS-Transistor
DE102010029527B4 (de) Verfahren zur Herstellung eines selbstjustierenden Transistors mit Mehrfachgate auf einem Vollsubstrat
DE102008011814B4 (de) CMOS-Bauelement mit vergrabener isolierender Schicht und verformten Kanalgebieten sowie Verfahren zum Herstellen derselben
DE102005052054B4 (de) Halbleiterbauteil mit Transistoren mit verformten Kanalgebieten und Verfahren zu seiner Herstellung
DE102008049733B3 (de) Transistor mit eingebettetem Si/Ge-Material mit geringerem Abstand zum Kanalgebiet und Verfahren zur Herstellung des Transistors
DE112011101378B4 (de) Epitaxie von Delta-Monoschicht-Dotierstoffen für eingebettetes Source/Drain-Silicid
DE10255849B4 (de) Verbesserte Drain/Source-Erweiterungsstruktur eines Feldeffekttransistors mit dotierten Seitenwandabstandselementen mit hoher Permittivität und Verfahren zu deren Herstellung
DE102009010882B4 (de) Transistor mit einer eingebetteten Halbleiterlegierung in Drain- und Sourcegebieten, die sich unter die Gateelektrode erstreckt und Verfahren zum Herstellen des Transistors
DE102005020133B4 (de) Verfahren zur Herstellung eines Transistorelements mit Technik zur Herstellung einer Kontaktisolationsschicht mit verbesserter Spannungsübertragungseffizienz
DE112008002270B4 (de) Verfahren zur Herstellung von MOS-Strukturen mit einem geringeren Kontaktwiderstand
DE102008054075B4 (de) Halbleiterbauelement mit Abgesenktem Drain- und Sourcebereich in Verbindung mit einem Verfahren zur komplexen Silizidherstellung in Transistoren
DE112007003116B4 (de) Verfahren zur Herstellung eines verspannten Transistors und Transistor
DE102008049725B4 (de) CMOS-Bauelement mit NMOS-Transistoren und PMOS-Transistoren mit stärkeren verformungsinduzierenden Quellen und Metallsilizidgebieten mit geringem Abstand und Verfahren zur Herstellung des Bauelements
DE3932621A1 (de) Halbleitervorrichtung und verfahren zur herstellung derselben
DE102004026149A1 (de) Technik zum Erzeugen mechanischer Spannung in unterschiedlichen Kanalgebieten durch Bilden einer Ätzstoppschicht, die eine unterschiedlich modifizierte innere Spannung aufweist.
DE102004052617B4 (de) Verfahren zur Herstellung eines Halbleiterbauelements und Halbleiterbauelement mit Halbleitergebieten, die unterschiedlich verformte Kanalgebiete aufweisen
DE102005057073B4 (de) Herstellungsverfahren zur Verbesserung der mechanischen Spannungsübertragung in Kanalgebieten von NMOS- und PMOS-Transistoren und entsprechendes Halbleiterbauelement
DE102006009226B9 (de) Verfahren zum Herstellen eines Transistors mit einer erhöhten Schwellwertstabilität ohne Durchlass-Strombeeinträchtigung und Transistor
DE102010001406A1 (de) Halbleiterbauelement, das durch ein Austausch-Gate-Verfahren auf der Grundlage eines früh aufgebrachten Austrittsarbeitsmetalls hergestellt ist
DE102007030054A1 (de) Transistor mit reduziertem Gatewiderstand und verbesserter Verspannungsübertragungseffizienz und Verfahren zur Herstellung desselben

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law

Ref document number: 112004001117

Country of ref document: DE

Date of ref document: 20060629

Kind code of ref document: P

8127 New person/name/address of the applicant

Owner name: GLOBALFOUNDRIES INC., GRAND CAYMAN, KY

8128 New person/name/address of the agent

Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER,

R016 Response to examination communication
R018 Grant decision by examination section/examining division
R020 Patent grant now final

Effective date: 20120302

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee