DE10318284A1 - Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur - Google Patents

Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur Download PDF

Info

Publication number
DE10318284A1
DE10318284A1 DE10318284A DE10318284A DE10318284A1 DE 10318284 A1 DE10318284 A1 DE 10318284A1 DE 10318284 A DE10318284 A DE 10318284A DE 10318284 A DE10318284 A DE 10318284A DE 10318284 A1 DE10318284 A1 DE 10318284A1
Authority
DE
Germany
Prior art keywords
layer
strained
substrate
layer structure
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE10318284A
Other languages
German (de)
English (en)
Inventor
Siegfried Prof. Dr. Mantl
Bernhard Dr. Holländer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Forschungszentrum Juelich GmbH
Original Assignee
Forschungszentrum Juelich GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Forschungszentrum Juelich GmbH filed Critical Forschungszentrum Juelich GmbH
Priority to DE10318284A priority Critical patent/DE10318284A1/de
Priority to JP2006504301A priority patent/JP5065676B2/ja
Priority to PCT/DE2004/000780 priority patent/WO2004095553A2/de
Priority to US10/553,562 priority patent/US7416965B2/en
Priority to EP04727506A priority patent/EP1616346A2/de
Publication of DE10318284A1 publication Critical patent/DE10318284A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
    • H10P14/3211—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions

Landscapes

  • Recrystallisation Techniques (AREA)
DE10318284A 2003-04-22 2003-04-22 Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur Withdrawn DE10318284A1 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE10318284A DE10318284A1 (de) 2003-04-22 2003-04-22 Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
JP2006504301A JP5065676B2 (ja) 2003-04-22 2004-04-15 基板上に歪層を製造する方法及び層構造
PCT/DE2004/000780 WO2004095553A2 (de) 2003-04-22 2004-04-15 Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur
US10/553,562 US7416965B2 (en) 2003-04-22 2004-04-15 Method for producing a strained layer on a substrate and corresponding layer structure
EP04727506A EP1616346A2 (de) 2003-04-22 2004-04-15 Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10318284A DE10318284A1 (de) 2003-04-22 2003-04-22 Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur

Publications (1)

Publication Number Publication Date
DE10318284A1 true DE10318284A1 (de) 2004-11-25

Family

ID=33304880

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10318284A Withdrawn DE10318284A1 (de) 2003-04-22 2003-04-22 Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur

Country Status (5)

Country Link
US (1) US7416965B2 (https=)
EP (1) EP1616346A2 (https=)
JP (1) JP5065676B2 (https=)
DE (1) DE10318284A1 (https=)
WO (1) WO2004095553A2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006010273A1 (de) * 2006-03-02 2007-09-13 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem spannungskompensierten Schichtstapel mit geringer Defektdichte und Schichtstapel

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004048096A1 (de) * 2004-09-30 2006-04-27 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
US7229901B2 (en) * 2004-12-16 2007-06-12 Wisconsin Alumni Research Foundation Fabrication of strained heterojunction structures
JP4654710B2 (ja) * 2005-02-24 2011-03-23 信越半導体株式会社 半導体ウェーハの製造方法
FR2891281B1 (fr) * 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
FR2892855B1 (fr) * 2005-10-28 2008-07-18 Commissariat Energie Atomique Procede de fabrication d'une structure en couches minces et structure en couches minces ainsi obtenue
WO2007070321A2 (en) * 2005-12-09 2007-06-21 Semequip Inc. System and method for the manufacture of semiconductor devices by the implantation of carbon clusters
FR2896255B1 (fr) 2006-01-17 2008-05-09 Soitec Silicon On Insulator Procede d'ajustement de la contrainte d'un substrat en un materiau semi-conducteur
EP1808886A3 (fr) * 2006-01-17 2009-08-12 S.O.I.T.E.C. Silicon on Insulator Technologies Procédé d'ajustement de la contrainte d'un substrat en un matériau semi-conducteur
DE102006004870A1 (de) * 2006-02-02 2007-08-16 Siltronic Ag Halbleiterschichtstruktur und Verfahren zur Herstellung einer Halbleiterschichtstruktur
JP4649511B2 (ja) * 2006-02-15 2011-03-09 富士通株式会社 光導波路デバイス
US7514726B2 (en) * 2006-03-21 2009-04-07 The United States Of America As Represented By The Aministrator Of The National Aeronautics And Space Administration Graded index silicon geranium on lattice matched silicon geranium semiconductor alloy
US7888197B2 (en) * 2007-01-11 2011-02-15 International Business Machines Corporation Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer
US7494886B2 (en) 2007-01-12 2009-02-24 International Business Machines Corporation Uniaxial strain relaxation of biaxial-strained thin films using ion implantation
US7558371B2 (en) * 2007-10-18 2009-07-07 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Method of generating X-ray diffraction data for integral detection of twin defects in super-hetero-epitaxial materials
JP5552276B2 (ja) * 2008-08-01 2014-07-16 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
CN102714144A (zh) * 2010-01-15 2012-10-03 住友化学株式会社 半导体基板、电子器件及半导体基板的制造方法
US8361889B2 (en) * 2010-07-06 2013-01-29 International Business Machines Corporation Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator
DE102010046215B4 (de) * 2010-09-21 2019-01-03 Infineon Technologies Austria Ag Halbleiterkörper mit verspanntem Bereich, Elektronisches Bauelement und ein Verfahren zum Erzeugen des Halbleiterkörpers.
US8501600B2 (en) * 2010-09-27 2013-08-06 Applied Materials, Inc. Methods for depositing germanium-containing layers
US9583364B2 (en) 2012-12-31 2017-02-28 Sunedison Semiconductor Limited (Uen201334164H) Processes and apparatus for preparing heterostructures with reduced strain by radial compression
US9614026B2 (en) 2013-03-13 2017-04-04 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration High mobility transport layer structures for rhombohedral Si/Ge/SiGe devices
FR3003686B1 (fr) * 2013-03-20 2016-11-04 St Microelectronics Crolles 2 Sas Procede de formation d'une couche de silicium contraint
US9305781B1 (en) 2015-04-30 2016-04-05 International Business Machines Corporation Structure and method to form localized strain relaxed SiGe buffer layer
CN111733378B (zh) * 2020-05-15 2022-12-13 中国兵器科学研究院宁波分院 一种钢表面的涂层结构及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19802977A1 (de) * 1998-01-27 1999-07-29 Forschungszentrum Juelich Gmbh Verfahren zur Herstellung einer einkristallinen Schicht auf einem nicht gitterangepaßten Substrat, sowie eine oder mehrere solcher Schichten enthaltendes Bauelement
US6326667B1 (en) * 1999-09-09 2001-12-04 Kabushiki Kaisha Toshiba Semiconductor devices and methods for producing semiconductor devices
US6429061B1 (en) * 2000-07-26 2002-08-06 International Business Machines Corporation Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation
JP2002343880A (ja) * 2001-05-17 2002-11-29 Sharp Corp 半導体基板及びその製造方法ならびに半導体装置及びその製造方法
DE10218381A1 (de) * 2002-04-24 2004-02-26 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer oder mehrerer einkristalliner Schichten mit jeweils unterschiedlicher Gitterstruktur in einer Ebene einer Schichtenfolge

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5442205A (en) 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
EP1350290B1 (en) * 2000-08-04 2006-11-22 Amberwave Systems Corporation Silicon wafer with embedded optoelectronic material for monolithic oeic
WO2002015244A2 (en) * 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Process for producing semiconductor article using graded expitaxial growth
JP2004531054A (ja) * 2001-03-02 2004-10-07 アンバーウェーブ システムズ コーポレイション 高速ｃｍｏｓ電子機器及び高速アナログ回路のための緩和シリコンゲルマニウムプラットフォーム
US6593625B2 (en) * 2001-06-12 2003-07-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
JP2003008022A (ja) * 2001-06-20 2003-01-10 Mitsubishi Materials Silicon Corp 半導体基板及び電界効果型トランジスタ並びにこれらの製造方法
JP4854871B2 (ja) * 2001-06-20 2012-01-18 株式会社Ｓｕｍｃｏ 半導体基板及び電界効果型トランジスタ並びにこれらの製造方法
US6562703B1 (en) * 2002-03-13 2003-05-13 Sharp Laboratories Of America, Inc. Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content
US6972245B2 (en) * 2002-05-15 2005-12-06 The Regents Of The University Of California Method for co-fabricating strained and relaxed crystalline and poly-crystalline structures
US6841457B2 (en) * 2002-07-16 2005-01-11 International Business Machines Corporation Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion
DE10310740A1 (de) * 2003-03-10 2004-09-30 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer spannungsrelaxierten Schichtstruktur auf einem nicht gitterangepassten Substrat, sowie Verwendung eines solchen Schichtsystems in elektronischen und/oder optoelektronischen Bauelementen
JP2004281764A (ja) * 2003-03-17 2004-10-07 Seiko Epson Corp 半導体装置およびその製造方法
DE10318283A1 (de) * 2003-04-22 2004-11-25 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
US7049660B2 (en) * 2003-05-30 2006-05-23 International Business Machines Corporation High-quality SGOI by oxidation near the alloy melting temperature

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19802977A1 (de) * 1998-01-27 1999-07-29 Forschungszentrum Juelich Gmbh Verfahren zur Herstellung einer einkristallinen Schicht auf einem nicht gitterangepaßten Substrat, sowie eine oder mehrere solcher Schichten enthaltendes Bauelement
WO1999038201A1 (de) * 1998-01-27 1999-07-29 Forschungszentrum Jülich GmbH Verfahren zur herstellung einer einkristallinen schicht auf einem nicht gitterangepassten substrat, sowie eine oder mehrere solcher schichten enthaltendes bauelement
US6326667B1 (en) * 1999-09-09 2001-12-04 Kabushiki Kaisha Toshiba Semiconductor devices and methods for producing semiconductor devices
US6429061B1 (en) * 2000-07-26 2002-08-06 International Business Machines Corporation Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation
JP2002343880A (ja) * 2001-05-17 2002-11-29 Sharp Corp 半導体基板及びその製造方法ならびに半導体装置及びその製造方法
DE10218381A1 (de) * 2002-04-24 2004-02-26 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer oder mehrerer einkristalliner Schichten mit jeweils unterschiedlicher Gitterstruktur in einer Ebene einer Schichtenfolge

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
E.A. Fitzgerald et al., Thin Solid Films 294, 3 (1997), S. 115 *
F. Schäffler, Semicond. Sci. Technol. 12, 1515 (1997), S. 1515-1549 *
Z. Cheng et al., Mat.Res.Soc. Symp. Proc., Vol. 686, 21 (2002), S. 21-26 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006010273A1 (de) * 2006-03-02 2007-09-13 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem spannungskompensierten Schichtstapel mit geringer Defektdichte und Schichtstapel
DE102006010273B4 (de) * 2006-03-02 2010-04-15 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem spannungskompensierten Schichtstapel mit geringer Defektdichte, Schichtstapel und dessen Verwendung

Also Published As

Publication number Publication date
US7416965B2 (en) 2008-08-26
JP2006524427A (ja) 2006-10-26
JP5065676B2 (ja) 2012-11-07
EP1616346A2 (de) 2006-01-18
WO2004095553A3 (de) 2004-12-23
US20060211221A1 (en) 2006-09-21
WO2004095553A2 (de) 2004-11-04

Similar Documents

Publication Publication Date Title
EP1604390B1 (de) Verfahren zur herstellung einer spannungsrelaxierten schichtstruktur auf einem nicht gitterangepassten substrat sowie verwendung eines solchen schichtsystems in elektronischen und/oder optoelektronischen bauelementen
DE10318284A1 (de) Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
WO2004095552A2 (de) Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur
DE112011102840B4 (de) Halbleiter, der durch elastische Kantenrelaxation eines Stressors in Kombination mit einer vergrabenen Isolierschicht verspannt wird
EP0838858B1 (de) Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung
KR100392166B1 (ko) 반도체 장치의 제조 방법 및 반도체 장치
US7348259B2 (en) Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers
DE69710031T2 (de) Verfahren zur Übertragung einer Halbleiterschicht mittels Silizium-auf-Isolator (SOI) Technologie
US7842940B2 (en) Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost
JP2006522469A5 (https=)
SG182855A1 (en) Semiconductor on insulator apparatus and method
EP1497855B1 (de) Verfahren zur herstellung einer oder mehrerer einkristalliner schichten mit jeweils unterschiedlicher gitterstruktur in einer ebene einer schichtenfolge
DE102006060886A1 (de) SOI-Baustein mit mehrfachen Kristallorientierungen
DE10229003B4 (de) Ein Verfahren zur Herstellung eines SOI-Feldeffekttransistorelements mit einem Rekombinationsgebiet
JP3933405B2 (ja) 半導体基板、半導体装置及びそれらの製造方法
DE10145699A1 (de) Schicht-Anordnung und Verfahren zum Herstellen einer Schicht-Anordnung
WO2006034679A2 (de) Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
R120 Application withdrawn or ip right abandoned
R120 Application withdrawn or ip right abandoned

Effective date: 20150507