DE10231192A1 - Verunreinigungssteuerung für Herstellungsverfahren eingebetteter ferroelektrischer Bauelemente - Google Patents

Verunreinigungssteuerung für Herstellungsverfahren eingebetteter ferroelektrischer Bauelemente

Info

Publication number
DE10231192A1
DE10231192A1 DE10231192A DE10231192A DE10231192A1 DE 10231192 A1 DE10231192 A1 DE 10231192A1 DE 10231192 A DE10231192 A DE 10231192A DE 10231192 A DE10231192 A DE 10231192A DE 10231192 A1 DE10231192 A1 DE 10231192A1
Authority
DE
Germany
Prior art keywords
substrate
ferroelectric
edge
etchant
sacrificial layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE10231192A
Other languages
German (de)
English (en)
Inventor
Stephen R Gilbert
Trace Q Hurd
Laura W Mirkarimi
Scott Summerfelt
Luigi Colombo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of DE10231192A1 publication Critical patent/DE10231192A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0402—Apparatus for fluid treatment
    • H10P72/0418—Apparatus for fluid treatment for etching
    • H10P72/0422—Apparatus for fluid treatment for etching for wet etching
    • H10P72/0424—Apparatus for fluid treatment for etching for wet etching using mainly spraying means, e.g. nozzles
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/212—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H10P50/285—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means of materials not containing Si, e.g. PZT or Al2O3

Landscapes

  • Semiconductor Memories (AREA)
  • Weting (AREA)
DE10231192A 2001-08-08 2002-07-10 Verunreinigungssteuerung für Herstellungsverfahren eingebetteter ferroelektrischer Bauelemente Withdrawn DE10231192A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/925,201 US6709875B2 (en) 2001-08-08 2001-08-08 Contamination control for embedded ferroelectric device fabrication processes

Publications (1)

Publication Number Publication Date
DE10231192A1 true DE10231192A1 (de) 2003-03-06

Family

ID=25451373

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10231192A Withdrawn DE10231192A1 (de) 2001-08-08 2002-07-10 Verunreinigungssteuerung für Herstellungsverfahren eingebetteter ferroelektrischer Bauelemente

Country Status (4)

Country Link
US (1) US6709875B2 (https=)
JP (1) JP4285954B2 (https=)
KR (1) KR100880109B1 (https=)
DE (1) DE10231192A1 (https=)

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JP5132859B2 (ja) * 2001-08-24 2013-01-30 ステラケミファ株式会社 多成分を有するガラス基板用の微細加工表面処理液
US6767750B2 (en) * 2001-12-31 2004-07-27 Texas Instruments Incorporated Detection of AIOx ears for process control in FeRAM processing
JP2004087691A (ja) * 2002-08-26 2004-03-18 Fujitsu Ltd ゲート絶縁膜を除去する方法
US6876021B2 (en) * 2002-11-25 2005-04-05 Texas Instruments Incorporated Use of amorphous aluminum oxide on a capacitor sidewall for use as a hydrogen barrier
KR100504693B1 (ko) * 2003-02-10 2005-08-03 삼성전자주식회사 강유전체 메모리 소자 및 그 제조방법
US20050037521A1 (en) * 2003-08-15 2005-02-17 Uwe Wellhausen Methods and apparatus for processing semiconductor devices by gas annealing
CN100505265C (zh) * 2003-12-26 2009-06-24 富士通微电子株式会社 半导体装置、半导体装置的制造方法
US7180141B2 (en) * 2004-12-03 2007-02-20 Texas Instruments Incorporated Ferroelectric capacitor with parallel resistance for ferroelectric memory
CN100578821C (zh) * 2005-09-22 2010-01-06 安捷尔射频公司 铁电薄膜装置及其制造方法
KR100722128B1 (ko) * 2005-12-28 2007-05-25 동부일렉트로닉스 주식회사 반도체 소자 제조방법
US7572698B2 (en) * 2006-05-30 2009-08-11 Texas Instruments Incorporated Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean
JP5109395B2 (ja) * 2007-02-14 2012-12-26 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US8269204B2 (en) * 2009-07-02 2012-09-18 Actel Corporation Back to back resistive random access memory cells
US20110297088A1 (en) * 2010-06-04 2011-12-08 Texas Instruments Incorporated Thin edge carrier ring
CN103087718B (zh) * 2013-01-16 2014-12-31 四川大学 湿法刻蚀镍酸镧薄膜和铁电薄膜/镍酸镧复合薄膜的腐蚀液及其制备方法
US9041919B2 (en) 2013-02-18 2015-05-26 Globalfoundries Inc. Infrared-based metrology for detection of stress and defects around through silicon vias
JP2016184677A (ja) * 2015-03-26 2016-10-20 株式会社ユーテック 強誘電体膜の製造方法
JP2017098367A (ja) * 2015-11-20 2017-06-01 東京エレクトロン株式会社 基板処理方法

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US5046043A (en) 1987-10-08 1991-09-03 National Semiconductor Corporation Ferroelectric capacitor and memory cell including barrier and isolation layers
US5258093A (en) * 1992-12-21 1993-11-02 Motorola, Inc. Procss for fabricating a ferroelectric capacitor in a semiconductor device
US6051858A (en) 1996-07-26 2000-04-18 Symetrix Corporation Ferroelectric/high dielectric constant integrated circuit and method of fabricating same
US6114254A (en) * 1996-10-15 2000-09-05 Micron Technology, Inc. Method for removing contaminants from a semiconductor wafer
US5807774A (en) 1996-12-06 1998-09-15 Sharp Kabushiki Kaisha Simple method of fabricating ferroelectric capacitors
US5773314A (en) 1997-04-25 1998-06-30 Motorola, Inc. Plug protection process for use in the manufacture of embedded dynamic random access memory (DRAM) cells
JPH10340893A (ja) * 1997-06-09 1998-12-22 Sony Corp 電子薄膜材料のエッチング方法
US6143476A (en) 1997-12-12 2000-11-07 Applied Materials Inc Method for high temperature etching of patterned layers using an organic mask stack
US6225156B1 (en) * 1998-04-17 2001-05-01 Symetrix Corporation Ferroelectric integrated circuit having low sensitivity to hydrogen exposure and method for fabricating same
US6174735B1 (en) 1998-10-23 2001-01-16 Ramtron International Corporation Method of manufacturing ferroelectric memory device useful for preventing hydrogen line degradation
US6140672A (en) * 1999-03-05 2000-10-31 Symetrix Corporation Ferroelectric field effect transistor having a gate electrode being electrically connected to the bottom electrode of a ferroelectric capacitor
JP3395696B2 (ja) * 1999-03-15 2003-04-14 日本電気株式会社 ウェハ処理装置およびウェハ処理方法
JP2000315670A (ja) * 1999-04-30 2000-11-14 Nec Corp 半導体基板の洗浄方法
KR100329759B1 (ko) * 1999-06-30 2002-03-25 박종섭 강유전체 캐패시터 형성 방법
JP2001068463A (ja) * 1999-08-31 2001-03-16 Hitachi Ltd 半導体集積回路装置の量産方法
US6261892B1 (en) * 1999-12-31 2001-07-17 Texas Instruments Incorporated Intra-chip AC isolation of RF passive components
JP2002231676A (ja) * 2001-01-30 2002-08-16 Toshiba Corp ウェハ洗浄方法及びウェハ洗浄装置
JP2002353182A (ja) * 2001-05-25 2002-12-06 Mitsubishi Electric Corp 半導体装置の洗浄方法および洗浄装置、ならびに半導体装置の製造方法

Also Published As

Publication number Publication date
KR20030014627A (ko) 2003-02-19
JP2003158115A (ja) 2003-05-30
KR100880109B1 (ko) 2009-01-21
JP4285954B2 (ja) 2009-06-24
US6709875B2 (en) 2004-03-23
US20030036209A1 (en) 2003-02-20

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