DE10216080A1 - Halbleiter-Bauelement - Google Patents
Halbleiter-BauelementInfo
- Publication number
- DE10216080A1 DE10216080A1 DE10216080A DE10216080A DE10216080A1 DE 10216080 A1 DE10216080 A1 DE 10216080A1 DE 10216080 A DE10216080 A DE 10216080A DE 10216080 A DE10216080 A DE 10216080A DE 10216080 A1 DE10216080 A1 DE 10216080A1
- Authority
- DE
- Germany
- Prior art keywords
- region
- pad
- electrically connected
- gnd
- vcc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 title claims abstract description 100
- 239000002184 metal Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims description 55
- 230000001681 protective effect Effects 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 12
- 230000015556 catabolic process Effects 0.000 claims description 8
- 230000035939 shock Effects 0.000 claims description 7
- 230000008901 benefit Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 description 17
- 230000008569 process Effects 0.000 description 17
- 238000010586 diagram Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 238000002161 passivation Methods 0.000 description 5
- 238000004364 calculation method Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 230000005012 migration Effects 0.000 description 3
- 238000013508 migration Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12035—Zener diode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12036—PN diode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12043—Photo diode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Gemäß der Erfindung wird der Niederimpedanzbereich durch den CMOS- Fabrikationsprozeß hergestellt, und dies beseitigt die Notwendigkeit eines speziel len Ionenimplantationsprozesses, wie er zum Herstellen eines Bipolartransistors erforderlich ist. Die integrierte CMOS-Schaltung kann also einschließlich der Verpolungsschutzschaltung zu niedrigen Kosten hergestellt werden.
Claims (15)
einen Niederimpedanzbereich (3), der durch einen CMOS-Herstel lungsprozeß gebildet ist und dazu ausgebildet ist, daß seine Impe danz sehr niedrig in einem Stromkreis wird, bei dem das Erd- oder Massepotential an die Vcc-Anschlußfläche (1) und die Speisespan nung an die GND-Anschlußfläche (2) angelegt sind;
einen ersten metallenen Leiter (11), der den Niederimpedanzbereich (3) elektrisch mit der Vcc-Anschlußfläche (1) verbindet; und
einen zweiten metallischen Leiter (21), der den Niederimpedanz bereich (3) elektrisch mit der GND-Anschlußfläche (2) verbindet.
einen p-MOS-Transistor (30), mit einem Quellenbereich (301), einem Steuerbereich (302) und einem n-Topfbereich (305), die elektrisch mit der Vcc-Anschlußfläche (1) verbunden sind, und mit einem Abflußbereich (303), der elektrisch mit der GND-Anschlußfläche (2) verbunden ist; und
einen Schutzring (31), der aus einem p-leitenden Halbleiter besteht, um den MOS-Transistor (30) herum liegt und elektrisch mit der GND- Anschlußfläche (2) verbunden ist.
einen p-MOS-Transistor (30) mit einem Quellenbereich (301), einer Steuerelektrode (302) und einem n-leitenden Halbleitersubstrat, die elektrisch mit der Vcc-Anschlußfläche (1) verbunden sind, und mit einem Abflußbereich (303), der elektrisch mit der GND-Anschlußflä che (2) verbunden ist; und
einen Schutzring (31), der aus einem p-leitenden Halbleiter besteht, um den MOS-Transistor (30) herum liegt und elektrisch mit der GND- Anschlußfläche (2) verbunden ist.
einen p-MOS-Transistor (30) mit einem Quellenbereich (301) und einem n-Topfbereich (305), die elektrisch mit der Vcc-Anschlußfläche (1) verbunden sind, und mit einer Steuerelektrode (302) und einer Abflußelektrode (303), die elektrisch mit der GND-Anschlußfläche (2) verbunden sind; und
einen Schutzring (31), der aus einem p-leitenden Halbleiter besteht, um den MOS-Transistor (30) herum liegt und elektrisch mit der GND- Anschlußfläche (2) verbunden ist.
einen p-MOS-Transistor (30) mit einem Quellenbereich (301) und einem n-leitenden Halbleitersubstrat, die elektrisch mit der Vcc- Anschlußfläche (1) verbunden sind, und mit einer Steuerelektrode (302) und einem Abflußbereich (303), die elektrisch mit der GND- Anschlußfläche (2) verbunden sind; und
einen Schutzring (31), der aus einem p-leitenden Halbleiter besteht, um den MOS-Transistor (30) herum liegt und elektrisch mit der GND- Anschlußfläche (2) verbunden ist.
eine Zenerdiode (32) mit einem Kathodenbereich, der elektrisch mit der Vcc-Anschlußfläche (1) verbunden ist, und einem Anodenbereich, der elektrisch mit der GND-Anschlußfläche (2) verbunden ist; und
einen Schutzring (31), der aus einem p-leitenden Halbleiter besteht, um die Zenerdiode (32) herum liegt und elektrisch mit der GND- Anschlußfläche (2) verbunden ist.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001-114328 | 2001-04-12 | ||
JP2001114328A JP2002313947A (ja) | 2001-04-12 | 2001-04-12 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE10216080A1 true DE10216080A1 (de) | 2002-10-17 |
DE10216080B4 DE10216080B4 (de) | 2007-09-13 |
Family
ID=18965416
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10216080A Expired - Fee Related DE10216080B4 (de) | 2001-04-12 | 2002-04-11 | Halbleiter-Bauelement mit Niederimpedanzbereich zum Verpolungsschutz |
Country Status (4)
Country | Link |
---|---|
US (1) | US6680512B2 (de) |
JP (1) | JP2002313947A (de) |
KR (1) | KR100817972B1 (de) |
DE (1) | DE10216080B4 (de) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002313947A (ja) * | 2001-04-12 | 2002-10-25 | Fuji Electric Co Ltd | 半導体装置 |
US20030123299A1 (en) * | 2002-01-02 | 2003-07-03 | Annavajjhala Ravi P. | Protection circuit |
US6798022B1 (en) * | 2003-03-11 | 2004-09-28 | Oki Electric Industry Co., Ltd. | Semiconductor device with improved protection from electrostatic discharge |
JP2007294613A (ja) | 2006-04-24 | 2007-11-08 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP5108250B2 (ja) | 2006-04-24 | 2012-12-26 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置及びその製造方法 |
JP5732763B2 (ja) * | 2010-07-20 | 2015-06-10 | 大日本印刷株式会社 | Esd保護素子を備える半導体装置およびesd保護素子を備える半導体装置の製造方法 |
JP7024277B2 (ja) | 2017-09-20 | 2022-02-24 | 株式会社デンソー | 半導体装置 |
JP6948893B2 (ja) * | 2017-09-21 | 2021-10-13 | 新日本無線株式会社 | 保護回路 |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5986252A (ja) * | 1982-11-09 | 1984-05-18 | Seiko Epson Corp | 半導体集積回路 |
JPS60113961A (ja) * | 1983-11-25 | 1985-06-20 | Hitachi Ltd | 半導体集積回路装置 |
JPS6195567A (ja) * | 1984-10-17 | 1986-05-14 | Hitachi Ltd | 半導体集積回路装置 |
JPS63301558A (ja) * | 1987-01-28 | 1988-12-08 | Toshiba Corp | 半導体集積回路装置 |
JPH0616558B2 (ja) * | 1987-01-28 | 1994-03-02 | 三菱電機株式会社 | 半導体装置の入力保護装置 |
US4819047A (en) * | 1987-05-15 | 1989-04-04 | Advanced Micro Devices, Inc. | Protection system for CMOS integrated circuits |
JPH021172A (ja) * | 1988-06-08 | 1990-01-05 | Nec Corp | 半導体集積回路装置 |
JPH04145658A (ja) * | 1990-10-08 | 1992-05-19 | Nec Ic Microcomput Syst Ltd | 半導体集積回路 |
US5237395A (en) * | 1991-05-28 | 1993-08-17 | Western Digital Corporation | Power rail ESD protection circuit |
US5428498A (en) * | 1992-09-28 | 1995-06-27 | Xerox Corporation | Office environment level electrostatic discharge protection |
JP3485655B2 (ja) * | 1994-12-14 | 2004-01-13 | 株式会社ルネサステクノロジ | 複合型mosfet |
US5610790A (en) * | 1995-01-20 | 1997-03-11 | Xilinx, Inc. | Method and structure for providing ESD protection for silicon on insulator integrated circuits |
DE19501985A1 (de) * | 1995-01-24 | 1996-07-25 | Teves Gmbh Alfred | Verpolschutz |
JPH0917947A (ja) * | 1995-06-30 | 1997-01-17 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US5726844A (en) * | 1996-04-01 | 1998-03-10 | Motorola, Inc. | Protection circuit and a circuit for a semiconductor-on-insulator device |
JPH09331072A (ja) * | 1996-06-12 | 1997-12-22 | Toshiba Corp | 半導体装置及びその製造方法 |
JPH1079472A (ja) * | 1996-09-05 | 1998-03-24 | Mitsubishi Electric Corp | 半導体集積回路 |
JPH10125802A (ja) * | 1996-10-16 | 1998-05-15 | Sanken Electric Co Ltd | 保護素子を含む半導体回路装置 |
JPH10223773A (ja) * | 1997-02-05 | 1998-08-21 | Matsushita Electric Ind Co Ltd | 電源間保護回路 |
JPH10270640A (ja) * | 1997-03-26 | 1998-10-09 | Mitsubishi Electric Corp | 半導体集積回路装置 |
DE19733707A1 (de) * | 1997-08-04 | 1999-02-11 | Siemens Ag | Schutzschaltung |
JP3853968B2 (ja) * | 1998-03-31 | 2006-12-06 | 沖電気工業株式会社 | 半導体装置 |
JP3141865B2 (ja) | 1998-12-28 | 2001-03-07 | セイコーエプソン株式会社 | 半導体集積装置 |
JP2001007349A (ja) * | 1999-06-18 | 2001-01-12 | Nec Corp | 低電圧用ツェナーダイオード |
JP2002313947A (ja) * | 2001-04-12 | 2002-10-25 | Fuji Electric Co Ltd | 半導体装置 |
-
2001
- 2001-04-12 JP JP2001114328A patent/JP2002313947A/ja active Pending
-
2002
- 2002-04-11 DE DE10216080A patent/DE10216080B4/de not_active Expired - Fee Related
- 2002-04-12 US US10/121,447 patent/US6680512B2/en not_active Expired - Lifetime
- 2002-04-12 KR KR1020020019993A patent/KR100817972B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US20020175425A1 (en) | 2002-11-28 |
JP2002313947A (ja) | 2002-10-25 |
KR20020079603A (ko) | 2002-10-19 |
KR100817972B1 (ko) | 2008-03-31 |
DE10216080B4 (de) | 2007-09-13 |
US6680512B2 (en) | 2004-01-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8110 | Request for examination paragraph 44 | ||
8125 | Change of the main classification |
Ipc: H01L 23/60 AFI20051017BHDE |
|
8364 | No opposition during term of opposition | ||
8320 | Willingness to grant licences declared (paragraph 23) | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: FUJI ELECTRIC SYSTEMS CO., LTD., TOKYO/TOKIO, JP |
|
R081 | Change of applicant/patentee |
Owner name: FUJI ELECTRIC CO., LTD., JP Free format text: FORMER OWNER: FUJI ELECTRIC SYSTEMS CO., LTD., TOKYO/TOKIO, JP Effective date: 20110826 Owner name: FUJI ELECTRIC CO., LTD., KAWASAKI-SHI, JP Free format text: FORMER OWNER: FUJI ELECTRIC SYSTEMS CO., LTD., TOKYO/TOKIO, JP Effective date: 20110826 |
|
R082 | Change of representative |
Representative=s name: BOEHMERT & BOEHMERT, DE Effective date: 20110826 Representative=s name: BOEHMERT & BOEHMERT ANWALTSPARTNERSCHAFT MBB -, DE Effective date: 20110826 |
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R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |