DE102018128329A1 - Speichervorrichtung und Verfahren zum Betreiben derselben - Google Patents

Speichervorrichtung und Verfahren zum Betreiben derselben Download PDF

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Publication number
DE102018128329A1
DE102018128329A1 DE102018128329.6A DE102018128329A DE102018128329A1 DE 102018128329 A1 DE102018128329 A1 DE 102018128329A1 DE 102018128329 A DE102018128329 A DE 102018128329A DE 102018128329 A1 DE102018128329 A1 DE 102018128329A1
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DE
Germany
Prior art keywords
memory cell
memory
read
state
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE102018128329.6A
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German (de)
English (en)
Inventor
Chea Ouk Lim
Tae Hui Na
Jung Sunwoo
Yong Jun Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE102018128329A1 publication Critical patent/DE102018128329A1/de
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0033—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0097—Erasing, e.g. resetting, circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0047—Read destroying or disturbing the data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0057—Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/15—Current-voltage curve
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
DE102018128329.6A 2017-12-05 2018-11-13 Speichervorrichtung und Verfahren zum Betreiben derselben Pending DE102018128329A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020170165843A KR102401183B1 (ko) 2017-12-05 2017-12-05 메모리 장치 및 그 동작 방법
KR10-2017-0165843 2017-12-05

Publications (1)

Publication Number Publication Date
DE102018128329A1 true DE102018128329A1 (de) 2019-06-06

Family

ID=66548389

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102018128329.6A Pending DE102018128329A1 (de) 2017-12-05 2018-11-13 Speichervorrichtung und Verfahren zum Betreiben derselben

Country Status (5)

Country Link
US (1) US10580488B2 (https=)
JP (1) JP7097792B2 (https=)
KR (1) KR102401183B1 (https=)
CN (1) CN109872751B (https=)
DE (1) DE102018128329A1 (https=)

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KR102701814B1 (ko) * 2019-02-27 2024-09-03 에스케이하이닉스 주식회사 효율적인 리드 동작을 수행하는 비휘발성 메모리 장치 및 이를 이용하는 시스템
US10867671B1 (en) 2019-07-02 2020-12-15 Micron Technology, Inc. Techniques for applying multiple voltage pulses to select a memory cell
US10942655B2 (en) * 2019-07-09 2021-03-09 Seagate Technology Llc Mitigating data errors in a storage device
JP2023025932A (ja) * 2021-08-11 2023-02-24 ソニーセミコンダクタソリューションズ株式会社 メモリモジュール
FR3155310B1 (fr) * 2023-11-10 2026-01-02 Commissariat Energie Atomique Estimation de l’état initial d’un élément résistif

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JP4189395B2 (ja) * 2004-07-28 2008-12-03 シャープ株式会社 不揮発性半導体記憶装置及び読み出し方法
KR100610014B1 (ko) * 2004-09-06 2006-08-09 삼성전자주식회사 리키지 전류 보상 가능한 반도체 메모리 장치
US7193898B2 (en) * 2005-06-20 2007-03-20 Sandisk Corporation Compensation currents in non-volatile memory read operations
US7679980B2 (en) 2006-11-21 2010-03-16 Qimonda North America Corp. Resistive memory including selective refresh operation
US7990761B2 (en) 2008-03-31 2011-08-02 Ovonyx, Inc. Immunity of phase change material to disturb in the amorphous phase
KR20090126587A (ko) * 2008-06-04 2009-12-09 삼성전자주식회사 상 변화 메모리 장치 및 그것의 읽기 방법
US8406033B2 (en) 2009-06-22 2013-03-26 Macronix International Co., Ltd. Memory device and method for sensing and fixing margin cells
KR20110107190A (ko) 2010-03-24 2011-09-30 삼성전자주식회사 저항성 메모리의 마모 셀 관리 방법 및 장치
US8467237B2 (en) * 2010-10-15 2013-06-18 Micron Technology, Inc. Read distribution management for phase change memory
US20130336047A1 (en) 2012-04-24 2013-12-19 Being Advanced Memory Corporation Cell Refresh in Phase Change Memory
US8885388B2 (en) 2012-10-24 2014-11-11 Marvell World Trade Ltd. Apparatus and method for reforming resistive memory cells
KR102023358B1 (ko) * 2012-10-29 2019-09-20 삼성전자 주식회사 저항체를 이용한 비휘발성 메모리 장치 및 그 구동 방법
KR20140090879A (ko) * 2013-01-10 2014-07-18 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 읽기 방법
US9165683B2 (en) 2013-09-23 2015-10-20 Sandisk Technologies Inc. Multi-word line erratic programming detection
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Also Published As

Publication number Publication date
US10580488B2 (en) 2020-03-03
CN109872751A (zh) 2019-06-11
JP7097792B2 (ja) 2022-07-08
KR20190066271A (ko) 2019-06-13
KR102401183B1 (ko) 2022-05-24
US20190172531A1 (en) 2019-06-06
CN109872751B (zh) 2024-09-10
JP2019102117A (ja) 2019-06-24

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