DE102007032290B8 - Transistor, integrierte Schaltung und Verfahren zur Herstellung einer integrierten Schaltung - Google Patents

Transistor, integrierte Schaltung und Verfahren zur Herstellung einer integrierten Schaltung Download PDF

Info

Publication number
DE102007032290B8
DE102007032290B8 DE102007032290A DE102007032290A DE102007032290B8 DE 102007032290 B8 DE102007032290 B8 DE 102007032290B8 DE 102007032290 A DE102007032290 A DE 102007032290A DE 102007032290 A DE102007032290 A DE 102007032290A DE 102007032290 B8 DE102007032290 B8 DE 102007032290B8
Authority
DE
Germany
Prior art keywords
integrated circuit
transistor
manufacturing
integrated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE102007032290A
Other languages
English (en)
Other versions
DE102007032290B3 (de
Inventor
Andrew Dr. Graham
Jessica Hartwich
Arnd Scholz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Polaris Innovations Ltd
Original Assignee
Qimonda AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qimonda AG filed Critical Qimonda AG
Publication of DE102007032290B3 publication Critical patent/DE102007032290B3/de
Application granted granted Critical
Publication of DE102007032290B8 publication Critical patent/DE102007032290B8/de
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Non-Volatile Memory (AREA)
  • Thin Film Transistor (AREA)
DE102007032290A 2007-05-30 2007-07-11 Transistor, integrierte Schaltung und Verfahren zur Herstellung einer integrierten Schaltung Expired - Fee Related DE102007032290B8 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/755,141 US20080296674A1 (en) 2007-05-30 2007-05-30 Transistor, integrated circuit and method of forming an integrated circuit
US11/755,141 2007-05-30

Publications (2)

Publication Number Publication Date
DE102007032290B3 DE102007032290B3 (de) 2008-10-16
DE102007032290B8 true DE102007032290B8 (de) 2009-02-05

Family

ID=40087153

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102007032290A Expired - Fee Related DE102007032290B8 (de) 2007-05-30 2007-07-11 Transistor, integrierte Schaltung und Verfahren zur Herstellung einer integrierten Schaltung

Country Status (5)

Country Link
US (1) US20080296674A1 (de)
JP (1) JP2008300843A (de)
KR (1) KR20080106116A (de)
DE (1) DE102007032290B8 (de)
TW (1) TW200847425A (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7977798B2 (en) * 2007-07-26 2011-07-12 Infineon Technologies Ag Integrated circuit having a semiconductor substrate with a barrier layer
US7948027B1 (en) * 2009-12-10 2011-05-24 Nanya Technology Corp. Embedded bit line structure, field effect transistor structure with the same and method of fabricating the same
JP5507287B2 (ja) * 2010-02-22 2014-05-28 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
JP5159816B2 (ja) * 2010-03-23 2013-03-13 株式会社東芝 半導体記憶装置
JP2011243948A (ja) * 2010-04-22 2011-12-01 Elpida Memory Inc 半導体装置及びその製造方法
JP2011233582A (ja) * 2010-04-23 2011-11-17 Elpida Memory Inc 半導体装置
JP2012084694A (ja) * 2010-10-12 2012-04-26 Elpida Memory Inc 半導体装置
JP2012084738A (ja) * 2010-10-13 2012-04-26 Elpida Memory Inc 半導体装置及びその製造方法、並びにデータ処理システム
JP5697952B2 (ja) 2010-11-05 2015-04-08 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置、半導体装置の製造方法およびデータ処理システム
TWI455314B (zh) 2011-01-03 2014-10-01 Inotera Memories Inc 具有浮置體的記憶體結構及其製法
JP2012174790A (ja) * 2011-02-18 2012-09-10 Elpida Memory Inc 半導体装置及びその製造方法
US20130001188A1 (en) * 2011-06-30 2013-01-03 Seagate Technology, Llc Method to protect magnetic bits during planarization
JP2013030698A (ja) 2011-07-29 2013-02-07 Elpida Memory Inc 半導体装置の製造方法
KR101920626B1 (ko) 2011-08-16 2018-11-22 삼성전자주식회사 정보 저장 장치 및 그 제조 방법
KR101847628B1 (ko) * 2011-09-28 2018-05-25 삼성전자주식회사 금속함유 도전 라인을 포함하는 반도체 소자 및 그 제조 방법
KR20130110733A (ko) * 2012-03-30 2013-10-10 삼성전자주식회사 반도체 장치의 제조 방법 및 이에 의해 형성된 반도체 장치
JP2014063776A (ja) * 2012-09-19 2014-04-10 Toshiba Corp 電界効果トランジスタ
KR102162733B1 (ko) * 2014-05-29 2020-10-07 에스케이하이닉스 주식회사 듀얼일함수 매립게이트형 트랜지스터 및 그 제조 방법, 그를 구비한 전자장치
JP6455846B2 (ja) * 2014-08-29 2019-01-23 インテル・コーポレーション 複数の金属層および関連する構成を有する高アスペクト比の細長い構造を充填するための技法
US9159829B1 (en) * 2014-10-07 2015-10-13 Micron Technology, Inc. Recessed transistors containing ferroelectric material
CN109119477B (zh) * 2018-08-28 2021-11-05 上海华虹宏力半导体制造有限公司 沟槽栅mosfet及其制造方法
WO2021095113A1 (ja) * 2019-11-12 2021-05-20 三菱電機株式会社 炭化珪素半導体装置、電力変換装置および炭化珪素半導体装置の製造方法
KR20210143046A (ko) 2020-05-19 2021-11-26 삼성전자주식회사 산화물 반도체 트랜지스터
KR20220064231A (ko) 2020-11-11 2022-05-18 삼성전자주식회사 전계 효과 트랜지스터, 전계 효과 트랜지스터 어레이 구조 및 전계 효과 트랜지스터 제조 방법
KR20220077741A (ko) * 2020-12-02 2022-06-09 삼성전자주식회사 반도체 메모리 소자
US20220271131A1 (en) * 2021-02-23 2022-08-25 Changxin Memory Technologies, Inc. Semiconductor structure and method for forming same
US20230197771A1 (en) * 2021-12-16 2023-06-22 Nanya Technology Corporation Memory device having word lines with reduced leakage

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020037615A1 (en) * 2000-09-27 2002-03-28 Kouji Matsuo Semiconductor device and method of fabricating the same
DE10345393A1 (de) * 2003-09-30 2005-05-19 Infineon Technologies Ag Verfahren zur Abscheidung eines leitfähigen Materials auf einem Substrat und Halbleiterkontaktvorrichtung
DE102004049452A1 (de) * 2004-10-11 2006-04-20 Infineon Technologies Ag Mikroelektronisches Halbleiterbauelement und Verfahren zum Herstellen eines mikroelektronischen Halbleiterbauelements

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19651108C2 (de) * 1996-04-11 2000-11-23 Mitsubishi Electric Corp Halbleitereinrichtung des Gategrabentyps mit hoher Durchbruchsspannung und ihr Herstellungsverfahren
JP2003158201A (ja) * 2001-11-20 2003-05-30 Sony Corp 半導体装置およびその製造方法
EP1704595A2 (de) * 2003-12-19 2006-09-27 Infineon Technologies AG Steg-feldeffekttransistor-speicherzellen-anordnung und herstellungsverfahren
DE102004006544B3 (de) * 2004-02-10 2005-09-08 Infineon Technologies Ag Verfahren zur Abscheidung eines leitfähigen Kohlenstoffmaterials auf einem Halbleiter zur Ausbildung eines Schottky-Kontaktes und Halbleiterkontaktvorrichtung
DE102004006505B4 (de) * 2004-02-10 2006-01-26 Infineon Technologies Ag Charge-Trapping-Speicherzelle und Herstellungsverfahren
US7365382B2 (en) * 2005-02-28 2008-04-29 Infineon Technologies Ag Semiconductor memory having charge trapping memory cells and fabrication method thereof
AT504998A2 (de) * 2005-04-06 2008-09-15 Fairchild Semiconductor Trenched-gate-feldeffekttransistoren und verfahren zum bilden derselben
JP2006339476A (ja) * 2005-06-03 2006-12-14 Elpida Memory Inc 半導体装置及びその製造方法
US7867851B2 (en) * 2005-08-30 2011-01-11 Micron Technology, Inc. Methods of forming field effect transistors on substrates
US7687342B2 (en) * 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US20070253233A1 (en) * 2006-03-30 2007-11-01 Torsten Mueller Semiconductor memory device and method of production

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020037615A1 (en) * 2000-09-27 2002-03-28 Kouji Matsuo Semiconductor device and method of fabricating the same
DE10345393A1 (de) * 2003-09-30 2005-05-19 Infineon Technologies Ag Verfahren zur Abscheidung eines leitfähigen Materials auf einem Substrat und Halbleiterkontaktvorrichtung
DE102004049452A1 (de) * 2004-10-11 2006-04-20 Infineon Technologies Ag Mikroelektronisches Halbleiterbauelement und Verfahren zum Herstellen eines mikroelektronischen Halbleiterbauelements

Also Published As

Publication number Publication date
DE102007032290B3 (de) 2008-10-16
US20080296674A1 (en) 2008-12-04
JP2008300843A (ja) 2008-12-11
TW200847425A (en) 2008-12-01
KR20080106116A (ko) 2008-12-04

Similar Documents

Publication Publication Date Title
DE102007032290B8 (de) Transistor, integrierte Schaltung und Verfahren zur Herstellung einer integrierten Schaltung
DE102006001792B8 (de) Halbleitermodul mit Halbleiterchipstapel und Verfahren zur Herstellung desselben
DE112009000756A5 (de) Verfahren zur Herstellung eines elektronischen Bauelements und elektronisches BAuelement
DE112007002801T8 (de) Abschirmungsleiter und Verfahren zur Herstellung des Abschirmungsleiters
DE502005001625D1 (de) Beschichtetes Bauteil und Verfahren zur Herstellung
ATE497955T1 (de) Verfahren zur herstellung von ethylenoxid und ethylenglykol
DE602007010616D1 (de) Verfahren zur herstellung einer organischen elektrovorrichtung
DE602006021081D1 (de) Integrierte Halbleitervorrichtung und Verfahren zur Herstellung abgeschirmter Verbindung
ATE455105T1 (de) Verfahren zur herstellung von difluormethylpyrazolylcarboxylaten
DE602005003730D1 (de) Nichthaftende Vorrichtungen zur Maskierung und Verfahren zur Herstellung derselben
HK1118379A1 (en) Semiconductor component and method of manufacture
DE502006006395D1 (de) Elektrisches Gerät und Verfahren zur Herstellung eines elektrischen Geräts
DE112006003129A5 (de) Hohlwelle und Verfahren zur Herstellung
DE102009044474A8 (de) Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterbauelements
DE112007001034T8 (de) Temperatursonde und Verfahren zur Herstellung derselben
DE602006000373D1 (de) Anschlusselement , dazugehöriger Verbinder und Verfahren zur Herstellung
ATE480531T1 (de) Verfahren zur herstellung von benzopyran-2- olderivaten
DE112007003777A5 (de) Leiteranordnung und Verfahren zur Herstellung derselben
HK1131696A1 (en) Semiconductor component and method of manufacture
HK1125739A1 (en) Semiconductor component and method of manufacture
DE502006008141D1 (de) Halbleitersubstrat und Verfahren zur Herstellung
DE602006000223D1 (de) Elektronisches Gerät und Verfahren zur Herstellung das selbe
DE602006005052D1 (de) Verfahren zur herstellung einer im wesentlichen schalenförmigen komponente
DE602006002930D1 (de) Kautschukzusammensetzung und Verfahren zur Herstellung
DE602007009955D1 (de) Schaltung und verfahren zur lärmminderung

Legal Events

Date Code Title Description
8396 Reprint of erroneous front page
8364 No opposition during term of opposition
R081 Change of applicant/patentee

Owner name: INFINEON TECHNOLOGIES AG, DE

Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE

Owner name: POLARIS INNOVATIONS LTD., IE

Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE

R081 Change of applicant/patentee

Owner name: POLARIS INNOVATIONS LTD., IE

Free format text: FORMER OWNER: INFINEON TECHNOLOGIES AG, 85579 NEUBIBERG, DE

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee