DE102006032958B4 - Speicherzellenarray mit vergrabener Bitleitung mit reduziertem Widerstand und Herstellungsverfahren hierfür - Google Patents

Speicherzellenarray mit vergrabener Bitleitung mit reduziertem Widerstand und Herstellungsverfahren hierfür Download PDF

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Publication number
DE102006032958B4
DE102006032958B4 DE102006032958A DE102006032958A DE102006032958B4 DE 102006032958 B4 DE102006032958 B4 DE 102006032958B4 DE 102006032958 A DE102006032958 A DE 102006032958A DE 102006032958 A DE102006032958 A DE 102006032958A DE 102006032958 B4 DE102006032958 B4 DE 102006032958B4
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Germany
Prior art keywords
region
layer
conductive
semiconductor substrate
semiconductor region
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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DE102006032958A
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German (de)
English (en)
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DE102006032958A1 (de
Inventor
Dr. Kleint Christoph
Dr. Fitz Clemens
Ulrike Bewersdorff-Sarlette
Dr. Ludwig Christoph
David Pritchard
Torsten Müller
Hocine Boubekeur
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Polaris Innovations Ltd
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Qimonda AG
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Publication of DE102006032958A1 publication Critical patent/DE102006032958A1/de
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Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
DE102006032958A 2006-06-30 2006-07-17 Speicherzellenarray mit vergrabener Bitleitung mit reduziertem Widerstand und Herstellungsverfahren hierfür Expired - Fee Related DE102006032958B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/478,313 2006-06-30
US11/478,313 US7678654B2 (en) 2006-06-30 2006-06-30 Buried bitline with reduced resistance

Publications (2)

Publication Number Publication Date
DE102006032958A1 DE102006032958A1 (de) 2008-01-17
DE102006032958B4 true DE102006032958B4 (de) 2013-04-11

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE102006032958A Expired - Fee Related DE102006032958B4 (de) 2006-06-30 2006-07-17 Speicherzellenarray mit vergrabener Bitleitung mit reduziertem Widerstand und Herstellungsverfahren hierfür

Country Status (3)

Country Link
US (1) US7678654B2 (pt-PT)
CN (1) CN101106122A (pt-PT)
DE (1) DE102006032958B4 (pt-PT)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110101876A (ko) * 2010-03-10 2011-09-16 삼성전자주식회사 매립 비트 라인을 갖는 반도체 장치 및 반도체 장치의 제조 방법
US9006827B2 (en) * 2011-11-09 2015-04-14 International Business Machines Corporation Radiation hardened memory cell and design structures
CN109037225B (zh) * 2018-09-19 2023-09-12 长江存储科技有限责任公司 存储器结构
US20220246752A1 (en) * 2019-07-29 2022-08-04 Enkris Semiconductor, Inc. Semiconductor Structure And Manufacturing Method For The Same
CN117457709A (zh) * 2022-07-18 2024-01-26 无锡华润华晶微电子有限公司 一种半导体器件结构及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10110150A1 (de) * 2001-03-02 2002-09-19 Infineon Technologies Ag Verfahren zum Herstellen von metallischen Bitleitungen für Speicherzellenarrays, Verfahren zum Herstellen von Speicherzellenarrays und Speicherzellenarray
US6531361B1 (en) * 2002-04-25 2003-03-11 Macronix International Co., Ltd. Fabrication method for a memory device
US20030119314A1 (en) * 2001-12-20 2003-06-26 Jusuke Ogura Monos device having buried metal silicide bit line
US6653227B1 (en) * 2000-08-31 2003-11-25 Chartered Semiconductor Manufacturing Ltd. Method of cobalt silicidation using an oxide-Titanium interlayer
US6987048B1 (en) * 2003-08-06 2006-01-17 Advanced Micro Devices, Inc. Memory device having silicided bitlines and method of forming the same
DE10328577B4 (de) * 2002-07-22 2006-01-19 Infineon Technologies Ag Nichtflüchtige Speicherzelle und Herstellungsverfahren

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7125763B1 (en) * 2000-09-29 2006-10-24 Spansion Llc Silicided buried bitline process for a non-volatile memory cell
US20020182829A1 (en) * 2001-05-31 2002-12-05 Chia-Hsing Chen Method for forming nitride read only memory with indium pocket region
EP1313149A1 (en) * 2001-11-14 2003-05-21 STMicroelectronics S.r.l. Process for fabricating a dual charge storage location memory cell
DE10250872B4 (de) * 2002-10-31 2005-04-21 Infineon Technologies Ag Verfahren zur Herstellung einer Halbleiterstruktur mit mehreren Gate-Stapeln
TW594945B (en) * 2003-09-05 2004-06-21 Powerchip Semiconductor Corp Flash memory cell and manufacturing method thereof
US6958272B2 (en) * 2004-01-12 2005-10-25 Advanced Micro Devices, Inc. Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell
US7315474B2 (en) * 2005-01-03 2008-01-01 Macronix International Co., Ltd Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
US20060198189A1 (en) * 2005-01-03 2006-09-07 Macronix International Co., Ltd. Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
US7642585B2 (en) * 2005-01-03 2010-01-05 Macronix International Co., Ltd. Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
US8264028B2 (en) * 2005-01-03 2012-09-11 Macronix International Co., Ltd. Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
US7414277B1 (en) * 2005-04-22 2008-08-19 Spansion, Llc Memory cell having combination raised source and drain and method of fabricating same
CN101167180A (zh) * 2005-04-27 2008-04-23 斯班逊有限公司 半导体装置及其制造方法
US20060281255A1 (en) * 2005-06-14 2006-12-14 Chun-Jen Chiu Method for forming a sealed storage non-volative multiple-bit memory cell
US20070212833A1 (en) * 2006-03-13 2007-09-13 Macronix International Co., Ltd. Methods for making a nonvolatile memory device comprising a shunt silicon layer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6653227B1 (en) * 2000-08-31 2003-11-25 Chartered Semiconductor Manufacturing Ltd. Method of cobalt silicidation using an oxide-Titanium interlayer
DE10110150A1 (de) * 2001-03-02 2002-09-19 Infineon Technologies Ag Verfahren zum Herstellen von metallischen Bitleitungen für Speicherzellenarrays, Verfahren zum Herstellen von Speicherzellenarrays und Speicherzellenarray
US20030119314A1 (en) * 2001-12-20 2003-06-26 Jusuke Ogura Monos device having buried metal silicide bit line
US6531361B1 (en) * 2002-04-25 2003-03-11 Macronix International Co., Ltd. Fabrication method for a memory device
DE10328577B4 (de) * 2002-07-22 2006-01-19 Infineon Technologies Ag Nichtflüchtige Speicherzelle und Herstellungsverfahren
US6987048B1 (en) * 2003-08-06 2006-01-17 Advanced Micro Devices, Inc. Memory device having silicided bitlines and method of forming the same

Also Published As

Publication number Publication date
DE102006032958A1 (de) 2008-01-17
US20080002466A1 (en) 2008-01-03
CN101106122A (zh) 2008-01-16
US7678654B2 (en) 2010-03-16

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OP8 Request for examination as to paragraph 44 patent law
R018 Grant decision by examination section/examining division
R082 Change of representative
R020 Patent grant now final

Effective date: 20130712

R081 Change of applicant/patentee

Owner name: INFINEON TECHNOLOGIES AG, DE

Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE

Owner name: POLARIS INNOVATIONS LTD., IE

Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE

R081 Change of applicant/patentee

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Free format text: FORMER OWNER: INFINEON TECHNOLOGIES AG, 85579 NEUBIBERG, DE

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee