DE10142690A1 - Kontaktierung des Emitterkontakts einer Halbleitervorrichtung - Google Patents

Kontaktierung des Emitterkontakts einer Halbleitervorrichtung

Info

Publication number
DE10142690A1
DE10142690A1 DE10142690A DE10142690A DE10142690A1 DE 10142690 A1 DE10142690 A1 DE 10142690A1 DE 10142690 A DE10142690 A DE 10142690A DE 10142690 A DE10142690 A DE 10142690A DE 10142690 A1 DE10142690 A1 DE 10142690A1
Authority
DE
Germany
Prior art keywords
contact
substrate
normal direction
conductor
metal plane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE10142690A
Other languages
German (de)
English (en)
Inventor
Klaus Goller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10142690A priority Critical patent/DE10142690A1/de
Priority to EP02797604A priority patent/EP1421619B1/de
Priority to PCT/EP2002/009346 priority patent/WO2003021676A2/de
Priority to CNB028171292A priority patent/CN100449748C/zh
Priority to TW091119800A priority patent/TWI306648B/zh
Publication of DE10142690A1 publication Critical patent/DE10142690A1/de
Priority to US10/789,384 priority patent/US20040227212A1/en
Priority to US11/458,076 priority patent/US20060246726A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
DE10142690A 2001-08-31 2001-08-31 Kontaktierung des Emitterkontakts einer Halbleitervorrichtung Withdrawn DE10142690A1 (de)

Priority Applications (7)

Application Number Priority Date Filing Date Title
DE10142690A DE10142690A1 (de) 2001-08-31 2001-08-31 Kontaktierung des Emitterkontakts einer Halbleitervorrichtung
EP02797604A EP1421619B1 (de) 2001-08-31 2002-08-21 Kontaktierung des emitterkontakts einer halbleitervorrichtung
PCT/EP2002/009346 WO2003021676A2 (de) 2001-08-31 2002-08-21 Kontaktierung des emitterkontakts einer halbleitervorrichtung
CNB028171292A CN100449748C (zh) 2001-08-31 2002-08-21 半导体装置及其制造方法
TW091119800A TWI306648B (en) 2001-08-31 2002-08-30 Emitter contact of a semiconductor device and method of producing the same
US10/789,384 US20040227212A1 (en) 2001-08-31 2004-02-27 Making contact with the emitter contact of a semiconductor
US11/458,076 US20060246726A1 (en) 2001-08-31 2006-07-17 Making contact with the emitter contact of a semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10142690A DE10142690A1 (de) 2001-08-31 2001-08-31 Kontaktierung des Emitterkontakts einer Halbleitervorrichtung

Publications (1)

Publication Number Publication Date
DE10142690A1 true DE10142690A1 (de) 2003-03-27

Family

ID=7697254

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10142690A Withdrawn DE10142690A1 (de) 2001-08-31 2001-08-31 Kontaktierung des Emitterkontakts einer Halbleitervorrichtung

Country Status (6)

Country Link
US (2) US20040227212A1 (zh)
EP (1) EP1421619B1 (zh)
CN (1) CN100449748C (zh)
DE (1) DE10142690A1 (zh)
TW (1) TWI306648B (zh)
WO (1) WO2003021676A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1695383A1 (en) * 2003-12-16 2006-08-30 International Business Machines Corporation Bipolar and cmos integration with reduced contact height

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6959134B2 (en) * 2003-06-30 2005-10-25 Intel Corporation Measuring the position of passively aligned optical components
KR100887474B1 (ko) * 2006-06-13 2009-03-10 인터내셔널 비지네스 머신즈 코포레이션 감소된 콘택트 높이를 갖는 바이폴라 및 ｃｍｏｓ 집적
KR101676810B1 (ko) 2014-10-30 2016-11-16 삼성전자주식회사 반도체 소자, 이를 포함하는 디스플레이 드라이버 집적 회로 및 디스플레이 장치
US9892958B2 (en) * 2014-12-02 2018-02-13 Globalfoundries Inc. Contact module for optimizing emitter and contact resistance
DE102018104944A1 (de) 2017-06-30 2019-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiter-Bauelement mit einer Auskleidungsschicht mit einem konfigurierten Profil und Verfahren zu dessen Herstellung
US10720358B2 (en) * 2017-06-30 2020-07-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a liner layer with a configured profile and method of fabricating thereof
US10204791B1 (en) * 2017-09-22 2019-02-12 Power Integrations, Inc. Contact plug for high-voltage devices
US11227926B2 (en) * 2020-06-01 2022-01-18 Nanya Technology Corporation Semiconductor device and method for fabricating the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5455189A (en) * 1994-02-28 1995-10-03 National Semiconductor Corporation Method of forming BICMOS structures
DE19650493A1 (de) * 1995-12-20 1997-06-26 Korea Electronics Telecomm Superselbstausgerichteter Bipolartransistor und Verfahren zu dessen Herstellung
US5886387A (en) * 1995-09-27 1999-03-23 Kabushiki Kaisha Toshiba BiCMOS semiconductor integrated circuit device having MOS transistor and bipolar transistor regions of different thickness
DE19958062A1 (de) * 1999-12-02 2001-07-05 Infineon Technologies Ag Verfahren zur Herstellung eines Bipolartransistors und Verfahren zur Herstellung einer integrierten Schaltungsanordnung mit einem solchen Bipolartransistor

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0612799B2 (ja) * 1986-03-03 1994-02-16 三菱電機株式会社 積層型半導体装置およびその製造方法
US4967253A (en) * 1988-08-31 1990-10-30 International Business Machines Corporation Bipolar transistor integrated circuit technology
GB2269938B (en) * 1990-01-10 1994-09-07 Microunity Systems Eng Method of forming self-aligned contacts in a semi-conductor process
US5144191A (en) * 1991-06-12 1992-09-01 Mcnc Horizontal microelectronic field emission devices
US5320972A (en) * 1993-01-07 1994-06-14 Northern Telecom Limited Method of forming a bipolar transistor
DE4418206C2 (de) * 1994-05-25 1999-01-14 Siemens Ag CMOS-kompatibler Bipolartransistor und Herstellungsverfahren desselben
TW297158B (zh) * 1994-05-27 1997-02-01 Hitachi Ltd
US5631495A (en) * 1994-11-29 1997-05-20 International Business Machines Corporation High performance bipolar devices with plurality of base contact regions formed around the emitter layer
JPH09153610A (ja) * 1995-12-01 1997-06-10 Mitsubishi Electric Corp 半導体装置およびその製造方法
US20010029079A1 (en) * 1997-03-28 2001-10-11 Nec Corporation Semiconductor device with multiple emitter contact plugs
US6251763B1 (en) * 1997-06-30 2001-06-26 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
US6239491B1 (en) * 1998-05-18 2001-05-29 Lsi Logic Corporation Integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level, and process for making same
US5933725A (en) * 1998-05-27 1999-08-03 Vanguard International Semiconductor Corporation Word line resistance reduction method and design for high density memory with relaxed metal pitch
US6165880A (en) * 1998-06-15 2000-12-26 Taiwan Semiconductor Manufacturing Company Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits
US6174803B1 (en) * 1998-09-16 2001-01-16 Vsli Technology Integrated circuit device interconnection techniques
DE69828968D1 (de) * 1998-09-25 2005-03-17 St Microelectronics Srl Verbindungsstruktur in mehreren Ebenen
US6074908A (en) * 1999-05-26 2000-06-13 Taiwan Semiconductor Manufacturing Company Process for making merged integrated circuits having salicide FETS and embedded DRAM circuits
US6291335B1 (en) * 1999-10-04 2001-09-18 Infineon Technologies Ag Locally folded split level bitline wiring
JP2001127151A (ja) * 1999-10-26 2001-05-11 Fujitsu Ltd 半導体装置およびその製造方法
US6525415B2 (en) * 1999-12-28 2003-02-25 Fuji Xerox Co., Ltd. Three-dimensional semiconductor integrated circuit apparatus and manufacturing method therefor
US6414371B1 (en) * 2000-05-30 2002-07-02 International Business Machines Corporation Process and structure for 50+ gigahertz transistor
US6534781B2 (en) * 2000-12-26 2003-03-18 Ovonyx, Inc. Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact
KR100400033B1 (ko) * 2001-02-08 2003-09-29 삼성전자주식회사 다층 배선 구조를 갖는 반도체 소자 및 그의 제조방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5455189A (en) * 1994-02-28 1995-10-03 National Semiconductor Corporation Method of forming BICMOS structures
US5886387A (en) * 1995-09-27 1999-03-23 Kabushiki Kaisha Toshiba BiCMOS semiconductor integrated circuit device having MOS transistor and bipolar transistor regions of different thickness
DE19650493A1 (de) * 1995-12-20 1997-06-26 Korea Electronics Telecomm Superselbstausgerichteter Bipolartransistor und Verfahren zu dessen Herstellung
DE19958062A1 (de) * 1999-12-02 2001-07-05 Infineon Technologies Ag Verfahren zur Herstellung eines Bipolartransistors und Verfahren zur Herstellung einer integrierten Schaltungsanordnung mit einem solchen Bipolartransistor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SCHINKE, M.: "Bipolar - HF - Transistor BFP 490 - Familienzuwachs", in: Components, no. 1, 1998, S. 12 u. 13 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1695383A1 (en) * 2003-12-16 2006-08-30 International Business Machines Corporation Bipolar and cmos integration with reduced contact height
EP1695383A4 (en) * 2003-12-16 2007-12-12 Ibm BIPOLAR INTEGRATION AND CMOS WITH REDUCED CONTACT HEIGHT
US7701015B2 (en) 2003-12-16 2010-04-20 International Business Machines Corporation Bipolar and CMOS integration with reduced contact height

Also Published As

Publication number Publication date
US20060246726A1 (en) 2006-11-02
WO2003021676A3 (de) 2003-12-04
CN1550038A (zh) 2004-11-24
CN100449748C (zh) 2009-01-07
US20040227212A1 (en) 2004-11-18
EP1421619B1 (de) 2012-03-07
TWI306648B (en) 2009-02-21
EP1421619A2 (de) 2004-05-26
WO2003021676A2 (de) 2003-03-13

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8139 Disposal/non-payment of the annual fee