CN1929115A - 半导体存储装置及其制造方法 - Google Patents

半导体存储装置及其制造方法 Download PDF

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Publication number
CN1929115A
CN1929115A CNA2006101281351A CN200610128135A CN1929115A CN 1929115 A CN1929115 A CN 1929115A CN A2006101281351 A CNA2006101281351 A CN A2006101281351A CN 200610128135 A CN200610128135 A CN 200610128135A CN 1929115 A CN1929115 A CN 1929115A
Authority
CN
China
Prior art keywords
insulating film
gate
floating gate
substrate
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2006101281351A
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English (en)
Chinese (zh)
Inventor
疋田恒昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CN1929115A publication Critical patent/CN1929115A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
CNA2006101281351A 2005-09-08 2006-09-05 半导体存储装置及其制造方法 Pending CN1929115A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005260383A JP4912647B2 (ja) 2005-09-08 2005-09-08 半導体記憶装置およびその製造方法
JP2005260383 2005-09-08

Publications (1)

Publication Number Publication Date
CN1929115A true CN1929115A (zh) 2007-03-14

Family

ID=37829257

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2006101281351A Pending CN1929115A (zh) 2005-09-08 2006-09-05 半导体存储装置及其制造方法

Country Status (3)

Country Link
US (1) US7315058B2 (https=)
JP (1) JP4912647B2 (https=)
CN (1) CN1929115A (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100590568B1 (ko) * 2004-11-09 2006-06-19 삼성전자주식회사 멀티 비트 플래시 메모리 소자 및 동작 방법
US7968934B2 (en) * 2007-07-11 2011-06-28 Infineon Technologies Ag Memory device including a gate control layer
US8247861B2 (en) * 2007-07-18 2012-08-21 Infineon Technologies Ag Semiconductor device and method of making same
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US20110133266A1 (en) * 2009-12-03 2011-06-09 Sanh Tang Flash Memory Having a Floating Gate in the Shape of a Curved Section

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2799566B2 (ja) * 1985-11-14 1998-09-17 セイコーインスツルメンツ株式会社 半導体装置の製造方法
JPH07130884A (ja) * 1993-10-29 1995-05-19 Oki Electric Ind Co Ltd 不揮発性半導体メモリの製造方法
JPH08181231A (ja) * 1994-12-27 1996-07-12 Hitachi Ltd 不揮発性半導体記憶装置及びその製造方法
JPH11354742A (ja) 1998-06-08 1999-12-24 Hitachi Ltd 半導体装置及びその製造方法
US6091104A (en) * 1999-03-24 2000-07-18 Chen; Chiou-Feng Flash memory cell with self-aligned gates and fabrication process
JP2003188290A (ja) * 2001-12-19 2003-07-04 Mitsubishi Electric Corp 不揮発性半導体記憶装置およびその製造方法
US6894339B2 (en) * 2003-01-02 2005-05-17 Actrans System Inc. Flash memory with trench select gate and fabrication process
JP2005051227A (ja) * 2003-07-17 2005-02-24 Nec Electronics Corp 半導体記憶装置
JP2005085903A (ja) * 2003-09-05 2005-03-31 Renesas Technology Corp 半導体装置およびその製造方法
JP2006121009A (ja) * 2004-10-25 2006-05-11 Renesas Technology Corp 半導体記憶装置およびその製造方法

Also Published As

Publication number Publication date
JP2007073804A (ja) 2007-03-22
US7315058B2 (en) 2008-01-01
JP4912647B2 (ja) 2012-04-11
US20070052006A1 (en) 2007-03-08

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