CN1875482A - 制造鳍型场效应晶体管的方法 - Google Patents
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
本发明涉及FinFET结构以及形成FinFET器件的方法。该方法包括：(a)提供半导体衬底(100)；(b)在所述衬底(100)的顶表面(105)上形成电介质层(110)；(c)在所述电介质层(110)的顶表面(115)上形成硅鳍(135)；(d)在所述鳍(135)的至少一个侧壁(150A)上形成保护层(160)；以及(e)在所述鳍(135)的沟道区(175)中从所述至少一个侧壁(150A)去除所述保护层(160)。在第二实施例中，保护层(160)转变为保护间隔物(210A)。
Description
技术领域
本发明涉及半导体器件领域；更具体地，涉及制造鳍型场效应晶体管(FinFET)的方法。
背景技术
在FinFET技术中，晶体硅的垂直鳍用于形成晶体管的体(body)且栅极形成在体的侧壁上。当栅极形成在体的两侧壁上时，该晶体管通常称为双栅极型FinFET。
随着FinFET密度增大，鳍厚度和形成在鳍上的栅极电介质厚度两者都降低。这产生了两个问题。第一，较薄的栅极电介质要求比现有FinFET制造技术所能制造的更洁净且结晶更理想的鳍侧壁。第二，当现有的鳍制造技术应用于制造薄鳍时，所得鳍不牢固地附着到支承衬底。
因此，需要一种制造具有很薄的鳍的FinFET的方法，所述薄鳍具有晶化接近完美的侧壁表面且克服了薄鳍的固有结构弱点。
发明内容
本发明的第一方面是形成FinFET器件的方法，包括：(a)提供半导体衬底；(b)在该衬底的顶表面上形成电介质层；(c)在该电介质层的顶表面上形成硅鳍；(d)在该鳍的至少一个侧壁上形成保护层；及(e)在该鳍的沟道区中从所述至少一个侧壁去除保护层。
本发明的第二方面是形成FinFET器件的方法，包括：(a)提供半导体衬底；(b)在该衬底的顶表面上形成电介质层；(c)在该电介质层的顶表面上形成具有侧壁的硅鳍；及(d)在所述侧壁的至少一个的至少下部上形成保护间隔物。
本发明的第三方面是FinFET器件，包括：半导体衬底；在该衬底的顶表面上的电介质层；具有侧壁的硅鳍，该鳍在该电介质层的顶表面上；及所述侧壁的至少一个的至少下部上的保护间隔物。
附图说明
本发明的特征阐明在所附权利要求中。然而，结合附图参考下面的示例性实施例的详细描述将更好地理解本发明本身，附图中：
图1A至10A是顶视图，且对应的图1B至10B是横截面图，示出了根据本发明第一实施例的FinFET结构的制造；
图11A是层间电介质(ILD)形成之后图10A和10B所示的利用保形栅极的FinFET的横截面图；
图11B是层间电介质(ILD)形成之后利用镶嵌平坦化的栅极的FinFET的横截面图；
图12A至16A是顶视图，且对应的图12B至16B是横截面图，示出了根据本发明第二实施例的FinFET结构的制造；以及
图17A至17F是横截面图，示出了根据本发明第三实施例的FinFET结构的制造。
具体实施方式
图1A至9A是顶视图，且对应的图1B至9B是横截面图，示出了根据本发明第一实施例的FinFET结构的制造。
图1B是通过图1A的线1B-1B的横截面图。图1A和1B中，提供了半导体衬底100。在一个例子中，衬底100是单晶硅。形成在衬底100的顶表面105上的是掩埋电介质层，当前示例了掩埋氧化物层(BOX)110。形成在BOX 110的顶表面115上的是硅层120。在一个例子中，硅层120为约200至2000厚。硅层120可以是单晶硅、多晶硅或非晶硅。可以获得衬底100、BOX 110和硅层120作为绝缘体上硅(SOI)衬底或SIMOX衬底。蚀刻掩模130形成在硅层125的顶表面上。在一个例子中，蚀刻掩模130通过应用光致抗蚀剂层到硅层120的顶表面125且光刻构图该光致抗蚀剂层而形成。
图2B是通过图2A的线2B-2B的横截面图。图2A和2B中，进行反应离子蚀刻(RIE)工艺(利用例如CF4)从而自BOX 110之上的硅层120去除不需要的硅且留下鳍135。鳍135具有宽度W和高度H。高度H与图1B的硅层120的厚度相同，其为约500至2000。在一个例子中，W为约50至350。鳍135的基面(base surface)140与BOX 110的顶表面115直接物理接触，且鳍与BOX之间的该接触和粘合支承鳍。
图3B是通过图3A的线3B-3B的横截面图。图3A和3B中，利用缓冲氢氟酸(BHF)去除掩模130(见图2B)，导致鳍135的基面140之下BOX110的底切(undercut)。鳍135现在仅由台座(pedestal)145支承。图4B是通过图4A的线4B-4B的横截面图。图4A和4B中，进行包括氧化和BHF剥离的多个清洁步骤来清洁侧壁150A和150B且从侧壁去除表面结晶缺陷。这些清洁步骤引起鳍135的基面140之下的BOX 110的进一步底切。现在鳍135仅由台座155支承。鳍的底切在鳍的每侧为D。在一个例子中，D为约50至75。必须注意不要完全底切鳍135。由于鳍135的基面140与台座155之间的总接触面积降低，鳍变得更容易断裂。
图5B是通过图5A的线5B-5B的横截面图。图5A和5B中，保形保护层160形成在鳍135的侧壁150A和150B以及顶表面150C上且形成在BOX110的暴露的顶表面115上。保护层160保护鳍135的侧壁150A和150B免于来自后续处理(下文描述)的潜在损坏，且结构性地支承鳍。在第一示例中，保护层160是通过等离子体增强化学气相沉积(PECVD)形成的四乙氧基甲硅烷(TEOS)氧化物且为约15至50厚。在第二示例中，保护层160为通过低压化学气相沉积(LPCVD)形成的硅氮化物且为约15至50厚。
接着进行形成掺杂区例如源极/漏极(S/D)区以及调整鳍135内沟道区的掺杂水平所需的一系列工艺步骤。所述步骤每个包括：(1)用光致抗蚀剂掩模对鳍135的区域进行掩模化；(2)进行离子注入；(3)去除光致抗蚀剂掩模(通常在氧等离子体中)；及(4)进行可选的退火。这四个步骤可以重复2至4次或更多次，精确次数取决于所需的鳍135内的掺杂水平控制。最后，进行清洁例如稀释氢氟酸(HF)清洁和/或黄A清洁(HuangA clean)、和/或黄B清洁(Huang B clean)。离子注入步骤的例子示于图6A和6B中且在下文中描述。没有适当的保护层160，侧壁150A和150B的表面会发生损坏且鳍135会底切至鳍从BOX 110分离。
图6B是通过图6A的线6B-6B的横截面图。图6A和6B中，光致抗蚀剂掩模165形成在鳍135的S/D区170之上且在鳍的沟道区175中进行离子注入。离子注入物质X可以是通常注入的任何物质，例如B、P、As、以及Ge。对于源极/漏极离子注入，沟道区175被掩模化且进行到S/D区170中的注入。
图7B是通过图7A的线7B-7B的横截面图。图7A和7B中，光致抗蚀剂掩模180形成在部分保护层160和BOX层110之上且保护层从鳍135未被光致抗蚀剂掩模保护的地方去除。在保护层160包括硅氮化物的例子中，氟基RIE或热磷酸蚀刻可被使用。在保护层160包括二氧化硅的例子中，氟基RIE或稀释HF酸蚀刻可被使用。
图8B是通过图8A的线8B-8B的横截面图。图8A和8B中，栅极电介质层185形成在暴露的侧壁150A和150B及鳍135的顶表面150C上。在一个例子中，栅极电介质层185是约15至50厚的热氧化物。
图9B是通过图9A的线9B-9B的横截面图。图9A和9B中，栅极190形成在鳍的沟道区175中栅极电介质185及鳍135之上。在本例中，栅极190通过导电材料的保形毯式沉积、光刻掩模步骤及RIE形成。适合的栅极材料的例子包括掺杂和未掺杂的多晶硅及诸如W或Al的金属。由于栅极190形成在鳍135的两个侧壁150A和150B之上，所得FinFET将是双栅极的。
图10B是通过图10A的线10B-10B的横截面图。图10A和10B中，如果保护层160是硅氮化物，任何残留的保护层160(见图9A)利用稀释HF蚀刻或氟基RIE或利用H3PO4被去除。鳍135现在被栅极190支承直到ILD沉积在整个FinFET结构上。
图11A是ILD形成之后如图10A和10B所示利用保形栅极的FinFET的横截面图。图11A中，ILD层195沉积在栅极190、鳍135的暴露表面及BOX 110的暴露表面上。进行化学机械抛光(CMP)工艺来平坦化ILD层的顶表面200。ILD材料的例子包括TEOS PECVD氧化物及氟掺杂玻璃(FSG)。通过经形成在ILD 195中的通孔形成到鳍135的S/D区170(见图6A)和栅极190的接触而完成所得FinFET。
图11B是层间电介质(ILD)形成之后利用镶嵌平坦化栅极的FinFET的横截面图。图11B中，首先沉积ILD195且通过镶嵌工艺形成栅极190A。在镶嵌工艺中，通过光刻构图应用于ILD之上的掩模层、进行ILD的反应离子蚀刻(RIE)、去除掩模层、沉积足够厚的导电材料从而填充沟槽及进行CMP工艺来共平坦化(co-planarize)导电材料和ILD的顶表面，来在ILD中形成沟槽。在图11B中，ILD 195的顶表面200与栅极190A的顶表面205共平面。对于镶嵌栅极，蚀刻沟槽之后形成栅极电介质185是必要的。通过经形成在ILD 195中的通孔形成到栅极185的直接接触和到鳍135的S/D区170(见图6A)的接触而完成所得FinFET。
图12A至16A是顶视图，且对应的图12B至16B是横截面图，示出了根据本发明第二实施例的FinFET结构的制造。
图12B是通过图12A的线12B-12B的横截面图。用于第二实施例的起点是紧接如上参照图5A和5B所述的保护层160的沉积之后，且包括图1A(B)至4A(B)所示的全部前面步骤。图12A和12B分别与图5A和5B相同。
图13B是通过图13A的线13B-13B的横截面图。图13A和13B中，进行保护层160(见图12B)的RIE来分别在鳍135的侧壁150A和150B的下部215A和215B上形成支承间隔物210A和210B。间隔物210A和2120B为鳍135提供支承结构。
然后进行形成掺杂区例如源极/漏极(S/D)区以及调整鳍135内沟道区所需的一系列工艺步骤。所述步骤每个包括：(1)用光致抗蚀剂掩模对鳍135的区域进行掩模化；(2)进行离子注入；(3)去除光致抗蚀剂掩模(通常在氧等离子体中)；及(4)进行可选的退火。这四个步骤可以重复2至4次或更多次，精确次数取决于所需的鳍135内的掺杂水平控制。最后，进行清洁例如稀释氢氟酸(HF)清洁和/或黄A清洁(Huang A clean)、和/或黄B(HuangB clean)。离子注入步骤的例子示于图14A和14B且在下文描述。
图14B是通过图14A的线14B-14B的横截面图。图14A和14B中，光致抗蚀剂掩模165形成在鳍135的S/D区170之上且在鳍的沟道区175中进行离子注入。离子注入物质X可以是通常注入的任何物质例如B、P、As、以及Ge。对于源极/漏极离子注入，沟道区175被掩模化且进行到S/D区170中的注入。
图15B是通过图15A的线15B-15B的横截面图。图15A和15B中，栅极电介质层185形成在鳍135的暴露侧壁150A和150B及顶表面150C上。在一个例子中，栅极电介质层185是约15至50厚的热氧化物。间隔物210A和210B将被结合到完成的FinFET器件中。供选地，在栅极电介质185的形成之前，支承间隔物210A和210B可以首先通过RIE被去除。
图16B是通过图16A的线16B-16B的横截面图。图16A和16B中，栅极190形成在鳍的沟道区175中栅极电介质185及鳍135之上。在本例中，通过导电材料的保形毯式沉积、光刻掩模步骤及RIE形成栅极190。适合的栅极材料的例子包括掺杂和未掺杂的多晶硅及诸如W或Al的金属。由于栅极190形成在鳍135的两个侧壁150A和150B之上，所得FinFET将是双栅极的。该FinFET可以如上面本发明第一实施例所述的那样被完成。
图17A至17F是横截面图，示出了根据本发明第三实施例的FinFET结构的制造。在图17A中，提供半导体衬底300。形成在衬底300的顶表面305上的是BOX 310。形成在BOX 310的顶表面315上的是芯层(mandrel layer)320。在一个例子中，芯层320是硅氮化物。在图17B中，芯层320(见图17A)被光刻构图且进行RIE从而形成芯(mandrel)325。在图17C中，非晶硅或多晶硅层330保形地沉积在芯325的顶表面335和侧壁340上以及在BOX 310的暴露的顶表面315上。在一个例子中，通过溅镀硅形成硅层330。硅层330经历高温退火从而转变成单晶硅层。在图17D中，硅层330(见图17C)被进行RIE从而形成鳍345。鳍345的内侧壁350A与芯335的侧壁340接触。在图17E中，保形保护层350形成在芯325的顶表面335、鳍345的顶表面360和外侧壁350B以及BOX 310的暴露顶表面315之上。在图17F中，进行RIE工艺从而形成与鳍345的外侧壁350A的下部370接触的支承间隔物365。可以进行如前所述的进一步处理从而完成FinFET器件。支承间隔物365可以在后面处理中被去除或留在原位并被包含到完成的FinFET器件中。
这样，本发明公开了一种制造具有很薄的鳍的FinFET的方法，所述薄鳍具有结晶接近完美的侧壁表面且克服了薄鳍的固有结构弱点。
上面给出了本发明实施例的说明以用于理解本发明。应理解，本发明不限于这里描述的特定实施例，而是如现在对本领域技术人员来说明显地，能够进行各种修改、调整和替代而不偏离本发明的范围。因此，下面的权利要求意图涵盖落在本发明的实质精神和范围内的这样的修改和变化。
Claims (28)
1.一种形成FinFET器件的方法，包括：
(a)提供半导体衬底；
(b)在所述衬底的顶表面上形成电介质层；
(c)在所述电介质层的顶表面上形成硅鳍；
(d)在所述鳍的至少一个侧壁上形成保护层；以及
(e)在所述鳍的沟道区中从所述至少一个侧壁去除所述保护层。
2.如权利要求1所述的方法，还包括在步骤(d)和(e)之间进行到所述鳍中的至少一个离子注入步骤。
3.如权利要求1所述的方法，还包括：
(f)在所述沟道区中在所述鳍的暴露表面上形成栅极电介质；以及
(g)在所述栅极电介质上形成导电栅极。
4.如权利要求3所述的方法，还包括：
(h)从所述鳍的源极/漏极区去除所述保护层。
5.如权利要求1所述的方法，还包括在步骤(c)和(d)之间从所述鳍之下去除部分所述电介质层。
6.如权利要求1所述的方法，其中所述保护层包括四乙氧基甲硅烷氧化物或硅氮化物。
7.如权利要求1所述的方法，其中所述保护层为约15至50厚。
8.如权利要求1所述的方法，其中所述鳍具有约500至2000的高度且具有约200至500的宽度。
9.如权利要求1所述的方法，其中步骤(c)包括：
在所述电介质层的所述顶表面上形成硅层；
在所述硅层之上形成掩模；
去除所述硅层的未被所述掩模保护的部分从而暴露所述电介质层；及
去除所述掩模。
10.如权利要求1所述的方法，其中所述鳍包括单晶硅。
11.一种形成FinFET器件的方法，包括：
(a)提供半导体衬底；
(b)在所述衬底的顶表面上形成电介质层；
(c)在所述电介质层的顶表面上形成具有侧壁的硅鳍；及
(d)在所述侧壁的至少一个的至少下部上形成保护间隔物。
12.如权利要求11所述的方法，还包括：
(e)进行到所述鳍中的至少一个离子注入步骤。
13.如权利要求11所述的方法，还包括：
(e)至少在所述鳍的沟道区中在所述鳍的暴露表面上形成栅极电介质；及
(f)在所述栅极电介质上形成导电栅极。
14.如权利要求11所述的方法，还包括在步骤(c)和(d)之间从所述鳍之下去除部分所述电介质层。
15.如权利要求11所述的方法，其中所述保护间隔物包括四乙氧基甲硅烷氧化物或硅氮化物。
16.如权利要求11所述的方法，其中所述保护间隔物为约15至50厚。
17.如权利要求11所述的方法，其中所述鳍具有约500至2000的高度且具有约200至500的宽度。
18.如权利要求11所述的方法，其中步骤(c)包括：
在所述的所述顶表面上形成硅层；
在所述硅层之上掩模化；
去除所述硅层的未被所述掩模保护的部分从而暴露所述电介质层；及
去除所述掩模。
19.如权利要求11所述的方法，其中步骤(c)包括：
在所述电介质层上形成芯；
在所述芯的顶表面和侧壁上以及在所述电介质层的未被所述芯覆盖的表面上沉积保形硅层；
从所述芯的所述顶表面及所述电介质层的未被所述芯覆盖的表面去除所述保形硅层。
20.如权利要求19所述的方法，还包括在该去除步骤之后进行所述保形硅层的高温退火。
21.如权利要求11所述的方法，其中所述鳍包括单晶硅。
22.一种FinFET器件，包括：
半导体衬底；
电介质层，其在所述衬底的顶表面上；
硅鳍，其具有侧壁，所述鳍在所述电介质层的顶表面上；及
保护间隔物，其在所述侧壁的至少一个的至少下部上。
23.如权利要求22所述的FinFET器件，其中所述鳍包括沟道区和源极/漏极区。
24.如权利要求22所述的FinFET器件，还包括：
栅极电介质，其在所述鳍的所述沟道区中在所述鳍的表面上；及
导电栅极，其在所述栅极电介质上。
25.如权利要求22所述的FinFET器件，其中所述保护间隔物包括四乙氧基甲硅烷氧化物或硅氮化物。
26.如权利要求22所述的FinFET器件，其中所述保护间隔物为约15至50厚。
27.如权利要求22所述的FinFET器件，其中所述鳍具有约500至2000的高度且具有约200至500的宽度。
28.如权利要求22所述的FinFET器件，其中所述硅鳍包括单晶硅。
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| US10/605,905 US6962843B2 (en) | 2003-11-05 | 2003-11-05 | Method of fabricating a finfet |
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| EP (1) | EP1690294A4 (zh) |
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| US6855583B1 (en) * | 2003-08-05 | 2005-02-15 | Advanced Micro Devices, Inc. | Method for forming tri-gate FinFET with mesa isolation |
| US7355253B2 (en) * | 2003-08-22 | 2008-04-08 | International Business Machines Corporation | Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates |
-
2003
- 2003-11-05 US US10/605,905 patent/US6962843B2/en not_active Expired - Lifetime
-
2004
- 2004-11-05 KR KR1020067008763A patent/KR100843488B1/ko not_active IP Right Cessation
- 2004-11-05 CN CNB2004800322936A patent/CN100459126C/zh active Active
- 2004-11-05 JP JP2006538523A patent/JP4953820B2/ja not_active Expired - Fee Related
- 2004-11-05 EP EP04810448A patent/EP1690294A4/en not_active Withdrawn
- 2004-11-05 WO PCT/US2004/037029 patent/WO2005045900A2/en active Application Filing
-
2005
- 2005-08-26 US US11/213,231 patent/US7247908B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315224A (zh) * | 2010-07-07 | 2012-01-11 | 中国科学院微电子研究所 | 使用FinFET的非易失性存储器件及其制造方法 |
| CN102315224B (zh) * | 2010-07-07 | 2014-01-15 | 中国科学院微电子研究所 | 使用FinFET的非易失性存储器件及其制造方法 |
| CN103811344A (zh) * | 2012-11-09 | 2014-05-21 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
| CN103811344B (zh) * | 2012-11-09 | 2016-08-10 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
| CN103855015A (zh) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | FinFET及其制造方法 |
| CN105097555A (zh) * | 2012-11-30 | 2015-11-25 | 中国科学院微电子研究所 | FinFET及其制造方法 |
| CN105097555B (zh) * | 2012-11-30 | 2017-03-29 | 中国科学院微电子研究所 | FinFET及其制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US7247908B2 (en) | 2007-07-24 |
| US20050280090A1 (en) | 2005-12-22 |
| WO2005045900A3 (en) | 2005-11-03 |
| JP2007511077A (ja) | 2007-04-26 |
| US6962843B2 (en) | 2005-11-08 |
| US20050093074A1 (en) | 2005-05-05 |
| EP1690294A2 (en) | 2006-08-16 |
| EP1690294A4 (en) | 2010-09-22 |
| WO2005045900A2 (en) | 2005-05-19 |
| KR20060115868A (ko) | 2006-11-10 |
| KR100843488B1 (ko) | 2008-07-04 |
| CN100459126C (zh) | 2009-02-04 |
| JP4953820B2 (ja) | 2012-06-13 |
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