CN1863438A - 用于制造嵌入电子元件的印刷电路板的方法 - Google Patents

用于制造嵌入电子元件的印刷电路板的方法 Download PDF

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CN1863438A
CN1863438A CNA2006100785680A CN200610078568A CN1863438A CN 1863438 A CN1863438 A CN 1863438A CN A2006100785680 A CNA2006100785680 A CN A2006100785680A CN 200610078568 A CN200610078568 A CN 200610078568A CN 1863438 A CN1863438 A CN 1863438A
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metal forming
electronic component
laminated member
layer
cross sectional
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李斗焕
柳彰燮
曹汉瑞
闵炳烈
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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Abstract

在此公开了一种用于制造经济且简单的嵌入元件的印刷电路板的方法。该方法特征在于：堆叠其中安装了高密度电子元件的板以形成其中嵌入电子元件的核心层，以及随后建立附加的电路层。

Description

用于制造嵌入电子元件的印刷电路板的方法
技术领域
一般而言，本发明涉及用于制造具有嵌入其中的电子元件的印刷电路板的方法，而且更特别地，涉及一种方法，其中具有嵌入其中的电子元件的核心层通过堆叠安装了电子元件的板而形成，随后在其上建立电路层，从而显著减少了工艺数目，以便以最小成本生产PCB。
背景技术
最近开发的小型便携电子设备，如移动电话、数字摄录机、数字相机、个人数字助理、便携计算机等，需要并基于用于安装高密度电子元件的技术。为满足需要，印刷板趋向于以多层结构来堆叠。
典型地，玻璃-环氧树脂浸渍的电路板具有多层结构，其中钻有通孔。该电路板是高度可靠的，但是难以用于高密度封装。作为实现高电路密度的一种可替换的方法，采用通过通路接触(via-contact)的互连来构建多层电路板。
这样的通路接触使将在LSI和元件间进行的互连最短，且仅必要的层连接于其之间，从而对高密度封装作出大的贡献。
最近，由于与常规技术相比所具备的优点，具有嵌入其中的元件的电路板很受关注。例如，嵌入元件的PCB是多功能的，且相对于其高功能的能力是小的。另外，嵌入元件的PCB在高频允许最短互连，且在某些情况下，提供对W/B或FC或BGA的焊球中发现的可靠性问题的解决方案。
图1所示为根据常规SIMPACT工艺制造的嵌入元件的PCB的截面视图。
如图1所示，嵌入元件的模块包括电绝缘层101、互连图案102、通孔103、焊剂105、以及具有互连图案106、108和内通孔107的单面基片109。
为了解决当元件安装在基片一面上时所发生的散热问题，嵌入元件的PCB还包括由激光或机械钻孔单独形成的内通孔107。
进一步，由于嵌入元件的PCB在基片上形成电路图案的随后通过层叠工艺制造，由此在早期不能检测到缺陷。
图2所示为根据常规SIMPACT工艺制造的具有嵌入其两面中的元件的PCB的截面视图。
如图2所示，嵌入元件的模块包括具有电子元件(有源元件214a和无源元件214b)嵌入其中的绝缘层212，在绝缘层212任一面设置了电路板211。电路板211具有多层互连图案形成于其中的绝缘基片211a。而且，其上和其中形成有互连图案的、绝缘层212中嵌入的电子元件214a和214b与形成在电路板211上的互连图案217电连接。在垂直方向延伸通过绝缘层212，内通孔213电连接形成在彼此相对的一对电路板211上的互连图案217。有源元件214a与互连图案217通过隆起215电连通，所述接触以树脂218密封。无源元件214b也与互连图案217经由连接部件216电连通。
与图1类似，图2的嵌入元件的模块也遭受由于元件安装在形成电路图案的基片上而引起的散热问题。而且，由于嵌入元件的PCB是通过在基片上形成电路图案随后的层叠工艺制造的，由此早期不可检测到缺陷。
发明内容
因此，本发明的一个目的是提供一种用于制造经济且简单的嵌入电子元件的PCB的方法。
本发明的另一目的是提供一种用于制造嵌入电子元件的PCB的方法，其可在安装电子元件之后早期查出有缺陷的板。
根据本发明，上述目标可通过提供用于制造嵌入元件的印刷电路板的方法来实现，所述方法包括：在第一金属箔的一面上安装电子元件；在第一金属箔和第二金属箔之间设置层叠部件，第一金属箔的安装电子元件的表面面对层叠部件；将第一金属箔和第二金属箔压在层叠部件上以形成核心层，其中电子元件嵌入在层叠部件中；以及在第一金属箔和第二金属箔上形成电路图案。
附图说明
本发明的以上和其他目的、特征和优点将结合附图详细说明，其中：
图1所示为根据常规SIMPACT(使用无源和有源元件嵌入技术的模块中的系统)工艺制造的具有电子元件嵌入其一面中的PCB的截面视图。
图2所示为根据常规SIMPACT工艺制造的具有电子元件嵌入其两面中的PCB的截面视图。
图3A到3O所示为根据本发明实施例用于制造嵌入元件的PCB的方法的截面视图；以及
图4A到4N所示为根据本发明另一实施例用于制造嵌入元件的PCB的方法的截面视图。
具体实施方式
下面参考附图详细说明本发明。
参考图3A到3O，提供了截面视图用于说明根据本发明实施例用于制造嵌入元件的PCB的方法。
首先，如图3A所示，电子元件320安装在第一金属箔310a上，具有电子元件320和第一金属箔310a之间的电连接。
对于第一金属箔310a，铜箔可为优选的。为了具有合适的刚性，铜箔可以是厚的，或用加强材(stiffener)支持。在这种情况下，加强材可经由带(tape)而附着到铜箔。优选地，所述带可以是热或UV可拆卸类型的，以方便层叠。
与需要激光或机械钻孔来形成孔穴的、具有嵌入电子元件的常规PCB相比，使用铜箔作为第一金属箔310a使得电子元件嵌入而无需激光或机械钻孔。进一步，铜箔允许省略曾被认为不可缺的盲通孔BVH形成工艺，因此显著降低了生产成本。
电子元件320可包括：有源元件(如晶体管、运算放大器(OPAMP)等)，具有输入和输出，且即使简单地在到其的电应用时也显示输入和输出间的恒定关系；和/或无源元件(电阻器、电感器、电容器等)，不可独立工作，而只有与有源元件组合才起作用。
使用丝网印刷技术，通过分配的导电糊、各向异性导电膜(ACF)或焊剂或非导电糊(NCP)等，可预先施加至铜箔的一面。
电子元件利用铜、ACF和焊剂之一作为用于其的电极。在铜的情况下，群接合是可能的。可替换地，FC连接可应用于电子元件的电极。群接合或FC连接的随后，可需要底部填充(underfill)。获得最佳设计是困难的。实际上，由于其高物理抗性—如对于下降效应、PCB错位效应(在PCB与元件组装时或用户使用时的PCB变形)的抗性等—以及高化学抗性—如使用时温度变化引起的热冲击、铅放射的α射线引起的功能异常等，通常需要底部填充。
图3B是将层叠部件330设置在第一金属箔310a和第二金属箔310b之间使得其上安装了电子元件320的第—金属箔310a的表面面对层叠部件330之后的截面视图。取决于条件，层叠部件330优选由B阶热固性树脂制成。B阶热固层克服了加压时基片或板中分层的问题，后面将对此加以说明。
图3C是通过将第一金属箔310a和第二金属箔310b按压在层叠部件330上而将二者集成到层叠部件中以形成核心层340之后的截面视图。所述按压是通过将外部的热应用于层叠部件来执行的。在热的情况下，B阶热固层软化，于是层叠部件330可紧密粘附于第一金属箔310a和第二金属箔310b而在其之间不留任何空隙。作为按压的缓冲，软化的B阶热固层可解决基片和板的分层问题。
典型的B阶热固层以玻璃纤维加固，这样在按压的时候他们可能损坏电子元件。但是，本发明中使用的层叠部件具有高含量的树脂或可预先处理成在按压时可损坏的地方具有孔穴。
形成核心层340的随后，电路可图案化以便主要检测缺陷。于是，与常规技术只能在最终电路层形成之后发现缺陷相比，本发明可早期发现有缺陷的板。在最终电路层形成之前、恰在形成核心层340之后早期检测到有缺陷的板享有大大降低生产成本的优点，因为如果有缺陷，即可将板丢弃，而无需建立附加电路层。
图3D是提供了用于形成电路图案光敏层350之后的截面视图。
可使用光刻方法或丝网印刷方法来形成电路。在本发明中，光刻方法是优选的。光刻方法根据使用的敏感材料来细分类：干膜和液体敏化材料。在本发明中，优选使用干膜。于是，光敏层由干膜350制成，干膜350包括光阻膜、用于提供挠性的聚脂膜、以及覆盖膜。覆盖膜在层叠工艺中被剥去，而聚脂膜用于在层叠工艺中保护光阻膜并恰在显影工艺之前被剥去。
图3E为与核心层340对准的干膜350被蚀刻以形成互连图案351之后的截面视图。互连图案351的形成通过以此顺序曝光和显影来实现。
对于曝光，形状为将形成的互连图案351的原图膜(artwork film)(未示出)被形成为紧密层迭在干膜350上，干膜350随后暴露于UV光以使光敏材料发生化学变化。因为它阻挡UV光，所以快速附至干膜350的原图膜保护互连图案351区不受UV光的影响而使干膜的其他区暴露于UV光。干膜350的暴露区被固化而未暴露区保持不变。
执行显影以溶解未暴露区，保留干膜350的固化区，这导致互连图案351。通常使用1％碳酸钠(Na2CO3)或碳酸钾(K2CO3)溶液作为显影液。
当然，在本专利文档中描述的每一电子元件的每个电互连点应该不同的互连到板上分离的垫中。但是，为了方便，详细的互连形状将完全简化。
图3F为以干膜350的互连图案作为蚀刻阻挡来形成核心层340的内部互连图案之后的截面视图。可以理解通过光刻法形成的干膜互连图案不负责互连，但铜箔的结果的互连图案有效地作为互连装置。
为了形成铜箔的互连图案，可应用蚀刻方法、使用导电糊的附加方法或丝网印刷方法，优选为蚀刻方法。当应用蚀刻方法时，可使用氯化铁溶液、氯化铜(CuCl2)溶液、碱溶液、或过氧化氢(hydrogen peroxide)-硫酸溶液作为蚀刻剂。
图3G是干膜350的蚀刻阻挡被剥除以显露金属箔310a和310b的内部互连图案352之后的截面视图。
作为用于剥除蚀刻阻挡的分层溶液，优选使用氢氧化钠或氢氧化钾溶液。当分层溶液的羟基(hydroxide group)与干膜的羧基(carboxyl group)反应时，该膜脱离基片。
图3H是一层绝缘层360沉积在其中金属箔的互连图案被暴露的核心层340之上后的截面视图。
一般而言，带有铜箔的预浸料或树脂涂覆的铜箔经常用于层叠工艺。通常的工艺可适用于本工艺。但是，更方便和应力更小的工艺如膜型层叠是更好的选择。在本专利申请中，我们将示出膜型层叠工艺。
绝缘层360防止金属箔310a和310b的互连图案与无电镀的铜层380a和电镀的铜层380b直接接触，其将在后面说明。
图3I为通过绝缘层360覆盖的核心层340而形成通孔370之后的截面视图。
通孔370起连接第一金属箔310a和第二金属箔310b的作用并通过钻孔形成。在钻孔的随后，执行去毛刺和去污工艺以去除钻孔工艺期间产生的各种杂质和污染。通常，穿过板形成有两种孔：一种将使元件插入其中以便与形成在相对面上的互连电连通；以及另一种是仅用于两层间的电连接。在本发明中，仅采用用于两层间电连接的孔。
完成去毛刺工艺是为了去除钻孔工艺期间产生的铜箔毛刺、孔内壁上的灰尘、以及铜箔上的灰尘和指纹。而且，去毛刺工艺使铜箔表面粗糙以在后述的镀工艺中增加铜对其的粘附性。
对于去污工艺，其目的是去除由于钻孔产生的热导致的基片树脂融化引起的污迹。由于对于劣化镀在孔内侧壁上的铜的质量有主要作用，因此这些污迹必须去除。
图3J是在铜镀在通孔370内侧壁上之后、随后在通孔370中填充填充物371的截面视图。
为了以铜来镀通孔370的内侧壁，顺序执行无电镀工艺380a和电镀工艺380b。通常，无电镀工艺是可为非导体—如树脂，陶瓷，玻璃等—的表面提供导电性的唯一工艺。在本发明中，用无电镀方式利用铜来镀通孔370的内侧壁，以电连通层间互连。
由于无电镀铜层380a的出现，可利用铜进行电镀。通常，电镀工艺能够形成比无电镀工艺更厚和更高质量的镀层。所以，电镀铜层380b比无电镀铜层380a更厚且质量更高。
填充物371优选为导电糊。
图3K是当用于外部互连图案的一层干膜350沉积在结果的结构之上以后的截面视图，其中核心层340是用铜来镀的。
图3L为用干膜350作为掩模进行光刻工艺以形成外部互连图案390之后的截面视图。该工艺与上述内部互连图案352的形成类似。
图3M为干膜350被去除以显露无电镀铜层380a和电镀铜层380b的外部互连图案的截面视图。该分层工艺可以上述相同的方式进行。
图3N为绝缘层391a和392b沉积在其中形成外部互连图案390的结构的整个表面之上、随后在每一绝缘层顶上形成电路图案392之后的截面视图。
图3O为通过上述多层印刷完成建立之后的多层PCB的截面视图。
参考图4A到4N，提供了根据本发明另一实施例制造嵌入元件的PCB的方法的截面视图。
图4A到4N所示方法与图3A到3O所示的类似，除了使用了其上安装了电子元件的第二金属箔410来替代第二金属箔310b以外，以制造具有电子元件嵌入其两面的PCB。
详细地，如图4A所示，电子元件320安装在第一金属箔410a和第二金属箔410b上，在电子元件420和第一金属箔410a之间以及在电子元件420和第二金属箔410b之间有电连接，而层叠部件410设置在第一金属箔410a和第二金属箔410b之间，以使第一金属箔410a和第二金属箔410b每个的安装元件的表面面对层叠部件410。
第一金属箔410a和第二金属箔410b二者优选由铜箔制成。为了具有合适的刚度，铜箔可以是厚的，或可用加强材支持。在这种情况下，加强材可经由带附着到铜箔。优选地，所述带可以是热或UV可拆卸类型的，以方便层叠。
与其中电子元件420安装在其上已形成了电路图案电路板上的常规方法相比，使用铜箔使得即使在不提供散热的通孔的情况下热也容易地从其散出。因此，本发明大大减少了安装高密度集成电路时发生的散热问题，甚至无需附加的激光或钻孔工艺。
电子元件420可包括：有源元件(如晶体管、运算放大器(OPAMP)等)，其具有输入和输出，且即使简单地在到其的电应用时也显示输入和输出间的恒定关系；和/或无源元件(电阻器、电感器、电容器等)，不可独立工作，而只有与有源元件组合才起作用。
使用丝网印刷技术，通过分配的导电糊、各向异性导电膜(ACF)或焊剂或非导电糊(NCP)等，可预先施加至铜箔的一面。
取决于条件，层叠部件410优选由B阶热固性树脂制成。B阶热固层克服了加压时基片或板中分层的问题，后面将对此加以说明。
图4B是在通过将第一金属箔410a和第二金属箔410b压在层叠部件410上使二者集成到层叠部件410中以形成核心层440之后的截面视图。所述按压通过将外部热应用于层叠部件来执行。在热的情况下，B阶热固层软化，使得层叠部件410可紧密粘附至第一金属箔410a和第二金属箔410b，而其之间不留任何空隙。作为对按压的缓冲，软化的B阶热固层可解决使基片和板分层的问题。
典型的B阶热固层利用玻璃纤维来加固，使得他们在按压的时候可能损坏电子元件。但是，本发明中使用的层叠部件具有高含量的树脂或可预先处理以在按压时可能损坏的地方具有空穴。
形成核心层340的随后，电路可图案化以便主要检测缺陷。于是，与常规技术只能在最终电路层形成之后发现缺陷相比，本发明可早期发现有缺陷的板。在最终电路层形成之前、恰在形成核心层340之后早期检测到有缺陷的板享有大大降低生产成本的优点，因为如果有缺陷，即可将板丢弃，而无需建立附加电路层。
图4C为提供了用于形成电路图案的光敏层450之后的截面视图。光刻方法或丝网印刷方法可用于形成电路。在本发明中，光刻方法是优选的。
图4D为蚀刻与核心层440对准的干膜450以形成互连图案451之后的截面视图。互连图案451的形成按此顺序通过曝光和显影来实现。
图4E为以干膜450的互连图案作为蚀刻阻挡而形成核心层440的内部互连图案452之后的截面视图。
图4F是剥除干膜450的蚀刻阻挡以显露金属箔410a和410b的内部互连图案452之后的截面视图。
图4G是当一层绝缘层460沉积在其中金属箔的互连图案被暴露的核心层440之上的截面视图。
绝缘层460起到防止金属箔410a和410b的互连图案与无电镀的铜层380a和电镀的铜层380b直接接触的作用，其将在后面说明。
图4H为穿过被绝缘层460覆盖的核心层440形成通孔470之后的截面视图。
图4I当铜被镀在通孔470的内侧壁上之后、随后在通孔470中填充填充物371的截面视图。
为了以铜来镀通孔470的内侧壁，顺序执行无电镀工艺480a和电镀工艺480b。
填充物371优选为导电糊。
图4J为用于外部互连图案的一层干膜450沉积在其中核心层440以铜镀的结果的结构之上以后的截面视图。
图4K为以干膜450作为掩模进行光刻工艺以形成外部互连图案490之后的截面视图。该工艺与上述内部互连图案452的形成类似。
图4L为干膜450已经被去除以显露无电镀铜层480a和电镀铜层480b的外部互连图案之后的截面视图。该分层工艺可以上述相同的方式进行。
图4M为绝缘层491a和492b已经沉积在形成外部互连图案490的结构的整个表面之上、随后在每一绝缘层顶上形成电路图案492以后的截面视图。
图4N为通过上述多层印刷完成建立之后的多层PCB的截面视图。
如上所述，与常规技术只能在最终电路层形成之后发现缺陷相比，根据本发明的制造嵌入元件的PCB的方法可早期发现有缺陷的板。在最终电路层形成之前、恰在形成核心层340之后早期检测到有缺陷的板享有大大降低生产成本的优点，因为如果有缺陷，即可将板丢弃，而无需建立附加电路层。
与需要激光或机械钻孔来形成孔穴的、具有嵌入电子元件的常规PCB相比，本发明无需激光或机械钻孔来形成嵌入的元件。进一步，本发明省略曾被认为不可缺的盲通孔BVH形成工艺，因此显著降低了生产成本。
而且，在本发明的方法中，使用软化的B阶热固层作为用于嵌入安装在金属箔上的元件的按压的缓冲，并且因此可解决按压时基片和板的分层问题。
虽然已其结合特定实施例说明了本发明，但是对本领域的技术人员显而易见的是，可进行很多替换、修改和变更。因此，意图是涵盖落入所附权利要求的精神和范围内的所有这些替换、修改和变更。

Claims (6)

1.一种用于制造嵌入元件的印刷电路板的方法，包括：
在第一金属箔的一面上安装电子元件；
在所述第一金属箔和第二金属箔之间设置层叠部件，所述第一金属箔的安装电子元件的表面面对所述层叠部件；
将所述第一金属箔和所述第二金属箔压在所述层叠部件上以形成核心层，其中电子元件嵌入所述层叠部件中；以及
在所述第一金属箔和所述第二金属箔上形成电路图案。
2.根据权利要求1的方法，进一步包括在所述设置步骤前在所述第二金属箔上安装电子元件。
3.根据权利要求1的方法，其中所述第一金属箔和所述第二金属箔由铜制成。
4.根据权利要求1的方法，其中所述电子元件通过使用焊球、各向异性导电膜、导电糊或非导电糊等、通过其之间的电连接安装在所述第一金属箔上。
5.根据权利要求1的方法，其中所述电子元件是有源元件和/或无源元件。
6.根据权利要求1的方法，其中所述层叠部件是B阶热固层。
CNA2006100785680A 2005-05-10 2006-05-10 用于制造嵌入电子元件的印刷电路板的方法 Pending CN1863438A (zh)

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