CN1971897B - 球格阵列布线架构 - Google Patents

球格阵列布线架构 Download PDF

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CN1971897B
CN1971897B CN200510101741A CN200510101741A CN1971897B CN 1971897 B CN1971897 B CN 1971897B CN 200510101741 A CN200510101741 A CN 200510101741A CN 200510101741 A CN200510101741 A CN 200510101741A CN 1971897 B CN1971897 B CN 1971897B
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via hole
grid array
metal level
ball grid
wiring structure
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CN1971897A (zh
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黄亚玲
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Priority to CN200510101741A priority Critical patent/CN1971897B/zh
Priority to US11/309,542 priority patent/US20070114578A1/en
Publication of CN1971897A publication Critical patent/CN1971897A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/093—Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

一种球格阵列布线架构，包括一基板、及若干焊盘，所述基板包括一表层和一金属层，所述基板的表层具有一布线区域和一周边区域，所述金属层上具有一层金属箔，所述若干焊盘呈阵列排列于所述布线区内，其特征在于：所述基板上还包括若干穿过所述表层和金属层的过孔，所述过孔包括一需与所述金属层导通的第一过孔以及若干无需与所述金属层导通的第二过孔，所述周边区域内设有至少一第二过孔，且所述第一及第二过孔与所述布线区域内的焊盘一一对应电性连接，所述第一过孔在所述金属层中与所述金属箔电性连通。

Description

球格阵列布线架构
【技术领域】
本发明涉及一种球格阵列布线架构。
【背景技术】
球格阵列是印刷电路板上常用的组件，通常中央处理器、北桥、南桥、加速图形接口芯片、连接卡总线芯片等，大多是以球格阵列的形式封装。如何处理球格阵列的走线，对信号会有很大的影响。
美国专利申请第6373139号揭露了一球格阵列布线架构，如图1所示，所述布线架构包括一基板、一组焊盘和一组与所述焊盘相对应的过孔，所述基板包括一表层100和一内层200。在所述表层120上，一球格阵列布线区域120运用正交坐标通过一X轴104和一Y轴102分成四个区域1、2、3，及4。在所述区域1和3中，一球格阵列的焊盘110与相应过孔112的连线与所述X轴104在顺时针方向的夹角均为45度；在所述区域2和4中，所述球格阵列的焊盘110与对应过孔112的连线与所述X轴104在顺时针方向的夹角均为135度。在所述四个区域中，所述球格阵列的过孔112比与之对应的焊盘110更靠近所述布线区域120的周边区域130。
请参阅图2，所述球格阵列的过孔在基板内金属层上的分布图。如上述球格阵列布线架构，所述内层200上铺有一层金属箔，因此又被称为“金属层”，所述过孔穿过基板表层100和所述内层200，所述内层200上，多数过孔无需与所述内层200导通，故此类过孔周边的金属箔即被挖空形成一绝缘区域；少量过孔需要与所述内层200导通，故此类过孔周边的金属箔需要保留。然而，由于过孔在印刷电路板上的分布密集，若一需与所述内层200导通的过孔被若干无需与所述内层200导通的过孔包围，则需与所述内层200直接电耦合的过孔周边的金属箔将被所述绝缘区域隔离，如过孔103周边的金属箔即属此类情形。可见，所述过孔103即使与其周边的金属箔连接，也未与所述内层200导通，因此需要通过走线绕过过孔与所述内层200导通，但由于过孔分布密集，布线不方便。
【发明内容】
鉴于上述技术内容，有必要提供一种球格阵列布线架构，使其过孔穿过印刷电路板的金属层时，避免位于需与该金属层导通的过孔周边的金属箔被绝缘区域隔离。
一种球格阵列布线架构，包括一基板、及若干焊盘，所述基板包括一表层和一金属层，所述基板的表层具有一布线区域和一周边区域，所述金属层上具有一层金属箔，所述若干焊盘呈阵列排列于所述布线区内，其特征在于：所述基板上还包括若干穿过所述表层和金属层的过孔，所述过孔包括一需与所述金属层导通的第一过孔以及若干无需与所述金属层导通的第二过孔，所述周边区域内设有至少一第二过孔，且所述第一及第二过孔与所述布线区域内的焊盘一一对应电性连接，所述第一过孔在所述金属层中与所述金属箔电性连通。
所述球格阵列的布线架构，使高密度排布的球格阵列在多层板的布线中，有效的避免了位于第一过孔周边的金属箔被绝缘区域隔离的情形。
【附图说明】
下面参照附图结合实施例对本发明作进一步的说明。
图1是现有技术中球格阵列于基板表层的布线架构图。
图2是现有技术中球格阵列布线架构中的过孔于基板内金属层上的分布图。
图3是本发明球格阵列布线架构较佳实施例球格阵列于基板表层的布线架构图。
图4是本发明球格阵列布线架构较佳实施例的球格阵列的过孔于基板内金属层上的分布图。
【具体实施方式】
请参阅图3，为本发明球格阵列布线架构较佳实施例的球格阵列于基板表层的布线架构图。
一种球格阵列布线架构，包括一基板，若干焊盘301及若干过孔302。
请一并参阅图4，为本发明较佳实施例的球格阵列的过孔于基板内金属层上的分布图，所述基板包括一表层300和一内层400，其中所述内层400为一金属层。所述表层300包括一布线区域310和一周边区域320。
所述焊盘301位于所述表层300上，且排列成点阵。所述过孔302穿过所述表层300和所述内层400。
在所述基板表层300上，各所述焊盘301均对应于一所述过孔302，其间通过走线电性连接。所述焊盘301与所述过孔302形成一一对应的关系。
所述若干过孔302包括一需与所述内层400导通的过孔303，及若干无需与所述内层400导通的过孔304。
请一并参阅图1、图3和图4，在现有技术中，所述表层100中，所述过孔103需与金属层导通，其四周的过孔均为无需与金属层导通的过孔。若将所述过孔103一侧的若干过孔移至所述周边区域，便得到如图3所示的布线架构，在本发明所述球格阵列布线架构中，两所述过孔304位于所述周边区域320，以使所述过孔303在所述内层400中与金属箔电性连通。
在所述内层400，每一所述过孔304周围具有一绝缘区域，用以将该过孔304与所述内层400中的金属箔隔离；所述过孔303穿过所述内层400的金属箔，且与所述金属箔电性连通。
所述球格阵列的布线架构，在高密度排布的球格阵列在多层板的布线中，有效的避免了位于需与金属层导通的过孔周边的金属箔被绝缘区域隔离的情形。

Claims (3)

1.一种球格阵列布线架构，包括一基板、及若干焊盘，所述基板包括一表层和一金属层，所述基板的表层具有一布线区域和一周边区域，所述金属层上具有一层金属箔，所述若干焊盘呈阵列排列于所述布线区内，其特征在于：所述基板上还包括若干穿过所述表层和金属层的过孔，所述过孔包括一需与所述金属层导通的第一过孔以及若干无需与所述金属层导通的第二过孔，所述周边区域内设有至少一第二过孔，且所述第一及若干第二过孔均与所述布线区域内的焊盘一一对应电性连接，所述第一过孔在所述金属层中与所述金属箔电性连通。
2.如权利要求1所述的球格阵列布线架构，其特征在于：所述第一过孔及若干第二过孔与对应焊盘之间通过走线电性连接。
3.如权利要求1所述的球格阵列布线架构，其特征在于：所述若干第二过孔周围均具有一绝缘环形区域，用以隔离所述第二过孔与所述金属箔。
CN200510101741A 2005-11-24 2005-11-24 球格阵列布线架构 Expired - Fee Related CN1971897B (zh)

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CN200510101741A CN1971897B (zh) 2005-11-24 2005-11-24 球格阵列布线架构
US11/309,542 US20070114578A1 (en) 2005-11-24 2006-08-18 Layout structure of ball grid array

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Publication number Priority date Publication date Assignee Title
CN102595776B (zh) * 2012-03-06 2014-12-10 京信通信系统（中国）有限公司 一种印刷电路板
CN113382557B (zh) * 2021-05-08 2023-02-28 山东英信计算机技术有限公司 一种内存条插槽连接器焊接布局方法及pcba板卡

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6373139B1 (en) * 1999-10-06 2002-04-16 Motorola, Inc. Layout for a ball grid array

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US5583378A (en) * 1994-05-16 1996-12-10 Amkor Electronics, Inc. Ball grid array integrated circuit package with thermal conductor
JP3570679B2 (ja) * 1999-09-22 2004-09-29 鈴鹿富士ゼロックス株式会社 グリッドアレイ電子部品およびその配線強化方法ならびにその製造方法
JP2005166794A (ja) * 2003-12-01 2005-06-23 Ricoh Co Ltd 部品パッケージとプリント配線基板および電子機器
KR100716826B1 (ko) * 2005-05-10 2007-05-09 삼성전기주식회사 전자부품이 내장된 기판의 제조방법

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6373139B1 (en) * 1999-10-06 2002-04-16 Motorola, Inc. Layout for a ball grid array

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