CN101982025B - 用于制造电子组件的方法 - Google Patents

用于制造电子组件的方法 Download PDF

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Publication number
CN101982025B
CN101982025B CN200980110836.4A CN200980110836A CN101982025B CN 101982025 B CN101982025 B CN 101982025B CN 200980110836 A CN200980110836 A CN 200980110836A CN 101982025 B CN101982025 B CN 101982025B
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electronic device
conducting film
circuit board
contact point
electronic
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CN101982025A (zh
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U·沙夫
A·库格勒
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Robert Bosch GmbH
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Robert Bosch GmbH
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Abstract

本发明涉及一种用于制造包括具有至少一个电子器件(9，13)的电路板(29)的电子组件(27)的方法，其中首先将至少一个具有接触点(11)的电子器件(9)固定在导电膜(1)上，其中所述至少一个电子器件(9)的有源侧指向导电膜(1)的方向，并且接触点(11)被布置在电子器件(9)的有源侧的接触位置处。在此之后，将导电膜(1)连同所述至少一个被固定在其上的电子器件(9，13)层压到电路板载体(17)上，其中所述至少一个电子器件(9，13)指向电路板载体(17)的方向。最后，通过使导电膜(1)结构化来构造印制导线结构(25)。此外，本发明涉及一种电子组件。

Description

用于制造电子组件的方法
技术领域
本发明涉及一种用于制造包括具有至少一个电子器件的电路板的电子组件的方法、以及一种根据权利要求11前序部分所述的电子组件。
背景技术
为了能够封装用在电路板上的电子组件中的电子器件并且为了提高电路载体上的面积利用，公知的是将电子器件容纳在电路板中。由此可以保护电子器件。例如从US-B 6,512,182中公知的是，在电路板衬底中铣削出容纳部，其中电子器件被置入到所述容纳部中。在置入电子器件以后，所述容纳部被填满，接着被平整化和层压。通过嵌入电子器件，可以实现所述电子器件的平整的表面。
该组件的缺点是，首先在电路板衬底中铣削出里面置入电子器件的容纳部。通过这种方式，对电子器件的精确定位仅能困难地实现。
从DE-A 10 2005 003 125中公知有一种用于制造电路的方法，其中所述电路具有通过浇注材料彼此机械连接的电子器件。在所述浇注材料的至少一侧设置有将所述电子器件彼此连接的至少一层印制导线。为了制造该电路，所述器件被施加到载体膜上并且接着被用浇注材料包封。紧接着，所述载体膜被除去，并且将所述器件彼此电连接的一层或多层印制导线被施加在所述器件与所述载体膜相连接了的那侧。
该方法的缺点是，必须无残留地除去所述载体膜，以便实现该电路的有功能作用的连接。
从现有技术中公知的方法的另一缺点是，由于所述电路板结构，所述电路板上的装配面受到限制。此外，所述接线端子部分地相对较长，这在高时钟频率范围中的应用中是不利的。
发明内容
一种根据本发明的用于制造包括具有至少一个电子器件的电路板的电子组件的方法包括下列步骤：
(a)将至少一个具有接触点的电子器件固定在导电膜上，其中所述至少一个电子器件的有源侧指向所述导电膜的方向，并且所述接触点被布置在所述电子器件的有源侧上的接触位置处，
(b)将所述导电膜连同所述至少一个被固定在其上的电子器件层压到电路板载体上，其中所述至少一个电子器件指向所述电路板载体的方向，
(c)通过使所述导电膜结构化来构造印制导线结构。
在本发明的意义上，所述接触点是由导电材料构成的、被设置在该电子组件的接触位置处的小突起。在此，所述突起的高度对应于该电子组件应当取的距所述导电膜的间距。合适的接触点例如是焊接凸点或短柱凸点。所述接触点同时用于使所述电子器件接触所述导电膜。通过这种方式，实现短的接线端子，所述短的接线端子尤其是在高时钟频率范围中的应用中是有利的。另一优点是，由此该电子组件在安装期间就已经被接触，从而可以减小工艺步骤的数目。使该电子组件与所述接触点接触的另一优点是，不需要空间来将所述电子器件的处于上面的接线端子与导电膜相连接。通过这种方式，可以进行更密集的装配，这导致提高的面积利用。
另一优点是，在制造中避免有风险的比如焊接、粘接和线键合的混合技术。
根据本发明的方法的另一优点是，所述电子器件可以通过固定在所述导电膜上被精确地定位。在接下来将所述导电膜连同所述至少一个被固定在其上的电子器件层压到电路板载体上时，其中所述至少一个电子器件指向所述电路板载体的方向，所述至少一个电子器件被电路载体包围。由此，所述器件被完全包封。通过完全包封敏感器件，实现所述电子组件的高的可靠性。
此外，实现平坦的初始结构，由此生成可复制的高频中间产品。
通过在层压到电路板载体上以后使导电膜结构化，通过简单的方式产生所需的印制导线。由此可以快速和低成本地制造电子组件。
在根据本发明的第一实施方式中，所述导电膜具有绝缘层。所述至少一个器件被固定在所述绝缘层上，其中所述接触点穿透所述绝缘层，并且器件与所述导电膜电相接触。所述绝缘层充当电介质并且用于使得不是所述电子器件的整个有源侧处于所述导电膜上。
可替代的特别优选的实施方式中，为了固定所述至少一个电子器件而将粘合剂涂覆到所述导电膜上。该粘合剂充当所述导电膜与所述至少一个电子器件之间的电介质。而且在该实施方式中，所述接触点使所述器件与所述导电膜接触。将粘合剂涂覆到所述导电膜上的实施方式的优点是，不需要对所述导电膜进行镀层。这与镀层的膜相比具有成本优势，因为将粘合剂施加到膜上比对膜进行镀层成本低。
此外，除了具有接触点的器件外，还可能的是：在一个实施方式中，将至少一个另外的没有接触点的电子器件固定在所述导电膜上的绝缘层或粘合剂层上。
在一个优选的实施方式中，所述至少一个电子器件以及必要时所述至少一个另外的电子器件在固定在所述导电膜上以后被聚合物材料包围。用聚合物材料包围所述至少一个电子器件导致对所述器件的附加保护。由此在敏感器件的情况下也明显减小损坏的危险。
用来包围所述至少一个电子器件以及必要时包围所示至少一个另外的电子器件的聚合物例如是低压压制材料、例如环氧树脂低压压制材料。所述低压压制材料例如通过注塑方法被施加。在所述聚合物材料中可以附加地留出例如用于较厚的电介质的占位。但是所述占位也可以作为插入件在压力注塑包封所述至少一个电子器件时一起被压力注塑包封。
所述至少一个电子器件以及必要时所述至少一个另外的电子器件的固定优选地通过粘接来进行。为此在第一实施方式中优选的是，所述导电的载体膜具有粘接层。在此，所述粘接层优选地同时形成所述绝缘层。在此，所述导电膜例如是自粘性的导电膜。该粘接可以通过加热和压制工艺来进行。这例如也是热粘接工艺。在第二实施方式中，所述至少一个器件以及必要时所述至少一个另外的器件的粘接通过将粘合剂涂覆到所述导电膜上进行。在此，粘合剂的涂覆可以通过技术人员公知的每种任意的方法进行。因此，例如可以将粘合剂以粘合剂点的形式涂覆到所述导电膜上。此外，也可以给所述导电膜例如涂抹上粘合剂层。但是所述粘合剂优选地以粘合剂点的形式被涂覆在安放有电子器件的位置处。
所使用的导电膜例如是在从电路板技术中亦作为RCC材料而已知的铜膜。另外的合适的导电膜例如是LCP膜或PI膜。除了铜以外，适于作为金属的例如还有铝。
在一个优选的实施方式中，在在步骤(a)中将所述至少一个电子器件施加到所述导电膜上以前，将校准标记引入到所述导电膜中。所述校准标记例如是具有任意截面的孔或盲孔。这些孔例如可以通过蚀刻、冲压、钻孔被引入到所述导电膜中。在此，所述校准标记被设置在所述导电膜的与所述至少一个导电元件相对的侧上。通过所述校准标记，可以在用聚合物材料包围所述至少一个电子器件以后或在将所述导电膜层压到电路板载体上以后确定所述至少一个电子器件以及必要时所述至少一个另外的电子器件的精确位置。这一方面例如是为了构造印制导线结构所必需的，另一方面，在只要至少一个另外的电子器件没有被施加接触点的情况下这是为了接触所述至少一个另外的电子器件所必需的。可替代地，适于作为校准标记的例如还有用来装配所述导电膜的器件。在布置有所述器件的位置处，所述导电膜优选地被钻开(freigebohrt)或者被用X射线探测，以便识别所述器件。除此之外，所述校准标记当然也可以具有技术人员公知的每种其它的形式。
如果不具有接触点的另外的电子器件被安置，则在应当使所述至少一个另外的电子器件与所述导电载体膜电接触的位置处优选地引入孔。为了使所述导电膜与所述至少一个另外的电子器件接触，所述孔例如被金属化。所述孔的引入例如通过激光钻孔来进行。引入孔的位置例如根据所述校准标记来确定。
为了实现所述至少一个另外的电子器件与所述导电载体膜的接触而对所述孔进行的金属化根据技术人员公知的方法来进行。所述金属化例如通过无电流的金属沉积进行。无电流的金属沉积是在电路板制造中所使用的常规方法。对孔的金属化优选地利用铜来进行。
另外的印制导线例如可以通过如下方式施加：在在步骤(c)中被结构化的导电膜上施加含有印制电路结构的另外的层。为此，优选首先施加电介质，由所述电介质来覆盖在步骤(c)中所构造的印制导线。由此同时进行对所述印制导线的绝缘，从而不发生与随后施加的层的印制导线的不期望的电接触。接着，根据技术人员公知的方法将另外的印制导线施加到所述电介质上。可替代地，含有印制导线的所述另外的层也可以通过如下方式来产生：将另外的导电膜施加到第一层上并且接着使所述膜结构化以构造印制导线。所述膜优选地包括用来将所述膜施加到印制导线上的粘性的绝缘层。
具有印制导线的两个层之间的接触例如通过引入孔并且随后使所述孔金属化来进行。可替代地，也可以在应当使第二层的印制导线接触第一层的印制导线的位置处不施加电介质。
为了排出所述电子组件运行时所产生的热，优选的是：在步骤(b)中将所述导电膜层压到电路板载体上以后，使所述至少一个电子器件在背向所述导电膜的侧上与冷却体接触，使得在层压到电路板载体上以后所述冷却体同样被集成到该电路板中。在此，所述冷却体可以是技术人员公知的每种任意的冷却体。因此，例如可能的是，所述冷却体是金属芯。那么，在运行中，所述电子器件将热传导给金属芯，通过所述金属芯，所述热可以被传递到外部。
通过根据本发明的方法，可以通过将工艺同时用于许多模块来实现低成本的布线和封装。另一优点是，可以作为标准构件继续处理所述电子组件。
此外，本发明涉及一种包括至少一个电子器件的电子组件，所述电子器件与电路板上的印制导线结构相连接。所述至少一个电子器件被嵌入在电路板载体中，并且所述印制导线结构被布置在所述电路板的表面上。所述器件与所述印制导线结构的接触通过被设置在器件上的接触点来进行。除了前面已经提到的低成本的封装和由此高的可靠性以外，如当前在现有技术中所使用那样的昂贵的衬底和封装技术被代替或者被减小为小的器件。此外，在根据本发明的电子组件的情况下可以将完整的包括天线的高频电路集中到一个模块上。根据本发明所制造的电子组件可以作为标准构件被继续处理。
所述接触点优选地为焊接凸点或短柱凸点。此外，合适的还有以电镀方式制造的由不同材料、例如铜或金制成的凸点。通过自动化地施加焊接凸点或短柱凸点可能的是，这些凸点分别具有均匀的高度。由此实现所述电子器件与所述导电膜的均匀间距。
在一个优选的实施方式中，在多个层中构造印制导线结构。由此可以提高电路载体上的面积利用。通过附加的层，可以在最狭窄的空间上将所述电子组件装配上构件并与这些构件接触。
为了良好地排出在所述电子组件运行时所产生的热，优选的是，在电路板中含有冷却体。适于作为冷却体的例如是金属芯，其中所述至少一个电子器件通过金属的方式连接到所述金属芯上。
除了所述至少一个电子器以外，还可能的是，所述电子组件含有一个或多个机械的器件。
在根据本发明的方法中或根据本发明所构造的电子组件中所使用的电子器件是技术人员公知的、如用在电路板技术和微电子中那样的所有电子器件。还可以将如电路板技术中所使用那样的、所有的器件用作机械的器件。
附图说明
在附图中示出发明的实施例，并且在下面的描述中详细阐述所述实施例。
附图：
图1-5示出了第一实施方式中的用于制造根据本发明的装置的多个步骤；
图6-10示出了第二实施方式中的用于制造根据本发明的装置的多个步骤。
具体实施方式
图1中示出了导电膜1，所述导电膜1包括导电层3和绝缘层5。绝缘层5优选地是上面可以施加电子器件的粘合层或热塑性塑料。在导电膜1的上面存在导电层3的那侧上引入校准标记7。校准标记7例如可以通过蚀刻、冲压、钻孔、例如激光钻孔被引入到导电膜1中。此外可能的是，校准标记7也是与导电膜1相连接的、被钻开或者由X射线显微镜来探测的器件。校准标记的为技术人员所公知的其它每种形式也是可能的。
导电层3优选地是金属层。特别优选铜作为金属。
在第二步骤中，将电子器件9施加到绝缘层5上。这在图2中予以示出。所述电子器件以其有源侧朝向导电膜1的方式被固定。在电子器件9上，在用于电子器件9与导电膜1接触的位置处设置接触点11。接触点11优选地为由导电材料制成的突起或凸起。接触点11优选地为焊接凸点或短柱凸点(Stubbump)。此外，除了具有接触点11的电子器件9以外还可能的是，将另外的、不具有接触点11的电子器件13施加在导电膜1的绝缘层5上。除了电子器件9、13以外还可能的是，将机械器件施加到导电膜1的绝缘层5上。被施加到导电膜1的绝缘层5上的电子器件9、13以及机械器件是如用在电路板构造中的常规器件。所述器件例如是芯片、处理器、高频组件、SMD部件、天线模块、冷却体、MEMS或者MOEMS。
电子器件9、另外的电子器件13、以及机械器件的施加优选地通过粘接到绝缘层5上来进行。在此，电子器件9、13如同所述电子器件9、13应在稍后被布置在电路中那样被放置到导电膜1的绝缘层5上。可以例如将冷却体施加到单个的或所有电子器件9、13上，以便保证在电子器件9、13的运行期间的提高的散热。在此，可以可选地设置的冷却体被安置在电子器件9、13的背对导电膜1的一侧。
为了实现对敏感电子器件9、13的封装，可以用聚合物材料15包围所述电子器件9、13。这例如在图5中予以示出。聚合物材料15例如是环氧树脂低压压制材料。在需要时，例如可以在聚合物材料15中压力注塑包封例如用于较厚的电介质(其例如被用于天线或冷却体)的占位。利用聚合物材料15进行的包封例如借助于压力注塑方法来进行。所述占位例如可以被成形为凹部或槽。但是除了压力注注塑方法以外，也可以使用技术人员公知的可以用来用聚合物材料15封包电子器件9、13的每种其它方法。附加地，利用聚合物材料15进行的封包所具有的优点是，可以在器件9、13具有不同的厚度的情况下进行高度补偿。这对后面的层压工艺是有利的。此外，构件可以被预封装到可脱去的膜上，并且在脱去所述膜以后被安装到导电膜1上。
在电子器件9被施加到导电膜1上以后、或者如果电子器件9、13应当被聚合物材料包围则在用聚合物材料15包围电子器件9、13以后，导电膜1被切分成电路板切分体(Leiterplattenzuschnitt)。
在切分以后，导电膜1与其上所安放的电子器件9、13、以及必要时的在此未示出的其它机械器件一起被层压成到电路板载体17上。这在图3中予以示出。在此处所示的实施变型方案中，在电子器件9、13未被聚合物材料15包围的情况下，导电膜1连同电子器件9、13被层压到电路板载体17上。但是根据本发明，在图5所示的、电子器件9、13被聚合物材料15包围的实施方式中，其也被层压到电路板载体17上。在此，该层压根据技术人员公知的方法进行。根据本发明，电路板载体17被层压(Auflaminieren)到导电膜1上，使得电子器件9、13或者被聚合物材料15所包围的电子器件9、13被电路板载体17包围。为此，电路板载体17被层压到导电膜1的上面还安放有电子器件9的那侧。
为此，一般而言在构件厚度大于0.1mm的器件9、13的情况下，首先将经过玻璃纤维增强并且在器件9、13的位置处被预先钻孔的经硬化的电路板材料置放于该膜上。在该电路板材料上置放预浸料并且在必要时置放另一经硬化的电路板材料。然后，该堆叠在层压工艺中被挤压。所述经硬化的电路板材料通常是经过玻璃纤维增强的环氧树脂。但是也可以使用技术人员公知的每种其它合适的材料。一般而言，同样将环氧树脂用作预浸料。但是所述预浸料不是完全硬化的。通过施加压力和升高的温度，所述预浸料完全硬化，由此所述预浸料与经硬化的电路板材料相连接。由预浸料和经硬化的电路板材料构成的复合体形成电路板载体17。
在将导电膜1连同电子器件9、13、以及必要时连同被聚合物15包围的电子器件9、13层压到电路板载体17上以后，在不具有接触点11的另外的电子器件13的接线位置处将孔19引入到包括导电层3和绝缘层5的导电膜1中。对孔19的正确定位可以由开头引入的校准标记7来确定。由此可以精确地在所述另外的电子器件13的电接线端子所处于的位置处生成孔19。具有接触点11的电子器件9以其接触点11接触在导电膜1的导电层3上。
通常，如图5所示，在引入孔9以使所述另外的电子器件13与导电层3接触的同时或者紧接着在此之后，在电路板载体17中钻出冷却通道21。为此，例如使用激光钻孔法。如果孔19也通过激光钻孔法来生成，则优选地为冷却通道21使用第二激光器。但是也可以利用同一激光器来钻出所有的孔19和冷却通道21。
通过金属化，所述另外的电子器件13与导电层3电接触。这在图4中予以示出。为了金属化可以通过技术人员公知的方法、例如通过无电流金属沉积将金属23沉积在孔19中。该金属将所述另外的电子器件13的接线端子与导电层3相连接。电接触被产生。通常，被用于金属化的金属23是铜。通常而言，为了金属化首先以无电流的方式沉积由钯构成的起始金属化部。接着，进行电镀铜沉积。金属23可以采取套管的形式或者完全填充孔19。
在为了电接触所述另外的电子器件13而将孔19引入到导电膜1中并且将孔19金属化以后，导电层3被如图4所示的那样结构化。在此，该结构化通过技术人员公知的任意方法进行。合适的方式例如有蚀刻法、光刻法、激光钻孔法、或者激光烧蚀法。
通过使导电层结构化，生成所述电路板所需的印制导线结构25。
通过将电子器件9、13嵌入到电路板载体17中，实现平面的表面。由此可以简单地处理所述表面。但是当然也可以首先从导电膜1加工出印制导线结构25并且接着将孔引入到导电膜1中并且金属化所述孔。
图5中示出了电子组件27。电子组件27包括两个电路板29。电介质31被施加到印制导线结构25上，以便施加另一印制导线结构33。适合作为电介质31的例如有从电路板技术中公知的环氧树脂或FR4材料。电介质31的施加利用技术人员公知的常规技术来进行。因此，例如可以通过刮板(rakeln)、涂抹、压印、层压、帘式涂布、涂膜、喷涂等方法施加电介质31。
另一印制导线结构33被施加到电介质31上。为此可以首先整面地涂覆导电层，所述导电层接着被结构化。
优选地也可以将另一导电膜涂覆到第一印制导线结构25上并且从第二导电膜的导电层中结构化出印制导线结构33。那么，这优选根据与用于将导电层3结构化成印制导线结构25的方法相同的方法进行。在产生印制导线结构33以后，可以将孔35引入到电介质31中，通过所述孔35借助于金属化进行印制导线结构25与该另一印制导线结构33的接触。
特别优选地，为了产生多个被结构化成印制导线的导电层，首先层压电介质31并且接着层压导电膜。在层压电介质31和导电膜以后，首先引入孔，所述孔接着被金属化，以便将所述导电膜与位于其下的层电连接。接着，从所述导电膜中加工出该另一印制导线结构33。
为了将热从电子器件9、13中排出，可以在电子器件9、13的背对印制导线结构25、33的侧将冷却通道21引入到电路板载体17中。冷却通道21可以与冷却体37相连接。在图5中所示的实施例中，冷却体37是金属芯。通过冷却体37和冷却通道21，热被从电子器件9、13排出。一般而言，冷却通道21到冷却体37上的连接通过背侧金属化或可替代的如下连接来进行：在该连接的情况下冷却通道21的内壁设置有金属层。但是也可以用金属完全填充冷却通道21。
此外，也可以在被构造成金属芯的冷却体37与电子器件9、13之间设置冷却元件。也可以将金属性构造为使得所述金属芯直接接触电子器件9、13。
电路板29的连接优选地同样借助于在电路板制造工艺中常见的层压工艺来进行。
利用穿过两个电路板29的通孔39，可以将一个电路板29的印制导线结构25与第二电路板29的印制导线结构33相连接。该电接触例如通过使通孔39的壁金属化来进行。借助于在被构造为金属芯的冷却体37上结束的通孔41，可以将印制导线结构25、33与该金属芯电接触。由此例如可以实现接地接触。在通孔41的情况下，该电接触也优选借助于金属化进行。对通孔39、41的金属化例如通过无电流或电镀的金属沉积来生成。但是可替代地，例如也可以引导导线穿过通孔39、41。
图6至10中示出了用于制造电子组件27的替代方法。图6至10中所示的方法与图1至5中所示的方法的不同之处在于，导电膜1仅仅具有导电层3而不具有绝缘层5。校准标记7被引入到在导电膜1中。为了固定电子器件9，将粘合剂43涂覆到导电膜1上。粘合剂43的涂覆可以成面地或者如图6中所示的那样优选地以粘接点的形式进行。
设置有接触点11的电子器件9被安置到粘接点43上。电子器件9与导电膜1相距的间距由接触点11来确定。粘合剂43充满电子器件9与导电膜1之间的间隙并且形成电介质，使得电子器件9不以其有源侧直接处于导电膜1上。这在图7中予以示出。
为了实现对敏感电子器件9的封装，可以用聚合物材料15包围电子器件9。这在图8中予以示出。聚合物材料15例如是环氧树脂低压压制材料。在需要时，例如可以在聚合物材料15中压力注塑包封例如用于较厚的电介质(其例如被用于天线或冷却体)的占位。利用聚合物材料15进行的包封例如借助于压力注塑法来进行。所述占位例如可以被成形为凹部或槽。但是除了压力注注塑法以外，也可以使用技术人员公知的可以用来用聚合物材料15封包电子器件9的每种其它方法。附加地，利用聚合物材料15进行的封包所具有的优点是，可以在器件9具有不同的厚度的情况下进行高度补偿。这对后面的层压工艺是有利的。此外，构件可以被预封装到可脱去的膜上，并且在脱去所述膜以后利用粘合剂43被安装到导电膜1上。
也如在图1至图5中所示的实施方式中的那样，在粘接电子器件9并且在必要时利用聚合物材料15进行包封以后，从导电膜1形成印制导线结构25。如果所有电子器件9都如图6至10中所示的那样借助接触点11来装备并且通过接触点11与导电膜1相连接，则不需要为了电接触而形成孔19，其中所述孔接着被金属化，以便产生电接触。但是如果利用粘合剂43粘接不具有接触点11的另外的电子器件13，则穿过导电膜1和粘合剂43引入孔19，所述孔19接着被金属化，以便使所述另外的电子器件9、13与导电膜1接触。在这种情况下，在引入孔19之后才进行导电膜1到印制导线结构25的结构化。
在图6至10中所示的实施方式中，在将导电膜1结构化成印制导线结构25以前也首先将电路板载体17如前面已经描述的那样层压到导电膜1上。
图10中示出了电子组件27，其中两个电路板29彼此连接。该构造对应于电子组件27的在图5中所示的构造。图10中所示的电子组件27与图5中所示的实施方式的不同之处在于，在电路板载体17与印制导线结构25之间未构造连续的绝缘层5。用来将电子器件9粘接到印制导线结构25上的粘合剂43用作印制导线结构25与电子器件9之间的电介质。在里面不存在电子器件9的区域中，印制导线结构25被直接施加在电路板载体17上。

Claims (8)

1.一种用于制造包括具有至少一个电子器件(9，13)的电路板的电子组件(27)的方法，包括下列步骤：
(a)将至少一个具有接触点(11)的电子器件(9)固定在导电膜(1)上，其中所述至少一个电子器件的有源侧指向该导电膜(1)的方向，并且接触点(11)被布置在电子器件(9)的有源侧的接触位置处，其中所述接触点是由导电材料构成的、被设置在该电子组件的接触位置处的小突起，并且所述突起的高度对应于该电子组件应当取的距所述导电膜的间距，以及其中为了固定所述至少一个电子器件(9)而将粘合剂(43)涂覆到导电膜(1)上，其中该粘合剂(43)充当导电膜(1)与所述至少一个电子器件(9)之间的电介质，并且所述接触点(11)使该器件(9)与导电膜(1)接触，其中实现短的接线端子并且产生平坦的初始结构以生成可复制的高频中间产品，
(b)将导电膜(1)连同所述至少一个被固定在其上的电子器件(9，13)层压到电路板载体(17)上，其中所述至少一个电子器件(9，13)指向电路板载体(17)的方向，
(c)在将所述至少一个电子器件(9)粘接到所述导电膜(1)上并且将该导电膜(1)层压到所述电路板载体(17)上之后，通过使导电膜(1)结构化来构造印制导线结构(25)，
其特征在于，
至少一个另外的没有接触点的电子器件(13)被固定在所述导电膜(1)上的粘合剂(43)上，以及
在应当使所述至少一个另外的电子器件(13)与所述导电膜(1)电接触的位置处将孔(19)引入到导电膜(1)中，并且为了使导电膜(1)与所述至少一个另外的电子器件(13)接触将所述孔(19)金属化。
2.根据权利要求1所述的方法，其特征在于，所述至少一个电子器件(9，13)在固定在导电膜(1)上以后被聚合物材料(15)包围。
3.根据权利要求1所述的方法，其特征在于，在步骤(a)中将所述至少一个电子器件(9，13)固定在导电膜(1)上以前，将校准标记(7)引入到导电膜(1)中。
4.根据权利要求1所述的方法，其特征在于，在在步骤(c)中被结构化的导电膜(1)上施加含有印制导线结构(33)的另外的层。
5.根据权利要求1所述的方法，其特征在于，所述至少一个电子器件(9，13)在步骤(b)中的层压以前在背向导电膜(1)的一侧上与冷却体(37)接触，使得所述冷却体(37)在所述层压到电路板载体(17)上以后同样被集成到电路板(29)中。
6.一种包括至少一个电子器件(9，13)的电子组件，所述电子器件(9，13)与电路板(29)上的印制导线结构(25，33)相连接，其中所述至少一个电子器件(9，13)被嵌入在电路板载体(17)中，并且所述印制导线结构(25，33)被布置在电路板(29)的表面上，其中，该器件(9)与印制导线结构(25)的接触通过被设置在该器件(9)上的接触点(11)进行，其中所述接触点是由导电材料构成的、被设置在该电子组件的接触位置处的小突起，并且所述突起的高度对应于该电子组件应当取的距所述导电膜的间距，其中构造出短的接线端子并且构造出平坦的初始结构以生成可复制的高频中间产品，以及其中为了固定所述至少一个电子器件(9)而将粘合剂(43)涂覆到导电膜(1)上，其中该粘合剂(43)充当导电膜(1)与所述至少一个电子器件(9)之间的电介质，并且所述接触点(11)使该器件(9)与导电膜(1)接触，
其特征在于，
至少一个另外的没有接触点的电子器件(13)被固定在所述导电膜(1)上的粘合剂(43)上，其中在应当使所述至少一个另外的电子器件(13)与所述导电膜(1)电接触的位置处将孔(19)引入到导电膜(1)中，并且为了使导电膜(1)与所述至少一个另外的电子器件(13)接触将所述孔(19)金属化，以及
能够根据权利要求1至5之一所述的方法来制造所述电子组件。
7.根据权利要求6所述的电子组件，其特征在于，所述接触点(11)是焊接凸点或短柱凸点。
8.根据权利要求6或7所述的电子组件，其特征在于，在多个层中构造印制导线结构(25，33)。
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007024189A1 (de) * 2007-05-24 2008-11-27 Robert Bosch Gmbh Verfahren zur Herstellung einer elektronischen Baugruppe
WO2009147936A1 (ja) * 2008-06-02 2009-12-10 イビデン株式会社 多層プリント配線板の製造方法
US8966747B2 (en) 2011-05-11 2015-03-03 Vlt, Inc. Method of forming an electrical contact
DE102012213916A1 (de) * 2011-11-08 2013-05-08 Robert Bosch Gmbh Elektronikmodul für ein Steuergerät
DE102011088256A1 (de) * 2011-12-12 2013-06-13 Zf Friedrichshafen Ag Multilayer-Leiterplatte sowie Anordnung mit einer solchen
US9536798B2 (en) * 2012-02-22 2017-01-03 Cyntec Co., Ltd. Package structure and the method to fabricate thereof
JP5406389B2 (ja) * 2012-03-01 2014-02-05 株式会社フジクラ 部品内蔵基板及びその製造方法
FI125959B (en) 2013-05-10 2016-04-29 Murata Manufacturing Co Microelectromechanical device and method of manufacture of microelectromechanical device
DE102013217146A1 (de) * 2013-08-28 2015-03-05 Carl Zeiss Smt Gmbh Optisches Bauelement
EP2911486B1 (en) * 2014-02-19 2024-07-31 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft PCB-based connector device
US20150351218A1 (en) * 2014-05-27 2015-12-03 Fujikura Ltd. Component built-in board and method of manufacturing the same, and mounting body
KR102333559B1 (ko) * 2015-05-11 2021-12-01 삼성전자 주식회사 안테나 장치 및 그를 포함하는 전자 장치
US10264664B1 (en) * 2015-06-04 2019-04-16 Vlt, Inc. Method of electrically interconnecting circuit assemblies
EP3562281A1 (de) 2018-04-25 2019-10-30 Siemens Aktiengesellschaft Backplane und verfahren zu deren herstellung
FR3090264B1 (fr) * 2018-12-13 2022-01-07 St Microelectronics Grenoble 2 Procédé de montage de composant
EP3709777A1 (en) 2019-03-11 2020-09-16 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Solder-free component carrier connection using an elastic element, and method
DE102019123193A1 (de) * 2019-08-29 2021-03-04 Endress+Hauser SE+Co. KG Feldgerät der Automatisierungstechnik

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1684341A2 (de) * 2005-01-21 2006-07-26 Robert Bosch Gmbh Elektrische Schaltung und Verfahren zur Herstellung einer elektrischen Schaltung
CN1863438A (zh) * 2005-05-10 2006-11-15 三星电机株式会社 用于制造嵌入电子元件的印刷电路板的方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6538210B2 (en) * 1999-12-20 2003-03-25 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module, radio device having the same, and method for producing the same
JP3598060B2 (ja) * 1999-12-20 2004-12-08 松下電器産業株式会社 回路部品内蔵モジュール及びその製造方法並びに無線装置
US6512182B2 (en) 2001-03-12 2003-01-28 Ngk Spark Plug Co., Ltd. Wiring circuit board and method for producing same
FI119215B (fi) * 2002-01-31 2008-08-29 Imbera Electronics Oy Menetelmä komponentin upottamiseksi alustaan ja elektroniikkamoduuli
US6919508B2 (en) * 2002-11-08 2005-07-19 Flipchip International, Llc Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing
JP2007535123A (ja) * 2003-07-14 2007-11-29 エイブイエックス コーポレイション モジュール式電子アッセンブリーおよび製造方法
FI20031201A (fi) * 2003-08-26 2005-02-27 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli
DE10353676B4 (de) * 2003-11-17 2007-11-29 Siemens Ag Verfahren zur Herstellung eines ultradünnen Moduls mit rauen Kontakten
FI20040592A (fi) * 2004-04-27 2005-10-28 Imbera Electronics Oy Lämmön johtaminen upotetusta komponentista
JP2006165175A (ja) * 2004-12-06 2006-06-22 Alps Electric Co Ltd 回路部品モジュールおよび電子回路装置並びに回路部品モジュールの製造方法
DE102005003125A1 (de) 2005-01-21 2006-07-27 Robert Bosch Gmbh Elektrische Schaltung und Verfahren zur Herstellung einer elektrischen Schaltung
US8225499B2 (en) * 2005-06-16 2012-07-24 Imbera Electronics Oy Method for manufacturing a circuit board structure, and a circuit board structure
JP2007227586A (ja) * 2006-02-23 2007-09-06 Cmk Corp 半導体素子内蔵基板及びその製造方法
KR100770874B1 (ko) * 2006-09-07 2007-10-26 삼성전자주식회사 매설된 집적회로를 구비한 다층 인쇄회로기판
US8174119B2 (en) * 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
DE102007015819A1 (de) * 2007-03-30 2008-10-09 Robert Bosch Gmbh Verfahren zur Herstellung einer elektronischen Baugruppe sowie elektronische Baugruppe
DE102007044754A1 (de) * 2007-09-19 2009-04-09 Robert Bosch Gmbh Verfahren zur Herstellung einer elektronischen Baugruppe sowie elektronische Baugruppe
US8375577B2 (en) * 2008-06-04 2013-02-19 National Semiconductor Corporation Method of making foil based semiconductor package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1684341A2 (de) * 2005-01-21 2006-07-26 Robert Bosch Gmbh Elektrische Schaltung und Verfahren zur Herstellung einer elektrischen Schaltung
CN1863438A (zh) * 2005-05-10 2006-11-15 三星电机株式会社 用于制造嵌入电子元件的印刷电路板的方法

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