KR100770874B1 - 매설된 집적회로를 구비한 다층 인쇄회로기판 - Google Patents
매설된 집적회로를 구비한 다층 인쇄회로기판 Download PDFInfo
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- KR100770874B1 KR100770874B1 KR1020060086215A KR20060086215A KR100770874B1 KR 100770874 B1 KR100770874 B1 KR 100770874B1 KR 1020060086215 A KR1020060086215 A KR 1020060086215A KR 20060086215 A KR20060086215 A KR 20060086215A KR 100770874 B1 KR100770874 B1 KR 100770874B1
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- conductive pads
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
- H01L2224/82035—Reshaping, e.g. forming vias by heating means
- H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01033—Arsenic [As]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10681—Tape Carrier Package [TCP]; Flexible sheet connector
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
Abstract
Description
Claims (7)
- 복수의 절연층 및 복수의 도전성 패턴층을 교대로 적층한 구조를 갖는 다층 인쇄회로기판에 있어서,상기 다층 인쇄회로기판의 내부에 매설되도록 상기 복수의 절연층 중 코어 절연층 내에 배치되며, 그 표면 상에 외부 전기 접속을 위한 복수의 외부접속단자를 구비한 집적회로와;상기 집적회로의 표면에 부착되며, 상기 복수의 외부접속단자와 일대일 전기 접속되는 복수의 내측 도전성 패드를 구비하고, 인접한 도전성 패턴층과 전기 접속되는 필름을 포함함을 특징으로 하는 다층 인쇄회로기판.
- 제1항에 있어서,상기 필름은 상기 복수의 내측 도전성 패드와 와이어들을 통해 일대일 전기 접속되며, 상기 인접한 도전성 패턴층과 전기 접속되는 복수의 외측 도전성 패드를 더 포함함을 특징으로 하는 다층 인쇄회로기판.
- 제2항에 있어서, 상기 필름은,상기 복수의 내측 도전성 패드, 와이어들 및 복수의 외측 도전성 패드가 그 표면 상에 적층되는 기판과;상기 복수의 내측 도전성 패드, 와이어들 및 복수의 외측 도전성 패드를 둘러싸도록 상기 기판의 표면 상에 적층된 접착층을 더 포함함을 특징으로 하는 다층 인쇄회로기판.
- 제2항에 있어서, 상기 필름은 상기 복수의 내측 도전성 패드를 포함하는 중앙부가 상기 집적회로의 표면에 부착되고, 상기 복수의 외측 도전성 패드를 포함하는 가장자리가 상기 인접한 도전성 패턴층의 표면에 부착됨을 특징으로 하는 다층 인쇄회로기판.
- 제1항에 있어서,상기 코어 절연층은 홀을 구비하고, 상기 필름 부착된 집적회로가 상기 홀에 삽입됨을 특징으로 하는 다층 인쇄회로기판.
- 제1항에 있어서,상기 필름은 COF(chip on film) 필름임을 특징으로 하는 다층 인쇄회로기판.
- 제1항에 있어서,상기 코어 절연층은 FR4 재질이고, 나머지 절연층은 ABF(Ajinomoto build-up film) 재질임을 특징으로 하는 다층 인쇄회로기판.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020060086215A KR100770874B1 (ko) | 2006-09-07 | 2006-09-07 | 매설된 집적회로를 구비한 다층 인쇄회로기판 |
US11/685,269 US7751202B2 (en) | 2006-09-07 | 2007-03-13 | Multi-layered printed circuit board having integrated circuit embedded therein |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020060086215A KR100770874B1 (ko) | 2006-09-07 | 2006-09-07 | 매설된 집적회로를 구비한 다층 인쇄회로기판 |
Publications (1)
Publication Number | Publication Date |
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KR100770874B1 true KR100770874B1 (ko) | 2007-10-26 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1020060086215A KR100770874B1 (ko) | 2006-09-07 | 2006-09-07 | 매설된 집적회로를 구비한 다층 인쇄회로기판 |
Country Status (2)
Country | Link |
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US (1) | US7751202B2 (ko) |
KR (1) | KR100770874B1 (ko) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI353661B (en) * | 2007-04-09 | 2011-12-01 | Unimicron Technology Corp | Circuit board structure capable of embedding semic |
EP2136610A4 (en) * | 2008-01-25 | 2011-07-13 | Ibiden Co Ltd | MULTILAYER CONDUCTOR PLATE AND METHOD FOR THE PRODUCTION THEREOF |
DE102008000842A1 (de) * | 2008-03-27 | 2009-10-01 | Robert Bosch Gmbh | Verfahren zur Herstellung einer elektronischen Baugruppe |
TWM362572U (en) * | 2009-04-13 | 2009-08-01 | Phytrex Technology Corp | Signal convertor |
KR101077380B1 (ko) * | 2009-07-31 | 2011-10-26 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
US20110216514A1 (en) * | 2010-03-03 | 2011-09-08 | Mutual-Tek Industries Co., Ltd. | Combined multilayer circuit board having embedded components and manufacturing method of the same |
AT12317U1 (de) * | 2010-04-13 | 2012-03-15 | Austria Tech & System Tech | Verfahren zur integration eines elektronischen bauteils in eine leiterplatte sowie leiterplatte mit einem darin integrierten elektronischen bauteil |
JP5352019B1 (ja) * | 2012-11-14 | 2013-11-27 | 太陽誘電株式会社 | 多層回路基板及び高周波回路モジュール |
JP5574071B1 (ja) * | 2012-12-26 | 2014-08-20 | 株式会社村田製作所 | 部品内蔵基板 |
US9153550B2 (en) * | 2013-11-14 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design with balanced metal and solder resist density |
US20150351218A1 (en) * | 2014-05-27 | 2015-12-03 | Fujikura Ltd. | Component built-in board and method of manufacturing the same, and mounting body |
Citations (4)
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KR19980071398A (ko) | 1997-02-17 | 1998-10-26 | 야스카와 히데아키 | 캐리어 필름 및 그것을 사용한 집적 회로 장치 |
US6903458B1 (en) * | 2002-06-20 | 2005-06-07 | Richard J. Nathan | Embedded carrier for an integrated circuit chip |
KR20060051422A (ko) | 2004-10-22 | 2006-05-19 | 신꼬오덴기 고교 가부시키가이샤 | 내장 칩을 갖고 그 양측에 외부 접속 단자를 갖는 기판과그 제조 방법 |
KR20060061374A (ko) | 2003-12-05 | 2006-06-07 | 이비덴 가부시키가이샤 | 다층 프린트 배선판 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7183658B2 (en) * | 2001-09-05 | 2007-02-27 | Intel Corporation | Low cost microelectronic circuit package |
TW575931B (en) * | 2002-10-07 | 2004-02-11 | Advanced Semiconductor Eng | Bridge connection type of chip package and process thereof |
DE10340129B4 (de) * | 2003-08-28 | 2006-07-13 | Infineon Technologies Ag | Elektronisches Modul mit Steckkontakten und Verfahren zur Herstellung desselben |
US7285321B2 (en) * | 2003-11-12 | 2007-10-23 | E.I. Du Pont De Nemours And Company | Multilayer substrates having at least two dissimilar polyimide layers, useful for electronics-type applications, and compositions relating thereto |
KR100888195B1 (ko) * | 2007-08-06 | 2009-03-12 | 한국과학기술원 | 능동소자가 내장된 유기기판 제조방법 |
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2006
- 2006-09-07 KR KR1020060086215A patent/KR100770874B1/ko not_active IP Right Cessation
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2007
- 2007-03-13 US US11/685,269 patent/US7751202B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19980071398A (ko) | 1997-02-17 | 1998-10-26 | 야스카와 히데아키 | 캐리어 필름 및 그것을 사용한 집적 회로 장치 |
US6903458B1 (en) * | 2002-06-20 | 2005-06-07 | Richard J. Nathan | Embedded carrier for an integrated circuit chip |
KR20060061374A (ko) | 2003-12-05 | 2006-06-07 | 이비덴 가부시키가이샤 | 다층 프린트 배선판 |
KR20060051422A (ko) | 2004-10-22 | 2006-05-19 | 신꼬오덴기 고교 가부시키가이샤 | 내장 칩을 갖고 그 양측에 외부 접속 단자를 갖는 기판과그 제조 방법 |
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US7751202B2 (en) | 2010-07-06 |
US20080062657A1 (en) | 2008-03-13 |
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