CN1750257A - 焊锡接垫上销子封装的组件、封装、基板结构及封装方法 - Google Patents

焊锡接垫上销子封装的组件、封装、基板结构及封装方法 Download PDF

Info

Publication number
CN1750257A
CN1750257A CNA2004101041503A CN200410104150A CN1750257A CN 1750257 A CN1750257 A CN 1750257A CN A2004101041503 A CNA2004101041503 A CN A2004101041503A CN 200410104150 A CN200410104150 A CN 200410104150A CN 1750257 A CN1750257 A CN 1750257A
Authority
CN
China
Prior art keywords
connection pad
substrate
conductor connection
conduction pin
solder bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2004101041503A
Other languages
English (en)
Other versions
CN100433317C (zh
Inventor
张国钦
江国宁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN1750257A publication Critical patent/CN1750257A/zh
Application granted granted Critical
Publication of CN100433317C publication Critical patent/CN100433317C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05023—Disposition the whole internal layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

本发明是关于一种焊锡接垫上销子封装的组件、封装、基板结构及封装方法，该具有增进可信度的半导体组件至少包括有一在表面上具有至少一导体接垫的第一基板；一在表面上具有至少一导体接垫的第二基板；至少一导电销子；和至少一焊锡凸块与位于第一基板的导体接垫接触，同时与位于第二基板的导体接垫接触，并环绕此至少一导电销子形成。

Description

焊锡接垫上销子封装的组件、封装、基板结构及封装方法
技术领域
本发明涉及一种半导体的组装，特别是涉及一种与覆晶封装和区域阵列封装有关的焊锡接垫上销子封装的组件、封装、基板结构及封装方法。
背景技术
于一封装过程中，覆晶封装技术主要是提供将一集成电路晶粒连接于一基板的方法。在覆晶封装方法上，在晶粒的主动面上形成有多个电性终端，即连接垫(pads)。而焊锡凸块则形成于每一个电性终端上。封装基板上则具有与晶粒上终端相互对应的多个终端接垫(terminal pads)。于封装时，晶粒被翻转，使得元件上的终端与封装基板上的接垫接触，然后，施加一热来让焊锡凸块热回流，使得封装基板与晶粒主动面间形成电性和机械接触。一底充(underfill)材料填充于封装基板与晶粒间，来加强封装基板与晶粒间的粘合，并重新分配不匹配的热负载，同时保护焊锡的连接。多个焊锡凸块形成在未具晶粒的封装基板面上的终端接垫上，并施加一热来让焊锡凸块热回流，使得覆晶封装与印刷电路板间形成电性和机械接触。熟习该项技艺者亦常将终端接垫称为焊锡接垫(solder pads)或接触接垫(contact pads)。
底充材料的填充常会增加封装时间和成本，且要将完成底充材料充填的晶粒进行重工是相当困难的。除此之外，覆晶封装过程，长期在湿热的情形下，常会吸附很多水气，造成介面的粘着性下降。当吸附有水气的覆晶封装进行焊锡热回流来与印刷电路板进行粘合时，高湿热应力常会被引入在一些已弱化的介面上。这些应力是因为晶粒与封装基板间的热膨胀系数的不匹配，和所吸附水气的膨胀。这些应力会超过介面强度，而于晶粒和底充间，或于底充与基板的介面间，或两者的介面形成细层。这细层会导引焊锡凸块上焊锡的流向，造成覆晶封装长期操作可性度下降。
假如不使用底充材料填充，则于晶粒和封装基板间仅余覆晶焊锡凸块提供两者的连接，且完全暴露于热制程中，会导致热应力的产生。重复的热制程，会造成焊锡凸块的毁坏，如金属疲劳的损坏，而于介面丧失粘着性，或是因为形变应力而导致焊锡凸块内部毁损。焊锡凸块的可性度与应力的拉伸/压缩行为造成周期性的热变形有关。
美国专利号码6,716,738和6,756,294更说明焊锡凸块的可性度与在焊锡接垫和焊锡凸块间的崩毁形状有关。一般，焊锡接垫至少含铜或铝金属。一凸块底层金属(under bump metallurgy，UBM)层粘合在接垫上，然后粘合在导电的焊锡凸块上。一凸块底层金属层至少包括复数个用以硬化粘接(metallization)的由其他金属所形成的薄层。一般而言，凸块底层金属粘着层(UBM adhesion layer)是被施加在接垫表面上，并且至少含有铬(Chromium)或钛(Tiantium)。实质上，凸块底层金属沾湿层(UBMwetting layer)是形成在凸块底层金属粘着层的顶表面上，用以增加焊锡的粘着力。传统上，凸块底层金属沾湿层至少包括有镍(Nickel)或铜(Cooper)金属。一金薄层被应用在凸块底层金属沾湿层上，以防止被氧化。
当焊锡凸块被形成在接垫上并进行热流，凸块底层金属层并不能够阻止焊锡与接垫间的分子扩散。除此之外，在周期性的重复热制程中，此扩散会持续进行。这会在邻接于焊锡/接垫接面处，形成一由内层金属化合物(intermetallic compounds)所构成的分子层。这些内层金属化合物分子层与焊锡相较，在结构上明显较弱，因此容易因应力而造成破损进而散布于这些层中。此问题会影响到覆晶封装与其后粘着于印刷电路板上的制程。
因此，对于一具高信度，且使用于焊锡凸块进行电性和机械性连接的方法存有需求。
由此可见，上述现有的覆晶封装技术在结构、方法与使用上，显然仍存在有不便与缺陷，而亟待加以进一步改进。为了解决覆晶封装技术存在的问题，相关厂商莫不费尽心思来谋求解决之道，但长久以来一直未见适用的设计被发展完成，而一般产品又没有适切的结构能够解决上述问题，此显然是相关业者急欲解决的问题。
有鉴于上述现有的覆晶封装技术存在的缺陷，本发明人基于从事此类产品设计制造多年丰富的实务经验及专业知识，并配合学理的运用，积极加以研究创新，以期创设一种新的焊锡接垫上销子封装的组件、封装、基板结构及封装方法，能够改进一般现有的覆晶封装技术，使其更具有实用性。经过不断的研究、设计，并经反复试作样品及改进后，终于创设出确具实用价值的本发明。
发明内容
本发明的目的在于，克服现有的覆晶封装技术存在的缺陷，而提供一种新的焊锡接垫上销子封装的组件、封装、基板结构及封装方法，所要解决的技术问题是使其使用于焊锡凸块进行电性和机械性连接，且具有高信度，从而更加适于实用。
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的一种组件结构，其至少包括：一第一基板，至少一导体接垫位在一表面上；一第二基板，至少一导体接垫位在一表面上；至少一导电销子，位于该第一基板和该第二基板其中之一的至少一个导体接垫上；以及至少一焊锡凸块，与位于该第一基板的该导体接垫接触，同时与位于该第二基板的该导体接垫接触，并环绕该至少一导电销子形成。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的组件结构，其中所述的至少一导电销子包括一第一导电销子粘合在该第一基板的该导体接垫上，和第二导电销子粘合在该第二基板的该导体接垫上，且该至少一焊锡凸块是环绕由该第一导电销子和该第二导电销子所形成群组的其中之一形成。
前述的组件结构，其中所述的第一基板为一半导体晶粒。
前述的组件结构，其中所述的组件为一覆晶封装结构，且其中的第二基板为一封装基板。
前述的组件结构，其中所述的第二基板为一印刷电路板。
前述的组件结构，其中所述的第一基板为一区域阵列封装的封装基板或一覆晶封装的封装基板。
前述的组件结构，其中所述的至少一导电销子的形状是从由圆形、正方形、长方形、菱形、椭圆形和多边形所组成的群组中选择出。
前述的组件结构，其中形成该至少一导电销子的材料，其材质比该焊锡凸块硬。
本发明的目的及解决其技术问题还采用以下的技术方案来实现。依据本发明提出的一种封装结构，其至少包括：一封装基板，在第一表面上具有一晶粒，而在相反于第一表面的第二表面上则具有至少一导体接垫；至少一导电销子位于该导体接垫上；以及至少一焊锡凸块与该导体接垫接触，其是环绕该至少一导电销子形成。
本发明的目的及解决其技术问题还采用以下的技术方案来实现。依据本发明提出的一种基板结构，其至少包括：至少一表面具有至少一导体接垫；至少一导电销子位于该至少一导体接垫上；以及至少一焊锡凸块，与该至少一导体接垫接触，并环绕该至少一导电销子形成。
本发明的目的及解决其技术问题还采用以下的技术方案来实现。依据本发明提出的一种封装方法，其至少包括以下步骤：提供一晶粒，在该晶粒的主动表面上具有至少一导体接垫；形成一导电销子在该导体接垫上；以及形成一焊锡凸块环绕该导电销子。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的封装方法，其中更包括形成一罩幕覆盖在该晶粒上，同时于该罩幕中具有一图案，其中该导电销子是藉由该罩幕形成。
本发明的目的及解决其技术问题还采用以下的技术方案来实现。依据本发明提出的一种封装方法，其至少包括以下步骤：提供一在一表面上具有至少一导体接垫的第一基板；形成至少一导电销子在该第一基板的部分该导体接垫上；以及环绕此导电销子施加一焊锡凸块在该第一基板的导体接垫至少一部分上。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的封装方法，其中更包括放置该焊锡凸块赖与一第二基板上的一导体接垫接触，和再热流该焊锡凸块，来使该第一基板和该第二基板形成电性和机械性接触，同时让导电销子位于该两基板中。
本发明与现有技术相比具有明显的优点和有益效果。由以上技术方案可知，为了达到前述发明目的，本发明的主要技术内容如下：
于一些实施例中，一组件至少包括有一在表面上具有至少一导体接垫的第一基板；一在表面上具有至少一导体接垫的第二基板；至少一位于导体接垫上的导电销子，其中此导体接垫是位于第一基板和第二基板的至少一个上；和至少一焊锡凸块与位于第一基板的导体接垫接触，同时与位于第二基板的导体接垫接触，并环绕此至少一导电销子形成。
于一些实施例中，一封装结构至少包括有一封装基板，在第一表面上具有一晶粒，而在相反于第一表面的第二表面上则具有至少一导体接垫；至少一位于导体接垫上的导电销子；和至少一与导体接垫接触的焊锡凸块，其是环绕此至少一导电销子形成。
于一些实施例中，一方法至少包括提供一在表面上具有至少一导体接垫的第一基板；形成一导电销子在导体接垫上；和环绕此导电销子形成一焊锡凸块。
于一些实施例中，一方法至少包括提供一在表面上具有至少一导体接垫的第一基板；形成至少一导电销子在第一基板的部分导体接垫上；环绕此导电销子，施加一焊锡凸块在第一基板的至少一部分导体接垫上；放置焊锡凸块与第二基板上的一导体接垫接触；和再热流焊锡凸块，来使第一基板和第二基板形成电性和机械性接触，同时让导电销子位于两基板中。
经由上述可知，本发明是有关于一种焊锡接垫上销子封装的组件、封装、基板结构及封装方法，该具有增进可信度的半导体组件至少包括有一在表面上具有至少一导体接垫的第一基板；一在表面上具有至少一导体接垫的第二基板；至少一导电销子；和至少一焊锡凸块与位于第一基板的导体接垫接触，同时与位于第二基板的导体接垫接触，并环绕此至少一导电销子形成。
综上所述，本发明特殊的焊锡接垫上销子封装的组件、封装、基板结构及封装方法，具高信度，且使用于焊锡凸块进行电性和机械性连接。其具有上述诸多的优点及实用价值，并在同类产品及方法中未见有类似的结构设计及方法公开发表或使用而确属创新，其不论在产品结构、方法或功能上皆有较大的改进，在技术上有较大的进步，并产生了好用及实用的效果，且较现有的覆晶封装技术具有增进的多项功效，从而更加适于实用，而具有产业的广泛利用价值，诚为一新颖、进步、实用的新设计。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图，详细说明如下。
附图说明
图1A和图1B均是根据本发明较佳具体实施例的组件剖面图。
图2是本发明另一较佳具体实施例的组件剖面图。
图3A和图3B均是根据本发明较佳具体实施例的覆晶组件剖面图。
图4是根据本发明另一较佳具体实施例的覆晶组件剖面图。
图5A和图5B均是根据本发明较佳具体实施例的组件剖面图，其中此组件包括一嵌合在印刷电路板上的封装结构。
图6是根据本发明另一较佳具体实施例的组件剖面图，其中此组件包括一嵌合在印刷电路板上的封装结构。
图7A是根据本发明的导电销子立体图，其中此箱子具有一交叉或圆形(如图7B所示)外观。
图7B至图7D是一剖面图，分别展示了一个导电销子、两个导电销子或三个导电销子形成在一传导接垫的情形。
图8A至图8E展示一个范例方法，其中一集成电路晶粒的至少一表面上具有至少一导电销子，而焊锡凸块则形成在此至少一导电销子的周围，且与此至少一导体接垫接触。
图9是根据本发明的一线图，其是显示各种圆形形状铜导电销子的半径与高度，在与导体接垫进行粘合时，对焊锡凸块的剪应力影响。
图10是根据本发明的一线图，其是显示各种交叉形状铜导电销子的半径与高度，在与导体接垫进行粘合时，对焊锡凸块的剪应力影响。
5、15、40、55、75、85、105：基板
120、140、150、170、190、205：基板
10、20、45、60、80、90、110：导体接垫
125、145、155、175、195、210：导体接垫
25、50、65、95、115、130、160、180、200、225：导电销子
30、70、100、135、165、185和230：焊锡凸块
151和152：区域阵列封装结构         206：焊锡罩幕
215：罩幕                          220：开口区域
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本发明所提出的焊锡接垫上销子封装的组件、封装、基板结构及封装方法其具体实施方式、结构、方法、步骤、特征及其功效，详细说明如后。
本发明具体实施例的描述应同时参阅图示，其亦为整份说明书的一部分。在本说明书中，比较性的词汇，如“较低的”、“较高的”、“水平的”、“垂直的”、“之上”、“之下”、“上”、“下”、“顶端”和“底端”和从其中衍生出的修饰语，例如，“水平地”、“向下地”和“向上地”等，课参考说明书中所描述的方位，同时亦可参阅图示的描述。然而使用这些比较性的词汇，是为了描述上的方便，并不用以限定本发明的外观或方位。有关“粘接”、“耦合”或其相近的词汇，例如，连结或内连结，除了说明书中有兔别的说明，否则其是指两结构以直接或间接的方式进行连接，其中间接是指中间相隔另一结构，而两者间是可移动或固定的连接。图中所示的相同参考数字是指相同的元件。
图1A和图1B每一图均展示一组件，其中每一组件至少包括一在表面上具有至少一导体接垫10的第一基板5；一在表面上具有至少一导体接垫20的第二基板15；和至少一嵌合于焊锡凸块30上的导电销子25，其中此焊锡凸块30是位于导体接垫10或20上。在第一基板5和第二基板15进行嵌合后，焊锡凸块30会与位于第一基板5的导体接垫10接触，同时与位于第二基板15的导体接垫20接触，并包括此至少一导电销子25。导电销子的高度是从5微米至60微米。
此导电销子25是用以补强连接第一基板5和第二基板15间的焊锡凸块机械强度，来对抗于热制程中所产生的剥离。
第一基板5和第二基板15可为任何的基板，例如包括，那些适合用来作为集成电路晶粒的基板、一封装基板或是一印刷电路板。如此的基板材料包括，但不限定于，陶瓷、玻璃、聚合物或半导体材料。在图1A中，导电销子25是形成在第一基板5的导体接垫10上，其中第一基板5是嵌合在第二基板15上，其中此第一基板5可例如为一集成电路晶粒。在图1B中，导电销子25是形成在第二基板15的导体接垫20上，其中第一基板5是嵌合在第二基板15上，而此第二基板15可例如为一封装基板。
在图1A中，导电销子25被包括在焊锡凸块30中，在未对第一基板5施加任何压力下，执行一热回流步骤，以于销子25和第二基板15的导体接垫20间形成一焊锡填充空间。而于可替代的结构中，亦可于第一基板5和第二基板15间形成一或多个空间(未展示于图中)，用以确保焊锡凸块30不会被压坏。相似的，在图1B中，在未对第一基板5施加任何压力下，执行一热回流步骤，以于销子25和第一基板5的导体接垫10间形成一焊锡填充空间。而亦可使用一空间支撑物(spacer)。
在图2中，在第一基板和第二基板的导体接垫上均具有一销子。图2展示一组件，其中此组件至少包括一在表面上具有至少一导体接垫45的第一基板40，其中至少一导电销子50粘合于此导体接垫45之上。此组件亦包括一在表面上具有至少一第二导体接垫60的第二基板55，且至少一导电销子65粘合于此第二导体接垫60之上。此组件更包括至少一焊锡凸块70，其中此焊锡凸块70不是环绕此至少一导电销子50形成，就是环绕此至少一导电销子65形成，并环绕导电销子50或65的另一个进行热回流。较佳地，焊锡凸块70是环绕形成在第一基板40上的导电销子50，而此第一基板40是嵌合在第二基板55上。
如上所述，图2的热回流步骤是在未对第一基板40施加任何压力下所执行，因此会销子50和销子65之间形成一焊锡填充空间。而于可替代的结构中，亦可于第一基板40和第二基板45间形成一或多个空间(未展示于图中)，用以确保焊锡凸块30不会被压坏，且可避免短路的情形。
在图3A、图3B和图4中，第一基板5为一集成电路晶粒，第二基板为一封装基板。图3A和图3B分别展示一覆晶组件，此覆晶组件至少包括一在表面上具有至少一导体接垫80的一晶粒75；一在表面上具有至少一导体接垫90的一基板85和至少一导电销子95。此组件包括至少一导体凸块，此导体凸块100和晶粒75上的导体接垫80相接触，亦与基板85上的导体接垫90相接触，且环绕至少一导电销子95形成。藉由使用导电销子95可使得覆晶组件并不需要使用底充材料(underfilled)，而仍可提供很强的机械性连接，并可抵抗锡球的剥离。此导电销子95可坚强覆晶封装焊锡凸块的可信度，且在不使用底充材料的封装结构中特别具有优点。当一由内层金属化合物(intermetallic compounds)层形成于焊锡/接垫间的介面时，此金属销子可阻挡破损经由此破损路径散布或蔓延。
请参阅图4所示，是一覆晶组件，此覆晶组件至少包括一在表面上具有至少一导体接垫110的一晶粒105，其中至少一导电销子115粘合在此导体接垫110之上。此组件亦包括一在表面上具有至少一导体接垫125的封装基板120，且至少一导电销子130粘合在此封装基板120的导体接垫125之上。此组件更包括至少一焊锡凸块135，此焊锡凸块135与导体接垫110和125相接，且此焊锡凸块135不是环绕此至少一导电销子115形成，就是环绕此至少一导电销子130形成。较佳地，焊锡凸块135是环绕形成于晶粒105上的导电销子115，并藉由热回流将导电销子115和130进行封装。
就如同描绘于图3A和图3B所示的覆晶组件结构，图4所示的组件结构亦可于晶粒105和封装基板120间提供高可性度的内连接，且可在不使用底充物的情形下，阻止于热制程过程中的剥离。
一熟悉该项技艺者，亦可了解到本发明的导电销子25亦可应用于具有底充材料的覆晶封装中，用以提供较大的机械可信度并阻挡产生剥离的可能。
在图5A、图5B和图6中，第一基板为一集成电路封装的封装基板，而第二基板为此封装基板要嵌合的印刷电路板。图5A和图5B分别展示一组件，此组件至少包括一印刷电路板150，而一区域阵列封装结构(area arraypackage)151粘合在此印刷电路板150上。此处所展示的区域阵列封装结构151范例是一个覆晶封装，然其他的区域阵列封装结构均可用于此处。此组件至少包括一在表面上具有至少一导体接垫145的一封装基板140；一在表面上具有至少一导体接垫155的一印刷电路板150和至少一导电销子160。此组件更包括至少一导体凸块165，此导体凸块165和封装基板140上的导体接垫145相接触，亦与印刷电路板150上的导体接垫155相接触，且环绕至少一导电销子160形成。
在一实施例中，请参阅图5A所示，封装结构151至少包括：一封装基板140，在第一表面上具有一晶粒，而在相反于第一表面的第二表面上则具有至少一导体接垫145；至少一位于导体接垫145上的导电销子160和至少一与导体接垫145接触的焊锡凸块165，其是环绕此至少一导电销子160形成。此封装结构151，藉由热回流焊锡凸块165与印刷电路板150相连接。
在一实施例中，图5B中，此导电销子160是形成于印刷电路板150上的导体接垫155，而一区域阵列封装结构152粘合在印刷电路板150上。其中区域阵列封装结构152，可为一传统的区域阵列封装结构或是其他的区域阵列封装结构，均可用于此处。
请参阅图6所示，是一封装组件和一印刷电路板，此封装形式可如图5A所示的封装形式，具有一销子180在导体接垫175上，并由焊锡凸块185所包覆。印刷电路板190可使用图5B所示的印刷电路板具有一销子200在导体接垫195上。此组件至少包括一封装结构，而此封装结构具有一封装基板170，在此封装基板170的表面上具有至少一导体接垫175，和至少一导电销子180粘合在此封装基板170的至少一导体接垫175之上。此组件亦包括一在表面上具有至少一导体接垫195的印刷电路基板190，和至少一导电销子200粘合在此印刷电路基板190的至少一导体接垫195之上。至少一焊锡凸块185环绕此导电销子180形成，并藉由热回流导电销子200，来使得导体接垫175和195相接。
此导电销子较佳地包括一导电材料，且此导电材料硬度会大于焊锡凸块，此材料可为铜、铝或金，但并不以此为限定。
请参阅图7A和图7B，此导电销子可有任何形式的交叉段落，包括如图7A所示的交叉形式，或图7B所示的圆形形式，但均不以此为限定，亦即其他交叉段落形式(图中未展示出)亦可用于本实施例中，例如正方形、长方形、菱形、椭圆形或多边形，但亦不以此为限定。除此之外，如同展示在图7C和图7D，超过一个的导电销子可被用来与导体接垫粘合。在图7C中，两个导电销子25形成在一导体接垫10上。在图7D中，三个导电销子25形成在一导体接垫10上。此外，如下所述般，导体销可具有多种交叉段落面积和长度形式，因为这些变化均会影响到可信度的改善。例如，导电销子具有一从10微米至100微米的交叉段落宽度。
请参阅图8A至图8E展示了根据本发明较佳实施例的一个制造粘合在基板导体接垫上的导电销子方法，在图8A中，基板205是一个具有焊锡罩幕(锡光阻)206于其上的集成电路晶粒，于焊锡罩幕206中具有至少一开口，而至少一导体接垫210则位在基板205上的至少一开口中。此焊锡罩幕206例如可为一液体形式或干燥形式的薄膜。液体形式的焊锡罩幕可使用如镜面印刷或其相近技术来加以形成。而此焊锡罩幕可以有机化合物，如环氧树脂，加以形成。例如，此焊锡罩幕可为一热固树脂(thermosettingresin)，在沉积后藉由加热加以固化。焊锡罩幕的材料可使用具有C-C、C-O、C-H或/和C-Si键结。本发明可使用如美国专利5,626,774号或美国专利6,346,678号中所介绍的焊锡罩幕形成方法。
在图8B中，展示了一罩幕215覆盖在焊锡罩幕206和导体接垫210的至少一部分上。此罩幕215包括一用以形成导电销子的开口区域220，利用图案化此罩幕215，可于开口220中提供任何意欲的交叉段落形状。本发明的罩幕215可采用任何形式罩幕，只要此罩幕能符合基板和本发明的沉积制程，例如此罩幕215可利用微影制程形成。而另一方面，罩幕层215亦可使用氧化硅、氮化硅或氮氧化硅材料制成，例如可藉由使用二氯硅甲烷(SiCl2H2，Dichlorosilane)和氨气(NH3)做为反应气体的化学气相沉积方法来形成罩幕层215。
在图8C中，展示了在一开口区域220中，藉由沉积一导体材料来制作导电销子225。罩幕215可控制导体材料的沉积总量和厚度，进而控制所形成的导电销子225的厚度(即高度)。一沉积导体材料的较佳方法是使用电镀的方法，而所使用的导体材料较佳为铜。而另一方面，化学气相沉积方法亦可用来形成导体材料。
在图8D中，展示了在移除罩幕215后，粘附在导体接垫210上的至少一导电销子225。假若罩幕215为一光阻，可使用传统的灰化制程来移除罩幕。
在图8E中，展示了一环绕形成在导电销子225周围的焊锡凸块230，其中此导电销子225粘附在导体接垫210上。可使用传统于一平板接垫上施加一凸块的制程方法在销子上形成凸块，此方法包括电镀法、镜面印刷法和球嵌合法等。
评估焊锡凸块的可信度，是使用于图4中，以铜作为导电销子115和130的覆晶组件且并不使用底充材料，而展示于图4中的两种结构形式，其热金属疲劳生命周期(thermal fatigue life cycles)是使用有限元件分析法(finite element analysis)来进行分析。第一种结构形式为采用圆形导体接垫，并在其上形成圆形铜导电销子；而第二种结构形式为采用圆形导体接垫，并在其上形成交叉形状(具有相同边长)的铜导电销子。
表1是根据本发明的一实验图表，其中的数字是代表根据图4结构，各种半径与高度情形下的圆形形状铜导电销子的金属疲劳生命周期。表2是根据本发明的一实验图表，其中的数字是代表根据图4结构，各种边长与高度情形下的交叉形状铜导电销子的金属疲劳生命周期。
其中，表1展示了第一种结构形式中，其热金属疲劳生命周期和圆形铜销子的高度与半径间的关系。表2展示了第二种结构形式中，其热金属疲劳生命周期和交叉形状铜销子的高度与边长间的关系。
表1
Figure A20041010415000131
表2
Figure A20041010415000132
两种比较结果均显示了，藉由在覆晶组件的焊锡凸块上使用适当大小的导电销子可明显强化热金属疲劳生命周期。此种可信度的改善，可提供一种于覆晶组件中不使用底充材料的机会，且于热制程中，不会有剥离风险的存在。
另一种明显的可信度争点是有关于在邻接于焊锡凸块和导体接垫接面处所形成的内层金属化合物，此内层金属化合物会若化整个焊锡结构同时造成崩坏。这使一个位于印刷电路板和嵌合封装结构间焊锡凸块的特定争点，广为人知的是，焊锡凸块/锡球剪应力测试方法曾被用来判定焊锡凸块/锡球的剪映力强度，并证明此争点。而焊锡凸块的有限元件分析法亦曾被引入，用以判定粘合在圆形导体接垫上的导电销子对焊锡凸块剪应力强度的影响。图9所示的线图，显示一圆形形状铜销子的半径与高度，在粘合于印刷电路板的导体接垫后，对焊锡凸块的剪应力影响。图10所示的线图，显示一交叉形状铜销子的边长与高度，在粘合于印刷电路板的导体接垫后，对焊锡凸块的剪应力影响。两种比较结果均显示了，藉由在覆晶组件的焊锡凸块上使用适当大小的导电销子可明显强化焊锡凸块的剪应力强度。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的方法及技术内容作出些许的更动或修饰为等同变化的等效实施例，但是凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (14)

1、一种组件结构，其特征在于其至少包括：
一第一基板，至少一导体接垫位在一表面上；
一第二基板，至少一导体接垫位在一表面上；
至少一导电销子，位于该第一基板和该第二基板其中之一的至少一个导体接垫上；以及
至少一焊锡凸块，与位于该第一基板的该导体接垫接触，同时与位于该第二基板的该导体接垫接触，并环绕该至少一导电销子形成。
2、根据权利要求1所述的组件结构，其特征在于其中所述的至少一导电销子包括一第一导电销子粘合在该第一基板的该导体接垫上，和第二导电销子粘合在该第二基板的该导体接垫上，且该至少一焊锡凸块是环绕由该第一导电销子和该第二导电销子所形成群组的其中之一形成。
3、根据权利要求1所述的组件结构，其特征在于其中所述的第一基板为一半导体晶粒。
4、根据权利要求3所述的组件结构，其特征在于其中所述的组件为一覆晶封装结构，且其中的第二基板为一封装基板。
5、根据权利要求1所述的组件结构，其特征在于其中所述的第二基板为一印刷电路板。
6、根据权利要求5所述的组件结构，其特征在于其中所述的第一基板为一区域阵列封装的封装基板或一覆晶封装的封装基板。
7、根据权利要求1所述的组件结构，其特征在于其中所述的至少一导电销子的形状是从由圆形、正方形、长方形、菱形、椭圆形和多边形所组成的群组中选择出。
8、根据权利要求1所述的组件结构，其特征在于其中形成该至少一导电销子的材料，其材质比该焊锡凸块硬。
9、一种封装结构，其特征在于其至少包括：
一封装基板，在第一表面上具有一晶粒，而在相反于第一表面的第二表面上则具有至少一导体接垫；
至少一导电销子位于该导体接垫上；以及
至少一焊锡凸块与该导体接垫接触，其是环绕该至少一导电销子形成。
10、一种基板结构，其特征在于其至少包括：
至少一表面具有至少一导体接垫；
至少一导电销子位于该至少一导体接垫上；以及
至少一焊锡凸块，与该至少一导体接垫接触，并环绕该至少一导电销子形成。
11、一种封装方法，其特征在于其至少包括以下步骤：
提供一晶粒，在该晶粒的主动表面上具有至少一导体接垫；
形成一导电销子在该导体接垫上；以及
形成一焊锡凸块环绕该导电销子。
12、根据权利要求11所述的封装方法，其特征在于其中更包括形成一罩幕覆盖在该晶粒上，同时于该罩幕中具有一图案，其中该导电销子是藉由该罩幕形成。
13、一种封装方法，其特征在于其至少包括以下步骤：
提供一在一表面上具有至少一导体接垫的第一基板；
形成至少一导电销子在该第一基板的部分该导体接垫上；以及
环绕此导电销子施加一焊锡凸块在该第一基板的导体接垫至少一部分上。
14、根据权利要求13所述的封装方法，其特征在于其中更包括放置该焊锡凸块赖与一第二基板上的一导体接垫接触，和再热流该焊锡凸块，来使该第一基板和该第二基板形成电性和机械性接触，同时让导电销子位于该两基板中。
CNB2004101041503A 2004-09-14 2004-12-30 焊锡接垫上销子封装的组件、封装、基板结构及封装方法 Active CN100433317C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/941,586 US20060055032A1 (en) 2004-09-14 2004-09-14 Packaging with metal studs formed on solder pads
US10/941,586 2004-09-14

Publications (2)

Publication Number Publication Date
CN1750257A true CN1750257A (zh) 2006-03-22
CN100433317C CN100433317C (zh) 2008-11-12

Family

ID=36033038

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004101041503A Active CN100433317C (zh) 2004-09-14 2004-12-30 焊锡接垫上销子封装的组件、封装、基板结构及封装方法

Country Status (3)

Country Link
US (1) US20060055032A1 (zh)
CN (1) CN100433317C (zh)
TW (1) TW200610078A (zh)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7820543B2 (en) 2007-05-29 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced copper posts for wafer level chip scale packaging
US8053906B2 (en) 2008-07-11 2011-11-08 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for processing and bonding a wire
US8110931B2 (en) 2008-07-11 2012-02-07 Advanced Semiconductor Engineering, Inc. Wafer and semiconductor package
US8241963B2 (en) 2010-07-13 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed pillar structure
US8299616B2 (en) 2010-01-29 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. T-shaped post for semiconductor devices
US8318596B2 (en) 2010-02-11 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
CN103094260A (zh) * 2011-10-31 2013-05-08 台湾积体电路制造股份有限公司 层叠封装器件及封装半导体管芯的方法
US8492263B2 (en) 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
CN103887191A (zh) * 2012-12-20 2014-06-25 新科金朋有限公司 半导体器件和制作无凸块倒装芯片互连结构的方法
US8803319B2 (en) 2010-02-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
CN104681530A (zh) * 2013-11-26 2015-06-03 日月光半导体制造股份有限公司 半导体结构及其制造方法
US9230932B2 (en) 2012-02-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods
US10453815B2 (en) 2012-04-20 2019-10-22 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for solder connections
CN116705743A (zh) * 2023-08-04 2023-09-05 深圳平创半导体有限公司 一种器件及其封装方法

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4817892B2 (ja) * 2005-06-28 2011-11-16 富士通セミコンダクター株式会社 半導体装置
KR100664500B1 (ko) * 2005-08-09 2007-01-04 삼성전자주식회사 돌기부를 갖는 메탈 랜드를 구비하는 인쇄회로기판 및 그의제조방법
TW200711154A (en) * 2005-09-08 2007-03-16 Advanced Semiconductor Eng Flip-chip packaging process
US8174119B2 (en) * 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
US8193034B2 (en) 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
JP2008192984A (ja) * 2007-02-07 2008-08-21 Elpida Memory Inc 半導体装置及びその製造方法
TW200836275A (en) * 2007-02-16 2008-09-01 Chipmos Technologies Inc Packaging conductive structure and method for manufacturing the same
US8709934B2 (en) * 2007-06-05 2014-04-29 Stats Chippac Ltd. Electronic system with vertical intermetallic compound
US20090127695A1 (en) * 2007-11-19 2009-05-21 Patrick Kim Surface mount package with enhanced strength solder joint
KR100924552B1 (ko) * 2007-11-30 2009-11-02 주식회사 하이닉스반도체 반도체 패키지용 기판 및 이를 갖는 반도체 패키지
TWI405311B (zh) * 2008-11-04 2013-08-11 半導體裝置、嵌埋電子元件之封裝結構、及其製法
TWI584434B (zh) * 2010-04-20 2017-05-21 瑞鼎科技股份有限公司 晶粒結構及晶粒接合方法
US9142533B2 (en) 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
US8519542B2 (en) * 2010-08-03 2013-08-27 Xilinx, Inc. Air through-silicon via structure
FR2964094B1 (fr) * 2010-08-31 2012-09-28 Commissariat Energie Atomique Assemblage d'objets par l'intermediaire d'un cordon de scellement comportant des composes intermetalliques
KR101695353B1 (ko) * 2010-10-06 2017-01-11 삼성전자 주식회사 반도체 패키지 및 반도체 패키지 모듈
US9184144B2 (en) 2011-07-21 2015-11-10 Qualcomm Incorporated Interconnect pillars with directed compliance geometry
US20130020698A1 (en) * 2011-07-22 2013-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar Design for Conductive Bump
US8912651B2 (en) * 2011-11-30 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure including stud bulbs and method
US9583425B2 (en) 2012-02-15 2017-02-28 Maxim Integrated Products, Inc. Solder fatigue arrest for wafer level package
US8643150B1 (en) * 2012-02-15 2014-02-04 Maxim Integrated Products, Inc. Wafer-level package device having solder bump assemblies that include an inner pillar structure
US9646923B2 (en) 2012-04-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9299674B2 (en) 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect
US9171790B2 (en) 2012-05-30 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
JP5980634B2 (ja) * 2012-09-14 2016-08-31 富士通コンポーネント株式会社 プリント基板
US9111817B2 (en) 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
CN102915986B (zh) * 2012-11-08 2015-04-01 南通富士通微电子股份有限公司 芯片封装结构
US9806045B2 (en) * 2013-08-29 2017-10-31 Taiwan Semiconductor Manufacturing Company Ltd. Interconnection structure including a metal post encapsulated by solder joint having a concave outer surface
JP6439389B2 (ja) * 2014-11-05 2018-12-19 富士電機株式会社 半導体装置
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
FR3041625B1 (fr) * 2015-09-29 2021-07-30 Tronics Microsystems Dispositif de fixation de deux elements tels qu'une puce, un interposeur et un support
US9984987B2 (en) 2016-08-05 2018-05-29 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
TWI822659B (zh) 2016-10-27 2023-11-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
JP2018195673A (ja) * 2017-05-16 2018-12-06 富士通株式会社 バンプ及びその形成方法、並びに基板
US10937735B2 (en) * 2018-09-20 2021-03-02 International Business Machines Corporation Hybrid under-bump metallization component

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5476211A (en) * 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
JP2716336B2 (ja) * 1993-03-10 1998-02-18 日本電気株式会社 集積回路装置
US5716738A (en) * 1995-06-21 1998-02-10 Texas Instruments Incorporated Dark rims for attenuated phase shift mask
US6038931A (en) * 1997-09-11 2000-03-21 International Business Machines Corporation Method and apparatus for the testing of plastically deformable objects
JPH11297889A (ja) * 1998-04-16 1999-10-29 Sony Corp 半導体パッケージおよび実装基板、ならびにこれらを用いた実装方法
IE20000263A1 (en) * 1999-04-07 2000-11-15 Mv Res Ltd A system and method for the inspection of dielectric materials
US6734540B2 (en) * 2000-10-11 2004-05-11 Altera Corporation Semiconductor package with stress inhibiting intermediate mounting substrate
US6756294B1 (en) * 2002-01-30 2004-06-29 Taiwan Semiconductor Manufacturing Company Method for improving bump reliability for flip chip devices
KR100476301B1 (ko) * 2002-07-27 2005-03-15 한국과학기술원 전기도금법에 의한 반도체 소자의 플립칩 접속용 ｕｂｍ의형성방법
US6784535B1 (en) * 2003-07-31 2004-08-31 Texas Instruments Incorporated Composite lid for land grid array (LGA) flip-chip package assembly
KR100568006B1 (ko) * 2003-12-12 2006-04-07 삼성전자주식회사 플립 칩 패키지의 오목형 솔더 범프 구조 형성 방법
US20050224967A1 (en) * 2004-04-01 2005-10-13 Brandenburg Scott D Microelectronic assembly with underchip optical window, and method for forming same

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7932601B2 (en) 2007-05-29 2011-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced copper posts for wafer level chip scale packaging
CN101315915B (zh) * 2007-05-29 2011-06-08 台湾积体电路制造股份有限公司 半导体装置
US7820543B2 (en) 2007-05-29 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced copper posts for wafer level chip scale packaging
US8492263B2 (en) 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
US9136211B2 (en) 2007-11-16 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
US8053906B2 (en) 2008-07-11 2011-11-08 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for processing and bonding a wire
US8110931B2 (en) 2008-07-11 2012-02-07 Advanced Semiconductor Engineering, Inc. Wafer and semiconductor package
US8299616B2 (en) 2010-01-29 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. T-shaped post for semiconductor devices
US8546945B2 (en) 2010-02-11 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US8803319B2 (en) 2010-02-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US8318596B2 (en) 2010-02-11 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US8921222B2 (en) 2010-02-11 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US8241963B2 (en) 2010-07-13 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed pillar structure
CN103094260A (zh) * 2011-10-31 2013-05-08 台湾积体电路制造股份有限公司 层叠封装器件及封装半导体管芯的方法
US9230932B2 (en) 2012-02-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods
US10340226B2 (en) 2012-02-09 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods
US11257767B2 (en) 2012-02-09 2022-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods
US10453815B2 (en) 2012-04-20 2019-10-22 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for solder connections
CN103887191A (zh) * 2012-12-20 2014-06-25 新科金朋有限公司 半导体器件和制作无凸块倒装芯片互连结构的方法
CN104681530A (zh) * 2013-11-26 2015-06-03 日月光半导体制造股份有限公司 半导体结构及其制造方法
CN104681530B (zh) * 2013-11-26 2017-09-26 日月光半导体制造股份有限公司 半导体结构及其制造方法
CN116705743A (zh) * 2023-08-04 2023-09-05 深圳平创半导体有限公司 一种器件及其封装方法

Also Published As

Publication number Publication date
CN100433317C (zh) 2008-11-12
US20060055032A1 (en) 2006-03-16
TW200610078A (en) 2006-03-16

Similar Documents

Publication Publication Date Title
CN1750257A (zh) 焊锡接垫上销子封装的组件、封装、基板结构及封装方法
CN100341127C (zh) 半导体器件
CN1231953C (zh) 形成倒装式半导体封装的方法
TWI527175B (zh) 半導體封裝件、基板及其製造方法
CN1790651A (zh) 芯片集成基板的制造方法
US20060068522A1 (en) Semiconductor device with improved heat dissipation, and a method of making semiconductor device
CN1700466A (zh) 半导体封装体及其形成方法
CN1445851A (zh) 轻薄叠层封装半导体器件及其制造工艺
US8039972B2 (en) Printed circuit board and method thereof and a solder ball land and method thereof
CN1512580A (zh) 半导体装置及其制造方法
CN1301540C (zh) 倒装芯片封装方法及其使用的衬底及不沾焊料的印刷网版
US11139281B2 (en) Molded underfilling for package on package devices
CN1320965A (zh) 半导体封装及其制造方法
TW201218468A (en) Semiconductor chip assembly with bump/base heat spreader and cavity in bump
CN1945805A (zh) 半导体封装方法以及用于半导体封装的载体
CN102456804A (zh) 封装体、发光二极管封装结构及封装体的制造方法
JP5822656B2 (ja) 半導体装置及びその製造方法
CN1956177A (zh) 芯片结构、芯片封装结构及其工艺
CN1451178A (zh) 改进的倒装芯片连接封装
CN1172369C (zh) 具散热片的半导体封装件
CN1848413A (zh) 覆晶球格阵列封装构造中具有晶体配向(100)的应变硅晶圆
TWI424549B (zh) 改良導線的二極體封裝及其製作方法
CN1257540C (zh) 一种半导体芯片封装方法及其封装结构
CN1330398A (zh) 管芯级封装及其制造方法
CN1835211A (zh) 电子装置的电路板及制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant