CN1301540C - 倒装芯片封装方法及其使用的衬底及不沾焊料的印刷网版 - Google Patents

倒装芯片封装方法及其使用的衬底及不沾焊料的印刷网版 Download PDF

Info

Publication number
CN1301540C
CN1301540C CNB2003101154598A CN200310115459A CN1301540C CN 1301540 C CN1301540 C CN 1301540C CN B2003101154598 A CNB2003101154598 A CN B2003101154598A CN 200310115459 A CN200310115459 A CN 200310115459A CN 1301540 C CN1301540 C CN 1301540C
Authority
CN
China
Prior art keywords
substrate
flip chip
mounting method
chip mounting
scolding tin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB2003101154598A
Other languages
English (en)
Other versions
CN1574255A (zh
Inventor
苏昭源
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN1574255A publication Critical patent/CN1574255A/zh
Application granted granted Critical
Publication of CN1301540C publication Critical patent/CN1301540C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3485—Applying solder paste, slurry or powder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0465—Shape of solder, e.g. differing from spherical shape, different shapes due to different solder pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1216—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by screen printing or stencil printing
    • H05K3/1225—Screens or stencils; Holders therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本发明揭示一形成填充底胶的倒装芯片封装方法及其所使用的衬底及不沾焊料的印刷网版。所述倒装芯片封装方法包含提供一衬底，该衬底上具有完全或至少露出部分于表面的导电焊垫，形成一自衬底伸出且呈锥形的预上锡膏于导电焊垫上方，接着形成一含二氧化硅填充料的填胶材料于衬底上，提供含导电凸块的芯片，将芯片附着于衬底上，接着回焊该预上锡膏以完整地附着导电凸块及导电焊垫，借此更硬化该填胶材料。当该芯片接合于衬底时导电凸块会对准于预上锡膏。

Description

倒装芯片封装方法及其使用的衬底及不沾焊料的印刷网版
技术领域
本发明是有关一种倒装芯片封装方法，特别是形成一填胶材料于衬底上的方法以减少芯片与衬底间的焊锡接点所含的二氧化硅填充料污染物。
背景技术
随着高密度、高功率的电子构装的迫切需求，倒装芯片(Flip Chip)封装技术已被广泛使用于许多领域。如其名所意指，倒装芯片封装是将裸晶(bare die)以表面朝下的方式借由软焊料的连接附着于衬底(substrate)上，以行接合物的连接。然而，如所知，当使用有机材料为衬底(organic substrate)时，软焊料连接过程中的温度循环会发生热胀冷缩。此热胀冷缩是由于有机衬底的热膨胀系数(CTE；coefficient ofthermal expansion)约为14-17ppm/℃，与硅芯片的CTE(约为4ppm/℃)差距过大。因此可知，CTE不匹配所引发的应力很容易导致接点损坏。
因此，为减少连接产生的应力并增加可靠度，通常需要在衬底与芯片的间隙内填入底胶。利用此法，可将应力分散至胶体，借以降低接点所受到的应力。如此便可减少接点破裂(crack)，而延长接点的疲劳寿命。此外，上述底胶是绝缘物质，亦可防止接点间有杂质造成漏电流的传递。既有数据显示，有填底胶的结构较无填底胶者其可靠性(reliability)高5-10倍。因此，填底胶已成为高需求的方法。然而，于不同的填底胶方法及硬化填胶材料以行连接的方式会分别产生问题。
一般而言，大多数的倒装芯片封装以低黏性的液态填胶材料利用点胶(dispensing)方式沿芯片外围填底胶。利用液体在芯片与衬底间微细间隙(小于100微米)所形成的毛细作用作为驱动力，以填满接点间的间隙。因由毛细作用引导的充填十分缓慢。当芯片大小增加时此问题会更严重，因为填充时间会随芯片尺寸增加而增加，此乃因填胶材料填充间隙所须流动的距离增加所致。
例如，在一典型的充填作业中，一个7mm见方的芯片，视液胶温度而定充填需时数分钟至十数分钟。仅以毛细作用不足以驱动较大的填底区域，因为流压无法充分维持，气泡(void)容易形成于填胶材料中。该气泡很可能在后续的热方法时造成封装体的爆米花效应(popcorn)使封装体失效，或于封装体承受应力时因应力集中而加速破坏造成失效。另外，表面污染物例如助焊剂残余物，会降低润湿作用并妨碍填胶材料流填底，使产生气泡，造成不充足的表面接触而减低结合力量。因此，对可靠度会有不良的影响。
利用所谓的非流动性(no-flow)填底胶技术可用来解决上述问题，其执行步骤如下述：(1)形成一填胶材料于衬底上；(2)将芯片附着于衬底上(3)将焊锡回焊。非流动性填底胶技术的填胶材料通常为低黏性及热固性的环氧化物，其包含助焊剂成分以促进焊锡回焊步骤。一倒装芯片封装的填胶方法时间可借由在将芯片形成于衬底前先将填胶材料附着于衬底而减少。借此亦可减少气泡产生于填胶材料中。
不幸的是，非流动性的填底胶技术会导致其它问题，如对倒装芯片封装中的可靠度上及电性功能有负面影响。传统封装或倒装芯片封装中，二氧化硅填充料通常会添加于填胶材料中再进而调和芯片及填胶材料的热膨胀系数。一非流动性填底胶技术的填胶材料亦包含二氧化硅填充料。当芯片附着于衬底时，填胶材料中的二氧化硅填充料通常陷入于芯片的导电凸块及焊垫或预上锡膏的衬底之中。当导电凸块及预上锡膏的焊垫回焊时二氧化硅填充料会存在于倒装芯片封装的焊锡接点中，而造成可靠度及电性功能如倒装芯片封装中的焊锡接合的电阻的负面影响。
图1A至图1F为一系列的剖面图说明于倒装芯片封装的填胶步骤使用非流动性技术时，二氧化硅填充料如何陷入倒装芯片封装的芯片及衬底间的焊锡接点。
在图1A中，一已备有焊锡掩模124及焊锡掩模开口123于表面上的衬底120。焊垫121形成于衬底120的表面上，其经焊垫掩模开123完全露出，接着预上锡膏122行成于焊垫121上。当焊垫121完全由焊锡掩模开口123露出时此焊垫121为NSMD(非防焊设计)型。预上锡膏122是视需要而(非必须地)形成于焊垫121上。而且，预上锡膏122通常具有近乎平坦的表面。
在图1B中，非流动性技术的填胶材料130以习知的方式形成于衬底上120。如所知，二氧化硅填充料132会随机分布于填胶材料130中。
在图1C中，半导体芯片110的主动表面上具有用以附着于衬底120上的导电凸块111。此导电凸块111更进一步附着于预上锡膏122上。如图解说明，二氧化硅填充料132于预上锡膏122上方及导电凸块111旁。
在图1D中，回焊预上锡膏122并与导电凸块111结合以形成焊锡接点140。当导电凸块111中包含焊锡材料时此凸块亦会被回焊。非流动性填底胶技术的填胶材料130通常含助焊剂成分以降低于预上锡膏金属122及金属导电凸块111之间在回焊期间的表面张力。预上锡膏122(及导电凸块111)的液化及预上锡膏122与导电凸块111的结合皆很快，预上锡膏122的平坦表面使得排除预上锡膏122上方及导电凸块111旁的二氧化硅填充料132变得困难。此造成于导电凸块111下方及预上锡膏122的二氧化硅填充料陷入焊锡接点140中，而导致焊锡接点140的可靠度及电性表现上的负面影响。
在图1E中，显示一包含SMD(防焊设计)的焊垫121′，由焊垫掩模124的焊垫开口123′部分露出形成。一预上锡膏122′视需要(而非必须地)形成于焊垫121上。而且，预上锡膏122通常具有一近乎平坦的表面。当半导体芯片110的导电凸块111附着于焊垫121′时，于导电凸块111下方及预上锡膏122′仍有一些二氧化硅填充料132。
在图1F中，当回焊预上锡膏122′以结合导电凸块111形成焊锡接点140′时，一些二氧化硅填充料会因图1D中所叙述的相同理由而被陷入于焊锡接点140′中。
美国专利6489,180中揭露另一种利用非流动性的填底胶技术的倒装芯片封装。利用图2A至图2G为一系列的剖面图，说明与美国专利6489,180中所揭露相同的非流动性填底胶技术的倒装芯片封装方法。
在图2A中，提供一适用于倒装芯片封装的衬底220。衬底220表面上包含焊锡掩模224及焊垫221。当焊垫221完全为焊锡掩模开口223所暴露时，此焊垫221为NSMD型。
在图2B中，一导电的导电的尖点凸块222形成于焊垫221上。此导电的尖点凸块222可由传统的金属线结合方法或其它方法制造。当利用传统的金属线结合方法时，导电的尖点凸块222由金或铝形成。
在图2C中，一填胶材料230提供于衬底220表面上，以将焊垫221及导电的尖点凸块222覆盖。填胶材料230可以点胶法或其它方法提供。此填胶材料230中包含随机分布于其内的二氧化硅填充料232，以使图2D中的芯片210及填胶材料230的热膨胀系数相配。
在图2D中，一具有焊锡凸块211的半导体芯片210以芯片上层向下的方式对准于焊垫221并附着于衬底220上。接着将该半导体芯片210对着衬底强制重压以使导电的尖点凸块222穿入焊锡凸块221中。如图所示，有些硅填充材料232会在焊锡凸块211导电的尖点凸块222及焊垫221的周围。
在图2E中，为焊锡回焊步骤，回焊焊垫221上的焊锡凸块211，使半导体芯片210与衬底220形成电性连接，此连结乃由熔化的焊锡凸块211沿导电的尖点凸块222及焊垫221的表面，向下流动而产生。而影响熔化的锡焊凸块211的流速有两个主要的因素。其中的一为沿着导电的尖点凸块222及结合焊垫221表面的熔化的焊锡凸块的毛细作用，另一因素为熔化的焊锡凸块211的重量。不幸的，此两因素以大体上相同的方向作用于熔化的焊锡凸块上，加速熔化的焊锡凸块211的流速。于焊锡掩模224与焊垫221间、及焊锡凸块211与焊垫221间的硅填充材料232，于回焊步骤后陷入于焊锡凸块211中对于焊锡凸块211与焊垫221的连接造成不良影响，劣化了倒装芯片封装250a中电性表现及焊锡接点的可靠度。此外，如所示，导电的尖点凸块222不会被回焊并保留先前的形状。此尖点A仍然存在于倒装芯片封装的250a′的焊锡接点中，该点在焊锡凸块211受到应力作用时会导致应力集中。更对倒装芯片封装中250a′的焊锡接点的可靠度负面影响。
图2F中说明与上述稍微不同的情形，其中衬底220是包含部分为焊锡掩模224的开口223′所暴露的SMD型焊垫221′。一导电的尖点凸块222′由传统的金属线结合法或其它方法形成于焊垫221′上，当以传统的金属线结合法制造时需使用金或铝。将半导体芯片210对着衬底200强制重压以使导电的尖点凸块222穿入焊锡凸块221中，在此有些硅填充材料232亦会于焊锡凸块211、导电的尖点凸块222，及焊垫221的周围。
如图2G所示，焊锡回焊步骤，回焊焊垫221上的焊锡凸块211′，使半导体芯片210与衬底220形成电性连接。于此步骤中，一些硅填充材料232因为与图2E中所述的相同理由，于回焊步骤后陷入于焊锡凸块211中。此填胶材料中的二氧化硅填充料会影响结合焊电221′与焊锡凸块211连接的完整性，导致倒装芯片封装250b中焊锡接点可靠度的劣化。此外，如图所示，该导电的尖点凸块222′不会被回焊并保留先前的形状，而此尖点A′仍然存在于倒装芯片封装的250b′的焊锡接点中，该点在焊锡凸块211受到应力作用时会导致应力集中。更对倒装芯片封装中250b′的焊锡接点的可靠度造成负面影响。
发明内容
本发明的主要目的是提供一种倒装芯片封装方法及其所使用的衬底，适用于底胶填充(underfill)，完成填底胶时二氧化硅填充料不会陷入于倒装芯片封装中的焊锡接点中，以改善倒装芯片封装中焊锡接点的可靠度。
本发明的另一目的是提供一种倒装芯片封装方法以形成一填底胶材料及衬底，当焊锡接点受到应力作用时避免应力集中于倒装芯片封装中的焊锡接点，以提升倒装芯片封装产品的可靠度与使用寿命。
为达成本发明的上述目的，本发明提供一种倒装芯片封装方法，适用于底胶填充。达成本发明，是主要在方法中提供或形成一预上锡膏于衬底的焊垫上，上述的预上锡膏呈锥形轮廓。另外，在形成填底胶材料(含硅填充材料)之后，预上锡膏对准于导电凸块并附着于倒装芯片封装的封装衬底上。之后，回焊方法缓慢地熔化上述预上锡膏并将其回焊至与其对准的导电凸块中。此缓慢回焊，连接锥形的预上锡膏形成一无(或大致上无)二氧化硅填充物的单一焊锡接点。
本发明还提供一衬底，适用于倒装芯片封装方法，以减少一芯片与该衬底间焊锡接点的二氧化硅填充料污染，其特征在于所述衬底包含：一导电焊垫，设于该衬底上；以及一预上锡膏物，自该衬底的导电焊垫上方伸出且呈锥形。
本发明还提供一不沾焊料的印刷网版，用于倒装芯片封装方法以减少在芯片与衬底间的焊锡接点过程中二氧化硅填充料上的污染物，其特征在于所述印刷网版包含：一反向漏斗形间隙，其具有一顶部开口；以及一大于顶部开口的底部开口。
附图说明
图1A至图1F是一系列剖面图，其显示利用非流动性填底胶技术的倒装芯片封装填胶步骤，其中二氧化硅填充料是陷入倒装芯片封装中的芯片及衬底间的焊锡接点；
图2A至图2G是利用相似于美国专利6,489,180中所揭露的非流动性的填底胶技术倒装芯片封装方法的剖面图；
图3A至图3G是一形成填底胶材料的倒装芯片封装方法其为本发明的实施例的剖面及一上示图；
图4A至图4C是形成一根据本发明的第二实施例的填底胶材料的倒装芯片封装方法的剖面图。
符号说明：
110～半导体芯片
111～导电凸块
120～衬底
121，121′～焊垫
122～预上锡膏
123，123′～焊锡掩模开口
124～焊锡罩
130～填胶材料
132～焊锡接点
140，140′～二氧化硅填充料
210～芯片
211，211′～焊锡凸块
220～衬底
221，221′～结合焊
222，222′～导电的尖点凸块
223，223′～焊锡掩模开口
224～焊锡掩模
230～填胶材料
232～二氧化硅填充料
250a～倒装芯片封装
250b～倒装芯片封装
A′～尖点
310～半导体芯片
311～导电凸块
320～衬底
321～焊垫
322～预上锡膏
323～焊锡掩模开口
324～焊锡罩
325～焊锡膏
330～填胶材料
340～焊锡接点
350～印刷网版
351～印刷网版较小开口
352～印刷网版较大开口
353～印刷网版腔室
355～刮刀
410～芯片
420～衬底
421～焊垫
422～预上锡膏
423～焊锡掩模开口
424～焊锡掩模
430～填胶材料
440～焊锡接点
具体实施方式
图3A至图3G显示本发明第一实施例的利用倒装芯片封装方法步骤，其中该方法是适用于填充底胶。本发明是提供一倒装芯片封装方法的手段以形成一底胶封装材料，而不会在焊锡接点中造成二氧化硅填充材的污染。本发明所形成的倒装芯片封装可更进一步防止因焊锡接点受到应力作用时所导致的应力集中所产生的危险点及界面，以使倒装芯片封装具有较佳的电性表面、较高的可靠度、及较长的寿命。
在图3A中，提供一衬底320，于其上表面包含焊锡掩模324及焊锡掩模开口323的衬底320。亦提供一焊垫321于焊锡掩模开口323内，且焊垫321是完全为焊锡掩模开口323所暴露，焊垫321为NSMD型，该焊垫321通常包含铜。
如图3B所示，提供一具有导电性的印刷网版350以定义反向漏斗型空隙。印刷网版350是使用于填胶方法的中间步骤，以适当的一相对位置与衬底320接触，例如将大的(底部)开口352与衬底320接触而使小的(顶部)开口远离衬底320。大致上该锥形空隙353形成于大的(底部)开口352与小开口351之间，如图3B所示，较大的开口对准于焊垫321并置于衬底320上。
在以下的叙述，印刷网版350用来形成具尖顶的预上锡膏。当印刷网版350附着于衬底320上时，该大的(底部)开口352最好够大以覆盖焊锡掩模开口323。接下来，将较好为包含锡铅合金或无铅的锡基合金等焊锡材料的焊锡膏325形成于焊垫上。利用括刀355使焊锡膏325扫过由衬底320与印刷网板350形成的组合物的顶部，并迫使焊锡膏325进入腔室353中以填满反向漏斗型印刷网版定义的空隙中。
在图3C中，回焊焊锡膏325以于焊垫321上形成一呈锥形且末为尖端的预上锡膏322。接着将印刷网版350与衬底320分开。此印刷网版最好为不锈钢涂覆有不具焊接特性的材料金属，以避免于回焊过程中，将焊锡高325焊于其上。一较佳的预上锡膏322于透视图3D中图解说明，但其并不受限于此。本发明亦可利用其它形状的预上锡膏来改善应力及提供其它优点，此技术乃熟习该技艺人士可领会的。
在图3E中，形成一的填胶材料330其中含有用于非流动性填充底胶技术的二氧化硅填充料332，并借由点胶法及其它已知方法将其铺于衬底320上。如图中所描绘二氧化硅填充料332随机分布于填胶材料330中。
如图3F所示，一半导体芯片310附着于衬底320上并包含一导电凸块311于主动的表面上。导电凸块311进一步对准并附着于预上锡膏322上。如图3F所说明，由于来自导电凸块311的压力对预上锡膏322的作用，使得抗导电凸块311的预上锡膏322尖顶稍变平坦。亦如图所说明，在此方法的阶段中，会有些二氧化硅填充材料332于预上锡膏322上及导电凸块311周围。导电凸块311最好为焊锡材料，金，铜，涂上焊锡材料的金，或涂上焊锡材料的铜。而焊锡材料最好为锡铅合金或无铅的锡基合金。
在图3G中所说明的方法步骤，回焊预上锡膏322以与导电凸块311结合而形成焊锡接点340。其中焊锡接点340的形成乃由熔化的预上锡膏322沿导电凸块311表面向下流动而产生。而影响熔化的预上锡膏322的流速有两个主要的因素。其中之一为沿着导电凸块311表面的熔化的预上锡膏322的毛细作用，另一因素为熔化的预上锡膏322的重量。此两力量大致为相反(在方向上)因而减少熔化的预上锡膏322的流速。因此，预上锡膏322及导电凸块311的连接会变慢。而预上锡膏322其呈锥形的轮廓再与导电凸块311的接触点附近呈为一倾斜面，而使预上锡膏322上及导电凸块311周围的二氧化硅填充料322在上述回焊过程中容易被排除。而造成无(或实际上无)二氧化硅填充料332陷入于焊锡接点中，而达成本发明的主要目的。
在导电凸块311由适当的焊锡材料例如：锡铅合金、无铅的锡基合金组成时，于预上锡膏321回焊期间导电凸块311亦会回焊。于预上锡膏322回焊期间导电凸块311亦会回焊，熔化的导电凸块311往下流而与熔化的预上锡膏322的流向相反，因此进一步使预上锡膏322与导电凸块311的连接变慢。结合预上锡膏321与导电凸块311的相反且较慢的流速的结合作用中、与呈锥形的预上锡膏332的作用是确保了可将二氧化硅填充材料排除于焊锡接点340之外，以达成本发明的重要目的。
非流动性填底胶技术的填胶材料330较好为含有助焊剂的成分，可于回焊时熔化的预上锡膏322及(熔化的)导电凸块间的表面张力。而填胶材料330于回焊期间亦会硬化。预上锡膏322回焊至导电凸块以产生成一体的焊锡接点340，使预上锡膏的尖顶(图3C与图3D)不再存在。因此，焊锡接点440并无先前技术的倒装芯片系统及方法中，受到应力集中的损害。
如图2B所述，导电的尖状凸块222揭露于美国专利6,489,180，当其借由传统金属线结合法制造时，该销子由金或铝形成。金的熔点大约1064.18度，而铝的熔点大约660.32度。当第2E图的焊锡凸块211回焊时，回焊温度通常不高于300度。因此，使用传统金属线结合法形成导电的尖点凸块222时，该尖状凸块222不会被回焊或熔化而在回焊焊锡凸块211时保持先前的形状。因此，尖点A仍存在于倒装芯片封装250a的焊锡接点中，导致在焊锡凸块211受到应力作用时应力集中于一点。
图4A至图4C显示本发明的另一实施例的倒装芯片封装方法的制造步骤以形成本发明的另一填充底胶方法。本实施例本是提供一倒装芯片封装方法的手段以形成一底胶封装材料，而不会在焊锡接点中造成二氧化硅填充材的污染。如先前描述的实施例，借此可防止焊锡接点中的不良点及应力集中点，以使倒装芯片封装产生较佳的电性功能可靠度及较长的寿命。
在图4A中，提供一衬底420，于其上表面包含焊锡掩模424及焊锡掩模开口423的衬底420。亦提供一焊电421于焊锡掩模开口423内，且焊垫321是完全为焊锡掩模开口423所暴露，焊垫421为SMD型，该焊垫421通常包含铜。
在图4B中，一具有尖顶的预上锡膏422利用与图3B及图3C相同的方法形成于焊垫421上。预上锡焊422通常由锡铅合金或无铅的锡基合金等焊锡材料组成。
如图4C中说明，一用于非流动性填充底胶技术的填胶材料430其中含有随机分布的二氧化硅填充料432，借由点胶或其它已知方法铺于衬底420上。接着，将于主动表面上具导电凸块411的半导体芯片410附着于衬底420上。导电凸块311最好为焊锡材料，金，铜，涂上焊锡材料的金，或涂上焊锡材料的铜。而焊锡材料最好为锡铅合金或无铅的锡基合金。预上锡膏422回焊以与芯片410的导电凸块结合并形成焊锡接点440此连结乃由熔化的预上锡膏422沿芯片410的导电凸块表面向下流动而产生。而影响熔化的预上锡膏422的流速有两个主要的因素。其中的一因素为沿着芯片410的导电凸块表面的熔化的预上锡膏422的毛细作用。另一因素为熔化的预上锡膏422重量的应用。此两力量所施的方向完全相反，因此减少熔化的预上锡膏422的流速。
因此预上锡膏422及导电凸块411连接的形成会变慢。另外，利用接近导电凸块接触点且呈锥形的预上锡膏422，以修改预上锡膏422及芯片410的导电凸块的对向回焊，而产生成一体且无(或实际上无)硅填充料432的焊锡接点。
以另一方法说明，于预上锡膏二氧化硅填充料421回焊期间导电凸块411亦会回焊，在此导电凸块411由一适当的焊锡材料组成，例如：锡铅合金，无铅的锡基合金。当预上锡膏回焊时芯片410的导电凸块亦会回焊，熔化的导电凸块411往下流，而与熔化的预上锡膏422流向完全相对，更将预上锡膏422与导电凸块411的连接减慢。因此将预上锡膏432有效地由焊锡接点440中移除或消除，为达成本发明的主要目的。
在非流动性填充底胶技术的填胶材料430回焊时，为减少熔化的预上锡膏422及芯片410的(熔化的)导电凸块间的表面张力，该填胶材料430最好含流体成分。填胶材料430于回焊期间亦会变硬。因预上锡膏322已回焊，使焊锡接点440的尖顶不再存在。因此，焊锡接点440并无先前技术中倒装芯片系统及方法中应力集中的损害。
由提供的叙述中可了解，本发明概括的方向是利用一方法达成提供或形成预上锡膏于衬底的焊垫上，其中预上锡膏的轮廓为逐渐变小成一点。另外，在利用填充底胶材料(含二氧化硅填充料)后，利用预上锡膏对准芯片的导电凸块的点，以附着于倒装芯片封装的衬底装置上。之后，回焊方法使一缓慢熔化及回焊的预上锡膏进入该对准的导电凸块。此缓慢回焊，使呈锥形的预上锡膏产生成一体且无(或实际上无)二氧化硅填充料的焊锡接点。

Claims (19)

1.一种倒装芯片封装方法，包含至少下列步骤：
提供一衬底，该衬底上具有一至少露出部分于该衬底表面的导电焊垫；
形成一凸出于该导电焊垫上且呈锥形的预上锡膏；
于该衬底上形成一具有二氧化硅填充料的填胶材料；
将一具有导电凸块的芯片附着于该衬底上，其中该导电凸块对准该预上锡膏；以及
回焊该预上锡膏以连结该导电凸块与该导电焊垫，形成一焊锡接点。
2.根据权利要求1所述的倒装芯片封装方法，其中该预上锡膏包含锡铅合金或无铅的锡基合金。
3.根据权利要求1所述的倒装芯片封装方法，其中该填胶材料是以点胶的方式形成于该衬底上。
4.根据权利要求1所述的倒装芯片封装方法，其中该导电凸块包含焊锡，金，铜，具有焊锡涂层的金，或具有焊锡涂层的铜。
5.根据权利要求4所述的倒装芯片封装方法，其中该焊锡包含锡铅合金或无铅的锡基合金。
6.根据权利要求1所述的倒装芯片封装方法，其中该导电凸块包含锡铅合金或无铅的锡基合金，并且于回焊预上锡膏的同时被回焊。
7.一种倒装芯片封装方法，包含下列步骤：
提供一衬底，该衬底上具有一至少露出部分于该衬底表面的导电焊垫；
提供一不沾焊料的印刷网版，其中定义有一反向漏斗形开口；且该反向漏斗形开口具有一顶部开口及底部开口；
使该衬底及该印刷网版相接触，其中该反向漏斗形开口的底部开口位于该导电焊垫上；
透过该反向漏斗形的顶部开口形成一焊锡膏覆盖于该导电焊垫上；
回焊该焊锡膏以形成锥形的一预上锡焊；
分离该印刷网版及该衬底；
形成一具有二氧化硅填充料的填胶材料于该衬底上；
将具有导电凸块的芯片附着于该衬底上，且其中该导电凸块对准于该预上锡膏；以及
回焊该预上锡膏以将该导电凸块及该导电焊垫完整接合。
8.根据权利要求7所述的倒装芯片封装方法，其中该预上锡膏包含锡铅合金或无铅的锡基合金。
9.根据权利要求7所述的倒装芯片封装方法，其中该填胶材料是以点胶的方式形成于该衬底上。
10.根据权利要求7所述的倒装芯片封装方法，其中该导电凸块包含焊锡，金，铜，具有焊锡涂层的金，或具有焊锡涂层的铜。
11.根据权利要求10所述的倒装芯片封装方法，其中该焊锡包含锡铅合金或无铅的锡基合金。
12.根据权利要求7所述的倒装芯片封装方法，其中该导电凸块包含锡铅合金或无铅的锡基合金，并且于回焊预上锡膏的同时被回焊。
13.根据权利要求7所述的倒装芯片封装方法，其中该印刷网版包含不锈钢或涂覆有不沾焊料的材料的金属材料。
14.根据权利要求7所述的倒装芯片封装方法，其中该焊锡膏由网版印刷形成。
15.一衬底，适用于倒装芯片封装方法，以减少一芯片与该衬底间焊锡接点的二氧化硅填充料污染，其特征在于所述衬底包含：
一导电焊垫，设于该衬底上；以及
一预上锡膏物，自该衬底的导电焊垫上方伸出且呈锥形。
16.根据权利要求15所述的衬底，其特征在于：该导电焊垫为非防焊设计型或防焊设计型。
17.根据权利要求15所述的衬底，其特征在于：该预上锡膏包含锡铅合金或无铅的锡基合金。
18.一不沾焊料的印刷网版，用于倒装芯片封装方法以减少在芯片与衬底间的焊锡接点过程中二氧化硅填充料上的污染物，其特征在于所述印刷网版包含：
一反向漏斗形间隙，其具有一顶部开口；以及
一大于顶部开口的底部开口。
19.根据权利要求18所述的不沾焊料的印刷网版，其特征在于：该印刷网板包含涂上一层不沾焊料材料的不锈钢或金属材料。
CNB2003101154598A 2003-05-22 2003-11-26 倒装芯片封装方法及其使用的衬底及不沾焊料的印刷网版 Expired - Lifetime CN1301540C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/443,418 2003-05-22
US10/443,418 US20040232560A1 (en) 2003-05-22 2003-05-22 Flip chip assembly process and substrate used therewith

Publications (2)

Publication Number Publication Date
CN1574255A CN1574255A (zh) 2005-02-02
CN1301540C true CN1301540C (zh) 2007-02-21

Family

ID=33450409

Family Applications (2)

Application Number Title Priority Date Filing Date
CNB2003101154598A Expired - Lifetime CN1301540C (zh) 2003-05-22 2003-11-26 倒装芯片封装方法及其使用的衬底及不沾焊料的印刷网版
CNU2004200598106U Expired - Fee Related CN2751509Y (zh) 2003-05-22 2004-05-21 覆晶封装工艺的基材

Family Applications After (1)

Application Number Title Priority Date Filing Date
CNU2004200598106U Expired - Fee Related CN2751509Y (zh) 2003-05-22 2004-05-21 覆晶封装工艺的基材

Country Status (3)

Country Link
US (1) US20040232560A1 (zh)
CN (2) CN1301540C (zh)
TW (1) TWI257161B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103042818A (zh) * 2011-10-17 2013-04-17 正中科技股份有限公司 网版结构

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040232560A1 (en) * 2003-05-22 2004-11-25 Chao-Yuan Su Flip chip assembly process and substrate used therewith
US6933171B2 (en) * 2003-10-21 2005-08-23 Intel Corporation Large bumps for optical flip chips
US7659633B2 (en) 2004-11-10 2010-02-09 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
WO2005048311A2 (en) 2003-11-10 2005-05-26 Chippac, Inc. Bump-on-lead flip chip interconnection
US8574959B2 (en) 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US8216930B2 (en) * 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US8129841B2 (en) 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
US8350384B2 (en) * 2009-11-24 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US7282433B2 (en) * 2005-01-10 2007-10-16 Micron Technology, Inc. Interconnect structures with bond-pads and methods of forming bump sites on bond-pads
US7216324B2 (en) * 2005-03-11 2007-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method for designing chip package by re-using existing mask designs
JP2008535225A (ja) 2005-03-25 2008-08-28 スタッツ チップパック リミテッド 基板上に狭い配線部分を有するフリップチップ配線
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
CN1852638B (zh) * 2006-01-24 2010-05-12 华为技术有限公司 一种印刷焊膏的方法及印锡钢网
US8174119B2 (en) * 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
CN103109361B (zh) * 2011-04-06 2016-04-13 北京大学深圳研究生院 一种半导体封装中的底胶填充方法及设备
TWI502733B (zh) * 2012-11-02 2015-10-01 環旭電子股份有限公司 電子封裝模組及其製造方法
CN103035604B (zh) * 2012-12-17 2014-07-16 矽力杰半导体技术(杭州)有限公司 一种倒装芯片封装结构及其制作工艺
CN103011053A (zh) * 2012-12-28 2013-04-03 矽格微电子(无锡)有限公司 传感器芯片正面向下外露的封装结构及封装方法
US9391040B2 (en) * 2014-10-17 2016-07-12 International Business Machines Corporation Planarity-tolerant reworkable interconnect with integrated testing
US9177835B1 (en) * 2014-04-17 2015-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Underfill dispensing with controlled fillet profile

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340277A (ja) * 1998-05-22 1999-12-10 Nec Corp 半導体チップ搭載基板、半導体装置及び前記半導体チップ搭載基板への半導体チップ搭載方法
JP2000232179A (ja) * 1999-02-10 2000-08-22 Shinko Electric Ind Co Ltd Ｐｇａ型電子部品用基板、その製造方法及び半導体装置
US6400034B1 (en) * 1999-07-12 2002-06-04 Nec Corporation Semiconductor device
US6555460B2 (en) * 1996-03-07 2003-04-29 Micron Technology, Inc. Methods for mask repattern process
CN2751509Y (zh) * 2003-05-22 2006-01-11 台湾积体电路制造股份有限公司 覆晶封装工艺的基材

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3348528B2 (ja) * 1994-07-20 2002-11-20 富士通株式会社 半導体装置の製造方法と半導体装置及び電子回路装置の製造方法と電子回路装置
US5539153A (en) * 1994-08-08 1996-07-23 Hewlett-Packard Company Method of bumping substrates by contained paste deposition
SG71734A1 (en) * 1997-11-21 2000-04-18 Inst Materials Research & Eng Area array stud bump flip chip and assembly process
JPH11168185A (ja) * 1997-12-03 1999-06-22 Rohm Co Ltd 積層基板体および半導体装置
JP3119230B2 (ja) * 1998-03-03 2000-12-18 日本電気株式会社 樹脂フィルムおよびこれを用いた電子部品の接続方法
US6204089B1 (en) * 1999-05-14 2001-03-20 Industrial Technology Research Institute Method for forming flip chip package utilizing cone shaped bumps
US6273327B1 (en) * 1999-06-16 2001-08-14 Trw Inc. Apparatus and method for depositing solder material onto a circuit board
JP3575384B2 (ja) * 2000-03-27 2004-10-13 関西日本電気株式会社 半導体装置の製造方法
TW456008B (en) * 2000-09-28 2001-09-21 Siliconware Precision Industries Co Ltd Flip chip packaging process with no-flow underfill method
US6680213B2 (en) * 2001-04-02 2004-01-20 Micron Technology, Inc. Method and system for fabricating contacts on semiconductor components
TW544901B (en) * 2001-06-13 2003-08-01 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
US20040000428A1 (en) * 2002-06-26 2004-01-01 Mirng-Ji Lii Socketless package to circuit board assemblies and methods of using same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6555460B2 (en) * 1996-03-07 2003-04-29 Micron Technology, Inc. Methods for mask repattern process
JPH11340277A (ja) * 1998-05-22 1999-12-10 Nec Corp 半導体チップ搭載基板、半導体装置及び前記半導体チップ搭載基板への半導体チップ搭載方法
JP2000232179A (ja) * 1999-02-10 2000-08-22 Shinko Electric Ind Co Ltd Ｐｇａ型電子部品用基板、その製造方法及び半導体装置
US6400034B1 (en) * 1999-07-12 2002-06-04 Nec Corporation Semiconductor device
CN2751509Y (zh) * 2003-05-22 2006-01-11 台湾积体电路制造股份有限公司 覆晶封装工艺的基材

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103042818A (zh) * 2011-10-17 2013-04-17 正中科技股份有限公司 网版结构
CN103042818B (zh) * 2011-10-17 2015-12-16 正中科技股份有限公司 网版结构

Also Published As

Publication number Publication date
TW200427037A (en) 2004-12-01
CN1574255A (zh) 2005-02-02
CN2751509Y (zh) 2006-01-11
TWI257161B (en) 2006-06-21
US20040232560A1 (en) 2004-11-25

Similar Documents

Publication Publication Date Title
CN1301540C (zh) 倒装芯片封装方法及其使用的衬底及不沾焊料的印刷网版
US10847493B2 (en) Bump-on-trace interconnect
US9468136B2 (en) Low void solder joint for multiple reflow applications
US7315081B2 (en) Semiconductor device package utilizing proud interconnect material
US7619318B2 (en) No-flow underfill composition and method
TWI243466B (en) Paste for forming an interconnect and interconnect formed from the paste
CN1738039A (zh) 半导体器件及其制造方法
CN1512580A (zh) 半导体装置及其制造方法
TWI532133B (zh) 半導體元件中的無鉛結構
CN1820889A (zh) 非低共熔无铅焊料组合物
JP5004549B2 (ja) 電子部品の基板への搭載方法及びはんだ面の形成方法
CN1684573A (zh) 安装基片及电子元件的安装方法
JP4814196B2 (ja) 回路基板
JP5822656B2 (ja) 半導体装置及びその製造方法
KR20030090481A (ko) 비도전성 접착제로 ｉｃ 칩을 기판에 본딩하는 방법과형성된 조립물
CN1299518A (zh) 半导体封装及其倒装芯片接合法
JP2007059485A (ja) 半導体装置、基板及び半導体装置の製造方法
TWI648835B (zh) 有芯構造焊料凸塊及其製造方法
US8466546B2 (en) Chip-scale package
CN1848413A (zh) 覆晶球格阵列封装构造中具有晶体配向(100)的应变硅晶圆
JP2007059638A (ja) 半導体装置およびその製造方法
US8083832B2 (en) Paste for forming an interconnect and interconnect formed from the paste
CN1871702A (zh) 用于形成互连结构的焊膏以及由焊膏形成的互连结构
JP2000031210A (ja) 転写用の金属ペーストおよびバンプ形成方法
Yang et al. Investigation of key factors in thermal compression (TCB) NCF bonding process

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20070221