CN1945805A - 半导体封装方法以及用于半导体封装的载体 - Google Patents

半导体封装方法以及用于半导体封装的载体 Download PDF

Info

Publication number
CN1945805A
CN1945805A CNA200610057299XA CN200610057299A CN1945805A CN 1945805 A CN1945805 A CN 1945805A CN A200610057299X A CNA200610057299X A CN A200610057299XA CN 200610057299 A CN200610057299 A CN 200610057299A CN 1945805 A CN1945805 A CN 1945805A
Authority
CN
China
Prior art keywords
base plate
solvent type
circuit base
chip
rank
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA200610057299XA
Other languages
English (en)
Inventor
林俊宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
Original Assignee
BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BERMUDA CHIPMOS TECHNOLOGIES Co Ltd, Chipmos Technologies Inc filed Critical BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Publication of CN1945805A publication Critical patent/CN1945805A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83874—Ultraviolet [UV] curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一种半导体封装方法，其包括以下步骤：首先，提供具有第一表面以及第二表面的线路基板。接着，在线路基板的第一表面上形成无溶剂型双阶热固性化合物。然后，将无溶剂型双阶热固性化合物部分固化，以于线路基板的第一表面上形成无溶剂型B阶粘着层。此后，利用B阶粘着层将芯片贴附到线路基板的第一表面上。之后，将芯片电连接到线路基板，然后形成密封材料以密封住芯片。本发明也提供一种能够应用于上述封装方法的载体。

Description

半导体封装方法以及用于半导体封装的载体
技术领域
本发明涉及一种半导体封装方法，且特别涉及一种基板上的芯片封装体(SOC package，Substrate On Chip package)的封装方法。
背景技术
所谓“SOC封装体”是指目前已普遍使用的一种半导体封装，其主要是将半导体芯片贴附到具有通孔的基板上，并利用多条通过这些通孔的金属焊线将基板与芯片连接起来。SOC封装体所使用的基板上通常会形成有多个以格状阵列方式排列的焊球。在第6,190,943号美国专利申请(CHIP SCALE PACKAGING METHOD)中，其披露了一种SOC封装体以及一种封装方法。
如图1所示，SOC封装体20包括线路基板22、半导体芯片24以及多个球形焊球44。其中，线路基板22具有用来贴附半导体芯片24的上表面30、上面植有球形焊球44的下表面38，以及至少一个形成在线路基板22中的通孔34。此外，SOC封装体20中的热塑性粘着层28能够将半导体芯片24贴附于线路基板22的上表面30。线路基板22中的通孔34会暴露出位于半导体芯片24的主动表面26上的接合垫36，以使得穿过通孔34的焊线32能够将半导体芯片24的接合垫36与线路基板22的导线区域41连接起来。在SOC封装体20中，导线区域41具有导线层40，其形成于基板22的下表面38上。另外，公知技术会采用一种不导电树脂材料形成的钝化层42来保护半导体芯片24的边缘以及线路基板22的各个通孔34。
如图2所示，在第6,190,943号美国专利申请(CHIP SCALEPACKAGING METHOD)中，其所披露的SOC封装体20的制造方法包括以下步骤：(a)提供具有上表面30的线路基板22，上表面30具有至少一个含有上述通孔34的芯片植入区域302；(b)用印刷的方式在芯片植入区域302上涂覆热塑性粘着层28；(c)将芯片24贴附于芯片植入区域302上，使得芯片24的主动表面26与热塑性粘着层28接触，并且使得接合垫36的位置对应于通孔34；(d)对线路基板22以及芯片24进行加热与加压一预定时间；(e)利用焊线接合法形成焊线32，且焊线32会穿过通孔34以将线路基板22的导线区域41与芯片24的接合垫36连接起来；(f)在芯片24的边缘以及通孔34上形成钝化层42；(g)在线路基板22的下表面38上植入多个呈格状阵列排列的焊球44。在执行完上述步骤之后便完成了SOC封装体20的制造。
值得注意的是，在步骤(b)中提到的热塑性粘着层28是一种有弹性的、半液态的，且不含溶剂的热塑性硅橡胶。由于在贴附之前热塑性硅橡胶呈半液态，所以，在步骤(d)中，受到加热以及加压的热塑性粘着层28容易发生溢流的现象，而覆盖住芯片24的接合垫36，进而导致封装体故障。公知技术的另一个缺点在于，在步骤(b)中涂覆了热塑性粘着层28之后，便无法再将线路基板22堆叠以供运送或储存，且在步骤(b)完成之后，必须尽快将热塑性粘着层28与芯片24贴合，否则线路基板22便会被污染，且会互相粘着，进而导致批量生产上的困难。
发明内容
有鉴于此，本发明提供一种用于半导体封装的载体，以改善芯片接合过程的合格率。
本发明提供一种半导体封装方法，以达到更好的生产质量。
为达上述或其它目的，本发明提供一种用于半导体封装的载体，此用于半导体封装的载体包括线路基板以及设置在线路基板上的无溶剂型B阶热固性粘着层。
在本发明的一实施例中，线路基板具有通孔，且无溶剂型双阶热固性化合物设置在通孔旁。
在本发明的一实施例中，无溶剂型B阶粘着层在室温下呈固态及/或不具有粘性。
在本发明的一实施例中，无溶剂型B阶粘着层有粘性且为胶体状。
在本发明的一实施例中，无溶剂型B阶粘着层包括聚醯亚胺、聚喹啉或苯并环丁烯。
为达上述或其它目的，本发明提供一种半导体封装方法，其包括以下步骤：首先，提供具有第一表面以及第二表面的线路基板。其次，在线路基板的第一表面上形成无溶剂型双阶热固性化合物。接着，将无溶剂型双阶热固性化合物部分固化，以于线路基板的第一表面上形成无溶剂型B阶粘着层。之后，利用B阶粘着层将芯片贴附到线路基板的第一表面上。之后，将芯片电连接到线路基板，然后形成密封材料以密封住芯片。
在本发明的一实施例中，线路基板具有通孔。
在本发明的一实施例中，无溶剂型双阶热固性化合物形成于通孔旁。
在本发明的一实施例中，芯片包括主动表面以及多个位于主动表面上的接合垫，芯片的主动表面利用无溶剂型B阶粘着层与线路基板的第一表面粘结，且芯片的接合垫可通过线路基板的通孔暴露出来。
在本发明的一实施例中，由焊线接合法所形成的多条焊线可将通孔所暴露的接合垫电连接到线路基板。
在本发明的一实施例中，封装胶体形成在通孔内，用以密封住芯片以及焊线。
在本发明的一实施例中，无溶剂型双阶热固性化合物包括聚醯亚胺、聚喹啉或苯并环丁烯。
在本发明的一实施例中，无溶剂型B阶粘着层在室温下呈固态及/或不具有粘性。
在本发明的一实施例中，无溶剂型B阶粘着层有粘性且为胶体状。
在本发明的一实施例中，无溶剂型双阶热固性化合物利用紫外线固化法或热固法来进行部分固化。
在本发明的一实施例中，芯片利用进一步固化无溶剂型B阶粘着层而贴附到线路基板的第一表面上。
在本发明的一实施例中，当芯片贴附到线路基板的第一表面上时，无溶剂型B阶粘着层会被完全固化。
在本发明的一实施例中，当芯片贴附到线路基板的第一表面上时，无溶剂型B阶粘着层未被完全固化。
在本发明的一实施例中，无溶剂型B阶粘着层利用后紫外线固化法或后热固法来进行完全固化。
在本发明的一实施例中，当形成封装胶体以密封住线路基板上的芯片时，无溶剂型B阶粘着层会被完全固化。
在本发明的一实施例中，芯片利用焊线接合法电连接到线路基板。
在本发明的一实施例中，封装胶体利用模造法或点胶法形成。
在本发明的一实施例中，上述半导体封装方法进一步包括在形成封装胶体之后，于线路基板的第二表面上形成多个焊球。
在对无溶剂型双阶热固性化合物进行预固化处理，以形成无溶剂型B阶粘着层之后，由于无溶剂型B阶粘着层为胶体状，所以本发明的载体不会被污染且不会互相粘结。此外，载体可堆叠起来以供运送或储存，并且在半导体封装方法中实现了更好的操作机动性。或者，如果部分固化已达到足够程度的话，B阶粘着层在室温下可呈固态，并且不带有粘性。
为让本发明的上述以及其它目的、特征以及优点能更明显易懂，下文特举较佳实施例，并配合附图，作详细说明如下。
附图说明
图1是名为“CHIP SCALE PACKAGING METHOD”(芯片级封装方法)的第6,190,943号美国专利申请的SOC封装的截面图。
图2是名为“CHIP SCALE PACKAGING METHOD”(芯片级封装方法)的第6,190,943号美国专利申请的SOC封装的制造流程图。
图3A～图3E是本发明的第一实施例的半导体封装方法的制造流程图。
图4A～图4F是本发明的第二实施例的半导体封装方法的制造流程图。
主要元件标记说明
20：SOC封装体
22：线路基板
24：半导体芯片
26：主动表面
28：热塑性粘着层
30：上表面
32：焊线
34：通孔
36：接合垫
38：下表面
40：导线层
41：导线区域
42：钝化层
44：球形焊球
100、200：线路基板
100a、200a：第一表面
100b、200b：第二表面
102、202：无溶剂型双阶热固性化合物
102’、202’：无溶剂型B阶粘着层
104、204：芯片
106、206：焊线
108、208：封装胶体
200c：通孔
204a：主动表面
204b：接合垫
210：焊球
具体实施方式
第一实施例
现在，下文中将参考附图来描述本发明，图中表示了本发明的多种实施例。但是，本发明可以许多种形式来实施，本发明并不受限于下文中所阐述的实施例。所提供的实施例是为了使得本披露内容详尽、完整，并使得本披露内容可将本发明的精神充分地表达给所属领域的技术人员。以下，相同的标号代表相同的构件。
图3A～图3E是根据本发明的第一实施例的半导体封装方法的制造流程图。请参照图3A，首先，提供具有第一表面100a以及第二表面100b的线路基板100。线路基板100可以是印刷线路板(例如FR-4、FR-5、BT及其类似物)，其例如含有玻璃纤维强化树脂。线路基板100的第一表面100a形成有电路图案(图中未示出)，例如导体垫、焊球垫，以及将导体垫与焊球垫连接起来的金属线。之后，于线路基板100的第一表面100a上形成无溶剂型双阶热固性化合物102。在本实施例中，无溶剂型双阶热固性化合物102的材料包括聚醯亚胺、聚喹啉(polyquinolin)、苯并环丁烯或其它类似的化合物。
请参照图3B，接着，将无溶剂型双阶热固性化合物102部分固化，以于线路基板100的第一表面100a上形成无溶剂型B阶粘着层102’。在上述预固化处理期间，本实施例会以预定的温度来加热线路基板100，即，本实施例可以用热固法来对线路基板100进行部分固化。在另一实施例中，我们可以用紫外线固化法来将线路基板100部分固化。在预固化处理之后，线路基板100上的无溶剂型B阶粘着层102’便具有B阶特征。在一较佳实施样态中，无溶剂型B阶粘着层102’在室温下可以没有粘性并且呈固态。因此，线路基板100可彼此堆叠以供大量运送或储存。上述优点有助于提高半导体封装方法中的操作机动性。如有必要，我们可使用一种有粘性且为胶体状的B阶粘着层，且其能进一步流动。
请参照图3C，提供至少一个芯片104，并利用无溶剂型B阶粘着层102’将芯片104贴附到线路基板100的第一表面100a上。具体而言，在进行芯片接合处理的过程中，芯片104会利用无溶剂型B阶粘着层102’紧密地贴附到线路基板100的第一表面100a上。在本实施例中，芯片接合处理是用热压法、紫外线固化法或类似方法进行的。应注意的是，在进行了芯片接合处理之后，无溶剂型B阶粘着层102’可以呈部分固化或完全固化的状态。如果在芯片接合处理之后，B阶粘着层102’仍然为部分固化时，本实施例可进一步采用后固化步骤(如热固法或紫外线固化法)来使B阶粘着层102’完全固化。
请参照图3D，在芯片接合处理之后，本实施例可用多条焊线106将芯片104电连接到线路基板100。且在本实施例中，焊线106(例如，金线)是通过焊线接合法中所使用的焊线机来形成。
请参照图3E，接着形成封装胶体108以密封住线路基板100上的芯片104。在一较佳实施样态中，封装胶体108可进一步密封住焊线106。在本实施例中，封装胶体108可以用模造法、点胶法或其它类似方法形成的。具体而言，如果无溶剂型B阶粘着层102’在密封处理前仍然是部分固化的话，那么无溶剂型B阶粘着层102’将会在密封处理期间被完全固化。
第二实施例
图4A～图4E是根据本发明的第二实施例的半导体封装方法的制造流程图。此处将针对使用无溶剂型B阶粘着层的基板上芯片(SOC)封装方法进行详细的说明。
请参照图4A，首先，提供具有第一表面200a以及第二表面200b的线路基板200。在本实施例中，线路基板200的详细结构与图3A所示的线路基板100大致相同，二者的主要区别在于，线路基板200具有至少一个通孔200c。此外，形成在线路基板200的第一表面200a上的无溶剂型双阶热固性化合物202定在通孔200c旁。
请参照图4B，随后，将无溶剂型双阶热固性化合物202部分固化，以于线路基板200的第一表面200a上形成无溶剂型B阶粘着层202’。在上述预固化处理期间，本实施例会以预定的温度来加热线路基板200，即，本实施例可以用热固法来对线路基板200进行部分固化。在另一实施例中，我们可以用紫外线固化法来将线路基板200部分固化。在预固化处理之后，线路基板200上的无溶剂型B阶粘着层202’便具有了B阶特征。在一较佳实施样态中，无溶剂型B阶粘着层202’在室温下可以没有粘性并且呈固态。因此，线路基板200可彼此堆叠以供大量运送或储存。上述优点有助于提高半导体封装方法中的操作机动性。如有必要，我们可使用一种有粘性且为胶体状的B阶粘着层，且其能进一步流动。
请参照图4C，提供至少一个芯片204，并利用无溶剂型B阶粘着层202’将其贴附到线路基板200的第一表面200a上。具体而言，在进行芯片接合处理的过程中，芯片204会利用无溶剂型B阶粘着层202’紧密的贴附到线路基板200的第一表面200a上。在本实施例中，芯片接合处理是用热压法、紫外线固化法或类似方法进行的。应注意的是，在进行了芯片接合处理之后，无溶剂型B阶粘着层202’可以呈部分固化或完全固化的状态。如果芯片接合处理后，B阶粘着层202’仍然为部分固化时，本实施例可进一步采用后固化步骤(如热固法或紫外线固化法)来使B阶粘着层202’完全固化。
如图4C所示，芯片204包括主动表面204a以及多个位于主动表面204a上的接合垫204b。芯片204的主动表面204a利用无溶剂型B阶粘着层202’而与线路基板200的第一表面200a粘结起来。由图4C可知，在芯片接合处理后，线路基板200的通孔200c会将芯片204的接合垫204b暴露出来。
请参照图4D，芯片接合处理之后，本实施例可用多条焊线206将芯片204电连接到线路基板200。在本实施例中，焊线206(例如，金线)是通过焊线接合法中使用的焊线机来形成。如图4D所示，穿过通孔200c的焊线206会电连接在芯片204的接合垫204b与线路基板200之间。
请参照图4E，接着形成封装胶体208以密封住线路基板200上的芯片204。在一较佳实施样态中，封装胶体208可进一步密封住焊线206。如图4E所示，本实施例的封装胶体208不仅填充于线路基板200的通孔200c中，而且还覆盖了部分的第一表面200a以及第二表面200b。在本实施例中，封装胶体208可以是用模造法、点胶法或其它类似方法形成的。具体而言，如果无溶剂型B阶粘着层202’在密封处理前仍然是部分固化的话，那么无溶剂型B阶粘着层202’将会在密封处理期间被完全固化。
请参照图4F，形成封装胶体208后，可将多个焊球210植入到线路基板200的第二表面200b上。最后，再进行切割处理，以获得多个SOC封装体300。
在本发明中，将无溶剂型B阶粘着层作为线路基板以及芯片之间的粘着薄膜，从而使得芯片的接合垫不会因为胶体的溢流现象而被粘着薄膜覆盖。本发明还提高了SOC封装透的堆叠能力以及供运送或储存的效率。此外，本发明的封装方法中还实现了更良好的操作机动性。
虽然本发明已以较佳实施例披露如上，然其并非用以限定本发明，任何所属技术领域的技术人员，在不脱离本发明之精神以及范围内，当可作些许之更动与改进，因此本发明之保护范围当视权利要求所界定者为准。

Claims (23)

1.一种半导体封装方法，其特征是包括：
提供具有第一表面以及第二表面的线路基板；
在该线路基板的该第一表面上形成无溶剂型双阶热固性化合物；
对该无溶剂型双阶热固性化合物进行部分固化，以于该线路基板的该第一表面上形成无溶剂型B阶粘着层；
利用该无溶剂型B阶粘着层将芯片贴附到该线路基板的该第一表面上；
将该芯片电连接到该线路基板；以及
形成封装胶体，以密封该线路基板上的该芯片。
2.根据权利要求1所述的半导体封装方法，其特征是该线路基板具有通孔。
3.根据权利要求2所述的半导体封装方法，其特征是该无溶剂型双阶热固性化合物形成于该通孔旁。
4.根据权利要求2所述的半导体封装方法，其特征是该芯片具有主动表面以及多个位于该主动表面上的接合垫，该芯片的该主动表面通过该无溶剂型B阶粘着层而贴附于该线路基板的该第一表面上，且该芯片的该接合垫会被该线路基板的该通孔暴露出来。
5.根据权利要求2所述的半导体封装方法，其特征是用焊线接合法所形成的多条焊线会将该通孔所暴露的该接合垫电连接到该线路基板。
6.根据权利要求5所述的半导体封装方法，其特征是该封装胶体形成在该通孔内，用以密封该芯片以及该焊线。
7.根据权利要求1所述的半导体封装方法，其特征是该无溶剂型双阶热固性化合物包括聚醯亚胺、聚喹啉或苯并环丁烯。
8.根据权利要求1所述的半导体封装方法，其特征是该无溶剂型B阶粘着层在室温下呈固态及/或不具有粘性。
9.根据权利要求1所述的半导体封装方法，其特征是该无溶剂型B阶粘着层有粘性且为胶体状。
10.根据权利要求1所述的半导体封装方法，其特征是该无溶剂型双阶热固性化合物利用紫外线固化法或热固法来进行部分固化。
11.根据权利要求1所述的半导体封装方法，其特征是该芯片是利用进一步固化该无溶剂型B阶粘着层，而贴附到该线路基板的该第一表面上。
12.根据权利要求11所述的半导体封装方法，其特征是当该芯片贴附到该线路基板的该第一表面上时，该无溶剂型B阶粘着层会被完全固化。
13.根据权利要求11所述的半导体封装方法，其特征是当该芯片贴附到该线路基板的该第一表面上时，该无溶剂型B阶粘着层未被完全固化。
14.根据权利要求13所述的半导体封装方法，其特征是该无溶剂型B阶粘着层利用后紫外线固化法或后热固法来进行完全固化。
15.根据权利要求13所述的半导体封装方法，其特征是当形成该封装胶体以密封该线路基板上的该芯片时，该无溶剂型B阶粘着层会被完全固化。
16.根据权利要求1所述的半导体封装方法，其特征是该芯片利用焊线接合法电连接到该线路基板。
17.根据权利要求1所述的半导体封装方法，其特征是该封装胶体利用模造法或点胶法形成。
18.根据权利要求1所述的半导体封装方法，其特征还包括在形成该封装胶体后，在该线路基板的该第二表面上形成多个焊球。
19.一种用于半导体封装的载体，其特征是包括：
线路基板；以及
设置在该线路基板上的无溶剂型B阶热固性粘着剂。
20.根据权利要求19所述的载体，其特征是该线路基板具有通孔，且该无溶剂型双阶热固性化合物设置在该通孔旁。
21.根据权利要求19所述的载体，其特征是该无溶剂型B阶粘着层在室温下呈固态及/或不具有粘性。
22.根据权利要求19所述的载体，其特征是该无溶剂型B阶粘着层有粘性且为胶体状。
23.根据权利要求19所述的载体，其特征是该无溶剂型B阶粘着层包括聚醯亚胺、聚喹啉或苯并环丁烯。
CNA200610057299XA 2005-10-06 2006-03-09 半导体封装方法以及用于半导体封装的载体 Pending CN1945805A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/246,403 US20070080435A1 (en) 2005-10-06 2005-10-06 Semiconductor packaging process and carrier for semiconductor package
US11/246,403 2005-10-06

Publications (1)

Publication Number Publication Date
CN1945805A true CN1945805A (zh) 2007-04-11

Family

ID=37910412

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA200610057299XA Pending CN1945805A (zh) 2005-10-06 2006-03-09 半导体封装方法以及用于半导体封装的载体

Country Status (3)

Country Link
US (1) US20070080435A1 (zh)
CN (1) CN1945805A (zh)
TW (1) TW200715503A (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009006318A1 (en) 2007-06-29 2009-01-08 Artificial Muscle, Inc. Electroactive polymer transducers for sensory feedback applications
TWI364827B (en) * 2008-11-25 2012-05-21 Chipmos Technologies Inc Chip package and manufacturing method thereof
EP2239793A1 (de) 2009-04-11 2010-10-13 Bayer MaterialScience AG Elektrisch schaltbarer Polymerfilmaufbau und dessen Verwendung
EP2337068A1 (en) * 2009-12-18 2011-06-22 Nxp B.V. Pre-soldered leadless package
WO2012118916A2 (en) 2011-03-01 2012-09-07 Bayer Materialscience Ag Automated manufacturing processes for producing deformable polymer devices and films
CN103703404A (zh) 2011-03-22 2014-04-02 拜耳知识产权有限责任公司 电活化聚合物致动器双凸透镜系统
US20140322522A1 (en) * 2011-10-10 2014-10-30 Bayer Materialscience Ag B-stageable silicone adhesives
US9876160B2 (en) 2012-03-21 2018-01-23 Parker-Hannifin Corporation Roll-to-roll manufacturing processes for producing self-healing electroactive polymer devices
WO2013192143A1 (en) 2012-06-18 2013-12-27 Bayer Intellectual Property Gmbh Stretch frame for stretching process
WO2014066576A1 (en) 2012-10-24 2014-05-01 Bayer Intellectual Property Gmbh Polymer diode

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5998860A (en) * 1997-12-19 1999-12-07 Texas Instruments Incorporated Double sided single inline memory module
US6190943B1 (en) * 2000-06-08 2001-02-20 United Test Center Inc. Chip scale packaging method
TW497236B (en) * 2001-08-27 2002-08-01 Chipmos Technologies Inc A soc packaging process
US7109588B2 (en) * 2002-04-04 2006-09-19 Micron Technology, Inc. Method and apparatus for attaching microelectronic substrates and support members

Also Published As

Publication number Publication date
US20070080435A1 (en) 2007-04-12
TW200715503A (en) 2007-04-16

Similar Documents

Publication Publication Date Title
CN1945805A (zh) 半导体封装方法以及用于半导体封装的载体
CN1298034C (zh) 半导体封装及其制造方法
CN100341127C (zh) 半导体器件
CN1167122C (zh) 半导体器件
CN1337738A (zh) 用于半导体封装处理的具有可注入导电区的带及其制造方法
CN1591885A (zh) 固态象传感装置的制造方法
CN1146985C (zh) 半导体装置和用于半导体装置的布线带
CN1777988A (zh) 条带引线框和其制作方法以及在半导体包装中应用的方法
CN1337741A (zh) 具有可注入导电区的半导体封装件及其制造方法
CN1292475C (zh) 半导体封装及其制造方法
CN1697127A (zh) 制造半导体器件的方法
CN1750257A (zh) 焊锡接垫上销子封装的组件、封装、基板结构及封装方法
US20080211075A1 (en) Image sensor chip scale package having inter-adhesion with gap and method of the same
CN1925141A (zh) 晶片封装结构
CN1612334A (zh) 具锯缘保护芯片之晶片级封装
CN101034689A (zh) 双密封半导体封装及其制造方法
JP2004072009A (ja) 半導体装置及びその製造方法
CN1652314A (zh) 引线框架、半导体芯片封装、及该封装的制造方法
CN1270418A (zh) 半导体器件及其制造方法
EP2287898A2 (en) Shrink Package on Board
CN2636411Y (zh) 多芯片封装结构
CN1295768C (zh) 集成电路或分立元件超薄无脚封装工艺及其封装结构
US7122407B2 (en) Method for fabricating window ball grid array semiconductor package
CN1146984C (zh) 半导体封装用芯片支持基片、半导体装置及其制造方法
CN101047160A (zh) 半导体连线封装结构及其与集成电路的连接方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication