CN1612334A - 具锯缘保护芯片之晶片级封装 - Google Patents

具锯缘保护芯片之晶片级封装 Download PDF

Info

Publication number
CN1612334A
CN1612334A CNA200410085694XA CN200410085694A CN1612334A CN 1612334 A CN1612334 A CN 1612334A CN A200410085694X A CNA200410085694X A CN A200410085694XA CN 200410085694 A CN200410085694 A CN 200410085694A CN 1612334 A CN1612334 A CN 1612334A
Authority
CN
China
Prior art keywords
chip
wafer
synthetic resin
resin sheet
class encapsulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA200410085694XA
Other languages
English (en)
Inventor
S·格耶
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE102004050027A external-priority patent/DE102004050027B4/de
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN1612334A publication Critical patent/CN1612334A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Dicing (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本案为与具有芯片边缘保护的芯片的晶片级封装及其方法有关的发明，其中所述的晶片级封装包含可在各种状况下设于适宜载板上的个别芯片。本发明的目的在于提供一种排除了已知技术的缺点、排除了热不匹配以及衬底层级可靠度的问题、实现了适当的薄形结构，并实现了可信赖的芯片边缘保护的晶片级封装。再者，藉由所提供的方法，上述的晶片级封装乃可得以实施。此乃是因为所述芯片(1)乃自后侧被极度地薄形化且接合于一纤维强化合成树脂片(4)，以形成一坚固接合装配，其在惯常温度范围内不会分离，且所述装配的边缘乃至少部分地被一高分子(8)所涂覆。

Description

具锯缘保护芯片之晶片级封装
技术领域
本案是关于一种具锯缘保护芯片之晶片级封装，包括在各种状况下可被设置在一适合的载板上个别的芯片，以及有关制造此种晶片级封装的方法。
背景技术
晶片级封装(WLP)已知是目前所有封装中最不昂贵的封装，其理由为芯片是直接与印刷电路板(Printed Circuit Board，PCB)及焊线接触，因此不再需要关键的引线框(leadframe)与封装(encapsulation)。晶片级封装具有与非常好的电性相结合的极小尺寸，此外，也保持测试及重新执行的可能性，并且可使用印刷电路板之惯用取放机器(pick-and-place machine)。
“晶片级封装”之意义为整个封装过程与在晶片上所有的互连以及其它的过程步骤是在切割(singulation/dicing)为芯片(chips/dies)之前进行，然后，这些切割的芯片直接被设置在衬底上。
此外，芯片须要利用合成材质(例如，高分子)的封入，此种封入的任务是保护芯片不受侵蚀性环境的影响，特别是在层序列区域中的锯缘，并且，在微机械(micromechanical)级上，可保护细小的焊线不受损害，而在大机械(macromechanical)级上，则可保护硬而脆的硅而不会破裂。
在大部分芯片或是封装中，此种保护方式是藉由在合成材料的封入而产生，其已知为一种模盖(mould cap)。为了达到此一目的，连同引线框或是一些其它载体组件的封装，是完全被封入在一个模具中的热固化(thermocuring)环氧树脂(一种模塑料化合物)。在此种操作中，锯缘、焊线以及硅都可受到保护，同时，可混入引线框或是载体组件。
在此种较不昂贵WLP的状况中，不再需要进行保护焊线的工作与引线框的混入。在WLP中，所必须进行的是保护层区域中的锯缘不受侵蚀性环境的影响以及保护背面易脆的硅，而为了达到此目的，则从晶片组装中分割出芯片，且各自被设置在电路板上，例如，以相当于倒装芯片(flip-chip)技术的方式，然后，在芯片的背面与芯片的锯缘接着被封入热固化的环氧树脂中。
然而，此种WLP所具有的缺点为仅可用于具有边缘长度最长接近2.5mm的小芯片。会产生此种情况的理由为较大的芯片在展开(大DNP)时具有较大的位移，而结合在芯片中2.3ppm/K与印刷电路板中20ppm/K两者非常个别的展开系数，在不可避免的温度变化发生时，将引起外部焊接逐步的分离。此意谓着，芯片可能在印刷电路板(PCB)上热循环测试中过早失败，而导致焊接的破裂。
未了避免此等问题，直至目前为止，已知有两种基本的可能方式。
第一可能性系引起一种芯片与印制电路板之”限制牢固”。例如，这可藉由该芯片与该印制电路板间之一”未充满”，或部分包覆该芯片上之焊球之一”高分子轴环”来达成。
然而，就”未充满”之”限制牢固”而言，其系藉由使用毛细孔作用来将制模材料引入该芯片与该印制电路板之间，其缺点为不易维修。此外，”未充满”需要一额外的操作步骤。再者，就超大型芯片而言，例如DRAMs，”未充满”就长期而言并不可靠。
“轴环”之使用效果有限，且就大型芯片而言并不适当，例如DRAMs。
第二种可能性系为该芯片与该印刷电路板之”闲置牢固”。例如，这可藉由”微弹簧”(以弹簧之方式设计的连接组件)、”软块”(弹性或顺的接触块)、使用一芯片嵌设膜(胶布)、或一”双层珠体再分配”(接线插入器，其中两个接触珠体之一位于另一个之上，而在下面的接触珠体被嵌入环氧树脂内。
然而，可以确定的是，所有的”闲置牢固”皆有一共同的主要缺点。假如该芯片与该印刷电路板间之距离(H)小的话(该焊珠之切变力系与被H所分开之DNP成比例)，则”自由增益”及”可靠度增益”也会变小。假如该芯片与该印刷电路板间之距离(H)大的话，则”自由增益”及”可靠度增益”固然会变大，但同时，结构会变厚，导致在持续的微型化中变的不一致。
该关系可以一通式来表示：
γ＝ΔT(CTEdie-CTEboard)DNP/H
γ＝切变力
CTE＝晶粒或电路板之热膨胀系数
ΔT＝应力周期之温度范围
DNP＝至焊连结中心点之距离
H＝晶粒(芯片)与电路板间之距离
从该通式可明显看出，该切变力特别地依赖H，且随着H的增加而降低。
US 5851845揭露了一种半导体芯片之封装方法。该方法系根据一问题，即在进行一未封装芯片于一印刷电路板上之芯片上电路板嵌设时，将会产生一热感应应力。该热应力系因该芯片之热膨胀系数与该印刷电路板之热膨胀系数间的不协调而产生。
该方法因此提供在晶片组装上之一芯片可藉由插入一顺的黏着层而嵌设于一衬底上。该顺的黏着层系用以吸收热感应应力。硅、陶瓷、或玻璃纤维强化环氧树脂(例如FR-4)皆可作为衬底材料。例如，多硫亚氨、环氧树脂、硅树脂等等皆可考虑作为该顺的黏着层。在切割后，对应之配备完成芯片可嵌设于印刷电路板上。
最后，US 2002/197771 A1揭露一种藉由CMP(化学机械研磨)来让晶片变薄的方法以及一种保护该变薄芯片的安排。为了保护该芯片免于损害或破裂，一强化装置系设置于其背部。一平板或一多硫亚氨或多晶硅层系作为该强化装置。本案固此系基于提出一种可消除已知技艺之缺失之晶片级封装之目的。热的不协调与电路板级可靠度的问题被消除了，且可允许适当之薄结构的实现，及允许芯片边缘之可靠保护。此外，实现该晶片级封装之方法系被提出。
其系藉由将该芯片之背面削的极薄，并与一纤维强化合成树脂板结合，形成一不会在常温范围内破碎之坚固结合装配，及至少部分涂覆一高分子于该装配之边缘。
在此例中，该合成树脂板可嵌设于该芯片之背面或正面。
发明内容
在本发明中，芯片正面之合成树脂板系具有穿孔，而穿孔之间距系相同于嵌设于该芯片对面之该合成树脂板面上之该焊珠，该芯片系面朝下地嵌设于该合成树脂板上，并经由穿孔电连接。
变薄的芯片的厚度约为10μm到100μm，以及合成树脂片的厚度约为100-2000μm。
芯片在一方正的0.5mm间距大小中较佳地具有一M3-RDL系统以及焊珠。
本发明的目的是基于藉由第一个方法达成，其特征在于，一晶片首先以向下的方式(即活性端向下)附着在一暂时的载体上，接着从后侧施以机械性在加以湿式化学处理，使其变薄至一预期的厚度，其中晶片的后侧在单层的基底上首先进行氧化，以及后续提供一硅氧起使子，此后续步骤中，一晶片大小的合成树脂片可黏着地结合在晶片后侧上，其中暂时的载体移除之后，此“晶片“被拉开从芯片侧至一预定的深度，形成切口，其中一光敏感高分子施用于芯片侧，并暴露和放置一段时间，使得切口两端为该高分子包覆，其中该晶片从具有合成树脂片的一端被拉开至到个别的“芯片”。
本发明的目的是基于藉由第二个方法达成，其中，具焊珠的晶片在一方正的0.5mm间距大小中以向下的方式黏着在一晶片大小的合成树脂片上，该合成树脂片藉由跟焊珠相同间距的穿孔所提供，其中，后续地该晶片从后侧变薄接着印上树脂，其中，经由穿孔以及与晶片相反的一端提供焊珠，此“晶片”接着被拉开从芯片侧至一预定的深度，形成切口，其中一光敏感高分子施用于芯片侧上，并暴露和放置一段时间，使得切口两端为该高分子包覆，其中该晶片从具有合成树脂片的一端被拉开到个别的“芯片”。
晶片的薄化于此约可为10μm的厚度。
本发明的目的是基于藉由第三个方法达成，其中，具焊珠的晶片在一方正的0.5mm间距大小中拉开至个别的芯片，其中，多样的芯片从芯片侧上的0.5mm间距到板端上的0.8mm间距，接合在一铜所涂覆的具有通过的穿孔以及一电路插入板合成树脂片上，其中，在气体顺流萤光化电浆中芯片从后侧薄化，以及在下方填充低黏着性的树脂以及印制，其中接着一光敏感高分子施用在该芯片侧上，并暴露和放置一段时间，使得芯片边缘为该高分子包覆，其中合成材料片拉开成“芯片”。
于此，芯片较佳地约薄化至10μm的厚度。
本发明的目的是基于藉由第四个方法达成，其中，具焊珠的晶片在一方正的0.5mm间距大小中拉开至个别的芯片，其中，该芯片接合到一印刷电路板，其中芯片在气体顺流萤光化电浆中薄化，洗去离子，在下方填充低黏着性的树脂以及印制。
芯片的薄化于此约可为10μm的厚度。
在本案对任何大小的芯片如DRAMs为例之晶片级封装中，板级可靠度的问题可藉由本发明来解决，其中芯片在非活性端薄化，因而其可适用在纤维强化聚氧树脂片的膨胀所生成的大偏移而不会有任何的问题，例如一玻璃纤维强化聚氧树脂(标准的印刷电路板材料)，其坚固地藉由芯片的后侧或者芯片的前端与其结合。
以此方式薄化的芯片可适用于PCB的膨胀而没有任何问题，因为Si具有厚度60+-25μm的0.5％的最大逆膨胀是可能的。此意味着硅坚固地结合至一具有20ppm/K(＝0.002％K)的膨胀系数的玻璃纤维强化聚氧树脂可合理的承受250K的温度范围(0.002％K×250＝0.5％)。
总之，本发明基于芯片/晶片极度地薄化，并接着接合至一具有膨胀系数与版片相同或相近的片材料，使得硅可以而且跟着板的大偏移，而不会发生接合连接脱离的现象。
以下将以最佳实施例更详细的说明本发明。
附图说明
第1图系为根据已知技术之一晶片级封装，其中一芯片系藉由焊接球之辅助而架设在一板片上；
第2图系为根据本发明之一晶片级封装，其中该芯片系被极端地薄化并且该芯片之背面系被结合到一玻璃纤维强化合成树脂片(glass-fibre reinforced synthetic resin sbeet)，以产生一不会破碎之装配；
第3图系为第2图中装配之断面示意图(schematic sectionalrepresentation)，一切口系被提供；
第4图系为第3图中之该切口被涂覆一高分子后之示意图；
第4图显示由背侧锯开而被分割并被提供一芯片边缘保护之芯片；
具体实施方式
第1图系为根据已知技术之一晶片级封装，其中一芯片1系藉由焊接球2之辅助而架设在一板片(玻璃纤维强化印刷电路板)上。如一开始所言，由于个别热膨胀系数，此时于焊接球2处可能会发生破裂。
第2图所示系为根据本发明之一晶片级封装，其中一极端薄化的芯片1系被层压到一玻璃纤维强化合成树脂片4上，以致一个于正常温范围不会破碎之装配5，系可以被提供于该芯片1以及合成树脂片4间。该焊接球2于被提供于芯片侧部之该装配5上，而该焊接球2系借着连接到铜导轨(contductor track)之焊料(solder contact)(图中未显示)之焊接而架设于一板片3上。
这个于该芯片1以及该玻璃纤维强化合成树脂片4间之坚固结合，具有强制于该芯片1上之该合成树脂片4之膨胀行为之效力，以致于该装配5之热膨胀系数相当于该板片之热膨胀系数，必然地，对该焊接球2一个热导致之压力系被避免。
实施例1：
本实施例系为一个较佳之实施例变化，系相关于一个芯片级环氧树酯芯片之背侧载体(chip-sized epoxy resin chip back-sidecarrier)(纤维强化合成材料片2)，用以接该收芯片1。
为了这个目的，一晶片系被较佳的设置与一M3-RDL系统(RDL：导线架)以及与一个0.5毫米高之正方形之焊接球2，并具有被放置在一暂时载体上且由其背侧，先机器化地，接着湿化学地(wet-chemically)，例如，藉湿化学机械研磨法(CMP)(wet-chemicallymerchanical pliishing)，被薄化至一约35微米厚度之DRAMs。
接着，于该暂时载体上以该方法被薄化之该晶片，系以一单层为准则被氧化，并被提拱以一硅甲烷初体(saline primer)。之后，一35微米厚之晶片级之玻璃纤维强化合成树脂片4被黏着于该晶片之背侧，而该装配系被接合。
接着，该暂时载体可被移除，而该“晶片”被锯开成晶片级封装之独立“芯片”5，而该锯缘6系被覆印(printed)一环氧化树脂，用以保护。然而，该锯缘保护系因为各个“芯片”5需单独的被覆印，而需相对地费力的来完成，
较便宜的芯片边缘保护是如第3图至第5图所示。为达此目的，使用一薄的锯齿片状厚度约为48微米，由该芯片的侧边朝向芯片与芯片的间隔，锯至完成的「晶片」上，至一预先决定深度(第3图)，因此产生横切的锯齿裂口。
所以，习惯上在该「晶片」的HMDS疏水处理后，藉由旋转披付一对光敏感的高分子8(PI或是BCB)，而将一薄层的合成材质使用至该芯片侧边。此处必须被确定的是该锯齿切口7未被完全填充。而后暴露并开发该高分子8，因而最后只有该锯齿裂口7的芯片边缘被包覆。
而后藉由最后锯通过该合成树脂片4，自该晶片的背侧，将该「晶片」进行最后单一化为「芯片」。
由于根据本发明之结构基础，该「晶片」与「芯片」5包含90％的玻璃纤维强化环氧树脂，所以该「晶片」与「芯片」的命名具有引号。
实施例2：
本实施例是关于芯片级环氧树脂芯片前侧导线架，以接收芯片1。
为达此目的，较佳是配备M3-RDL(RDL：再分配层)系统与方形高度0.5mm的焊珠且具有DRAM的一晶片，其是「面朝下」被贴覆在厚度350微米晶片级玻璃纤维加强环氧树脂片，且以与该焊珠具有相同高度的垂直穿孔进行两面之间的连接。
所以，以此方式所形成的该接合配装，是自该晶片的背侧以湿化学薄化至硅厚度为35微米。而后，该晶片的整个后侧是被完全印刷，且以一环氧树脂作为保护，以及提供焊珠至与该信道穿孔相反的该侧。
最后，以此方式所改变的该「晶片」是被锯开为个别「芯片」5。产生该锯缘保护的方式是与实施例1中的方式相同。
实施例3：
此实施例是关于一种环氧树脂芯片前侧导线架，用于接收一芯片，其是比该芯片稍大一些。为达此目的，较佳是配备M3-RDL(RDL：再分配层)系统与方形高度0.5mm的焊珠且具有DRAM的一晶片，其是被锯成芯片。而后，以已知技术将该芯片焊接至400微米厚玻璃纤维加强的环氧树脂板，其携带数个100s芯片。将铜电镀、信道穿孔与接线中介片提供至该环氧树脂板(在芯片侧高度为05.mm，在该板侧的标准高度为0.8mm)。
所以，在大气顺流氟化的电浆中，位于该载体上的该芯片是被薄化至25微米，而后未被高黏度的环氧树脂充满，且被印刷。
而后，提供焊珠至该载体的对侧，且该载体被锯成「芯片」，而后芯片边缘的产生方式是与实施例1中的方式相同。
实施例4
本实施例是关于芯片在板上(chip-on-board)的系统，而后该芯片被薄化与包装。
为达此目的，较佳是配备M3-RDL(RDL：再分配层)系统与方形高度0.5mm的焊珠且具有DRAM的一晶片，其是被锯成芯片。而后以已知的技术，将这些芯片与其它的芯片一起焊接至一板上。而后，在大气顺流氟化的电浆中，在该板上将裸露的芯片薄化至25微米且以无离子的方式清洗。而后，该芯片未充满低黏度的环氧树脂，且被印刷。
由于铜、铝、镍、锡、铅与有机树脂几乎不会受到氟化电浆的破坏，所以可在该板上薄化。
而后藉由旋转披负、暴露与建立一高分子，而可进行敏感性芯片边缘6的保护。

Claims (14)

1.一种晶片级封装，其包含可在各种状况下设于一适宜载板上的个别芯片，其特征在于所述芯片乃自后侧而极度地薄形化且接合于一纤维强化合成树脂片，以形成一坚固接合装配，其在惯常温度范围内不会分离，且所述装配的边缘乃至少部分地被一高分子所涂覆。
2.如权利要求1所述的晶片级封装，其特征在于所述纤维强化合成树脂片乃排列于所述芯片的该后侧。
3.如权利要求1所述的晶片级封装，其特征在于所述纤维强化合成树脂片乃设置于所述芯片的前端。
4.如权利要求3所述的晶片级封装，其特征在于所述纤维强化合成树脂片乃具有穿孔，且其中所述芯片”以面朝下(face-down)”的方式设在所述合成树脂载板上并透过所述穿孔来电连结。
5.如权利要求1至4之任一项所述的晶片级封装，其特征在于所述被薄形化后的芯片之厚度乃为10-100μm。
6.如权利要求1至4之任一项所述的晶片级封装，其特征在于所述纤维强化合成树脂片的厚度为100-2000μm。
7.如权利要求1至6之任一项所述的晶片级封装，其特征在于所述芯片乃配有一M3-RDL系统以及在方形0.5mm间距的焊珠。
8.一种产生一晶片级封装的方法，其特征在于一晶片先以”面朝下(face-down)”的方式附在一临时载板，其次是利用机械而薄形化，接着则是经湿式化学性处理而达到一预定厚度，其中所述晶片的后侧乃先在一单层基础氧化，其次则是设置一硅烷引物，又，一晶片尺寸的纤维强化合成树脂片则是被黏附于所述晶片的后侧，其中，在移除所述临时衬底后，所述”晶片”乃自该芯片侧被锯裂至一预定深度以形成切口，而，一光敏感多分子乃被施加至所述芯片侧并被曝光与显影，因此所述切口的两端都被高分子涂覆，并且，所述晶片则是自具有所述合成树脂片的那侧被锯裂成个别”芯片”。
9.一种制造晶片级封装的方法，其特征在于一晶片乃具有在方形0.5mm间距的焊珠，且以”面朝下(face-down)”的方式黏附在一晶片尺寸的纤维强化合成树脂片，其乃具有相同于焊珠间距的穿孔，随后所述晶片乃藉一湿式化学性处理而自后侧薄形化，接着则是被涂上一合成树脂，其中具有所述穿孔且与所述晶片背离的那侧乃设有焊珠，而所述”晶片”乃自该芯片侧被锯裂至一预定深度以形成切口，然后，一光敏感多分子乃被施加至所述芯片侧并被曝光与显影，因此所述切口的两端都被高分子涂覆，并且，所述晶片则是自具有所述合成树脂片的那侧被锯裂成个别”芯片”。
10.如权利要求9所述的方法，其特征在于所述晶片的薄形处理深度约为10μm。
11.一种产生一晶片级封装的方法，其特征在于一晶片乃在方形0.5mm间距有焊珠，且被锯裂成个别芯片，其中，多数所述芯片乃被焊于一铜镀合成树脂片上，其中所述铜镀合成树脂片乃具有穿孔以及一线路介入器，其自芯片侧0.5mm间距而至衬底端的一0.8mm间距，其中所述芯片乃在一加压氟化电浆下游中自后侧进行薄形化，并以一低黏性合成树脂来不足充填，以及印刷，其中所述合成树脂片在背离所述芯片侧乃具有焊珠，其次，一光敏感多分子乃被施加至所述芯片侧并被曝光与显影，因此所述芯片边缘被高分子涂覆，接着，所述合成材料片乃被锯裂成个别”芯片”。
12.如权利要求11所述的方法，其特征在于所述芯片的薄形处理深度约为10μm。
13.一种产生一晶片级封装的方法，其特征在于在方形0.5mm间距有焊珠的一晶片乃被锯裂成个别芯片，其中，所述芯片乃被焊至一印刷电路板上，而所述芯片乃在一加压氟化电浆下游环境下薄形化、洗去离子，接着并以一低黏性合成树脂来不足充填与印刷。
14.如权利要求13所述的方法，其特征在于所述芯片的薄形处理深度约为10μm。
CNA200410085694XA 2003-10-15 2004-10-15 具锯缘保护芯片之晶片级封装 Pending CN1612334A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE10348640 2003-10-15
DE10348640.2 2003-10-15
DE102004050027A DE102004050027B4 (de) 2003-10-15 2004-10-13 Verfahren zum Herstellen eines Wafer Level Packages
DE102004050027.4 2004-10-13

Publications (1)

Publication Number Publication Date
CN1612334A true CN1612334A (zh) 2005-05-04

Family

ID=34593349

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA200410085694XA Pending CN1612334A (zh) 2003-10-15 2004-10-15 具锯缘保护芯片之晶片级封装

Country Status (3)

Country Link
US (1) US7091062B2 (zh)
CN (1) CN1612334A (zh)
TW (1) TWI259564B (zh)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
PT1568071T (pt) * 2002-11-29 2019-06-17 Fraunhofer Ges Forschung Pastilha com camada de separação e camada de suporte e seu processo de fabrico
TWI328844B (en) * 2006-07-12 2010-08-11 Ind Tech Res Inst A packaging structure with protective layers and manufacture method thereof
JP5428123B2 (ja) 2006-08-16 2014-02-26 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US7791199B2 (en) * 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
EP2575166A3 (en) * 2007-03-05 2014-04-09 Invensas Corporation Chips having rear contacts connected by through vias to front contacts
US20080308932A1 (en) * 2007-06-12 2008-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structures
JP2010535427A (ja) 2007-07-31 2010-11-18 テッセラ，インコーポレイテッド 貫通シリコンビアを使用する半導体実装プロセス
US7811859B2 (en) * 2007-09-28 2010-10-12 Sandisk Corporation Method of reducing memory card edge roughness by edge coating
US7772691B2 (en) * 2007-10-12 2010-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally enhanced wafer level package
US20100053407A1 (en) * 2008-02-26 2010-03-04 Tessera, Inc. Wafer level compliant packages for rear-face illuminated solid state image sensors
US20090212381A1 (en) * 2008-02-26 2009-08-27 Tessera, Inc. Wafer level packages for rear-face illuminated solid state image sensors
US7863722B2 (en) 2008-10-20 2011-01-04 Micron Technology, Inc. Stackable semiconductor assemblies and methods of manufacturing such assemblies
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
KR101059490B1 (ko) 2010-11-15 2011-08-25 테세라 리써치 엘엘씨 임베드된 트레이스에 의해 구성된 전도성 패드
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US20130119538A1 (en) * 2011-11-16 2013-05-16 Texas Instruments Incorporated Wafer level chip size package
US8867870B2 (en) 2012-02-05 2014-10-21 Mellanox Technologies Ltd. Optical module fabricated on folded printed circuit board
US8871570B2 (en) * 2012-03-14 2014-10-28 Mellanox Technologies Ltd. Method of fabricating integrated optoelectronic interconnects with side mounted transducer
US8870467B2 (en) 2012-05-06 2014-10-28 Mellanox Technologies Ltd. Optical interface and splitter with micro-lens array
US9323014B2 (en) 2012-05-28 2016-04-26 Mellanox Technologies Ltd. High-speed optical module with flexible printed circuit board
KR102518803B1 (ko) 2018-10-24 2023-04-07 삼성전자주식회사 반도체 패키지

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5306370A (en) * 1992-11-02 1994-04-26 Xerox Corporation Method of reducing chipping and contamination of reservoirs and channels in thermal ink printheads during dicing by vacuum impregnation with protective filler material
US5851845A (en) * 1995-12-18 1998-12-22 Micron Technology, Inc. Process for packaging a semiconductor die using dicing and testing
DE19651566B4 (de) * 1996-12-11 2006-09-07 Assa Abloy Identification Technology Group Ab Chip-Modul sowie Verfahren zu dessen Herstellung und eine Chip-Karte
DE19752404C1 (de) 1997-11-26 1999-08-19 Siemens Ag Verfahren zum Herstellen eines Kontaktflächen aufweisenden Trägerelements, das ein Trägersubstrat mit einem Halbleiterchip mit sehr geringer Dicke bildet
US6350664B1 (en) * 1999-09-02 2002-02-26 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
JP4687838B2 (ja) * 2000-04-04 2011-05-25 株式会社ディスコ 半導体チップの製造方法
JP2002353369A (ja) * 2001-05-28 2002-12-06 Sharp Corp 半導体パッケージおよびその製造方法
DE10164494B9 (de) 2001-12-28 2014-08-21 Epcos Ag Verkapseltes Bauelement mit geringer Bauhöhe sowie Verfahren zur Herstellung

Also Published As

Publication number Publication date
TWI259564B (en) 2006-08-01
TW200522305A (en) 2005-07-01
US7091062B2 (en) 2006-08-15
US20050110156A1 (en) 2005-05-26

Similar Documents

Publication Publication Date Title
CN1612334A (zh) 具锯缘保护芯片之晶片级封装
CN1221028C (zh) 半导体装置及其制造方法和安装方法
CN101312162B (zh) 一种制造半导体器件的方法
US8313982B2 (en) Stacked die assemblies including TSV die
US7915080B2 (en) Bonding IC die to TSV wafers
JP4719042B2 (ja) 半導体装置の製造方法
US8058098B2 (en) Method and apparatus for fabricating a plurality of semiconductor devices
JP2004072009A (ja) 半導体装置及びその製造方法
CN1697127A (zh) 制造半导体器件的方法
CN1174486C (zh) 半导体器件及其制造方法
EP3038144B1 (en) A process for manufacturing a package for a surface-mount semiconductor device
KR101681360B1 (ko) 전자부품 패키지의 제조방법
CN1945805A (zh) 半导体封装方法以及用于半导体封装的载体
CN101807531A (zh) 一种超薄芯片的封装方法以及封装体
CN1242463C (zh) 叠层式半导体器件的制造方法
CN1144284C (zh) 半导体器件及其制造方法
US20040002181A1 (en) Microelectronic assembly with die support and method
CN1667421A (zh) 传感器器件
JP2000228465A (ja) 半導体装置及びその製造方法
US7122407B2 (en) Method for fabricating window ball grid array semiconductor package
CN109003946B (zh) 封装结构及其制造方法
US20070273022A1 (en) Semiconductor device
KR102012789B1 (ko) 반도체 장치
CN1257540C (zh) 一种半导体芯片封装方法及其封装结构
TWI624008B (zh) 引線架面陣列封裝技術

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication