CN1706038A - 通过掩埋氧化物层中的压缩材料导入张力应变硅的半导体器件 - Google Patents

通过掩埋氧化物层中的压缩材料导入张力应变硅的半导体器件 Download PDF

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CN1706038A
CN1706038A CNA2003801016755A CN200380101675A CN1706038A CN 1706038 A CN1706038 A CN 1706038A CN A2003801016755 A CNA2003801016755 A CN A2003801016755A CN 200380101675 A CN200380101675 A CN 200380101675A CN 1706038 A CN1706038 A CN 1706038A
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D·J·瑞斯特
相奇
J·F·布勒
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Abstract

一种在不需要形成硅锗层的情况下，提供绝缘体上硅(SOI)与应变硅技术的高速能力的半导体器件。在SOI半导体衬底(20)上形成压缩材料层(22)，以引起在覆盖硅层(21)中的应变。该压缩材料包括氧氮化硅、磷、氮化硅以及硼/磷掺杂的硅玻璃。

Description

通过掩埋氧化物层中的压缩材料导入张力应变硅的半导体器件
技术领域
本发明涉及半导体器件的制造，更具体地，涉及包含绝缘体上硅(SOI)技术的改良半导体器件。
背景技术
在半导体工业中持续研究的重要目标是在降低半导体器件中的功率的同时，增加半导体性能。平面晶体管，譬如金属氧化物半导体场效应晶体管(MOSFET)，特别适合在高密度的集成电路中使用。随着MOSFET与其它器件尺寸的减少，该器件的源极/漏极区域、沟道区域与栅极电极的尺寸也会减少。
具有短沟道长度的持续变小的平面晶体管的尺寸必须提供非常浅的源极/漏极结。浅结对避免注入掺杂物横向扩散入沟道内极为必要，这是因为此扩散会不利地导致漏电流与差的击穿性能。厚度大约为1000埃或更小的浅源极/漏极结通常是短沟道器件的可接受性能所需要的。
绝缘体上硅(SOI)技术可用以形成高速、浅结器件。此外，SOI器件通过减少寄生的结电容值而改善性能。虽然SOI技术改善浅结器件的性能，但是需要较深结的器件则不会从SOI受益。例如，对温度敏感或需要深注入的器件形成在整块衬底上会有较佳的表现。
在SOI衬底中，由氧化硅制成的掩埋氧化物(BOX)薄膜形成在单晶硅上，且该氧化物薄膜上会形成单晶硅薄膜。制造此SOI衬底的种种方法为已知的。一种方法为SIMOX(注氧隔离)，其中氧被离子注入于单晶硅衬底内，以形成掩埋氧化物薄膜(BOX)。
形成SOI衬底的另一方法为晶片接合，其中具有氧化硅表面层的两个半导体衬底在氧化硅表面处接合在一起，以在两个半导体衬底之间形成BOX层。
另一SOI技术为Smart Cut(智能剥离)，其同样包含经由氧化物层来接合半导体衬底。在Smart Cut方法中，其中的一个半导体衬底在接合之前被掺杂了氢离子。随后，氢离子掺杂将会受到氢离子掺杂的衬底从接合的衬底分开，而在表面上留下薄硅层。
应变硅技术同样可形成较高速度的器件。形成应变硅晶体管的方法是通过将硅锗(SiGe)的渐变层(graded layer)沉积于整块硅晶片(bulk silicon wafer)上。接着在SiGe上沉积薄硅层。在SiGe晶格中原子之间的距离比在一般硅晶格中原子之间的距离还大。因为当将一晶体形成在另一晶体上时，不同晶体内的原子会自然地倾向于彼此对齐，所以当硅沉积在SiGe顶部时，硅原子则倾向于伸长或“应变”(strain)，以对齐SiGe晶格中的诸原子。应变硅中的电子会遭受较少的阻力，并且比在一般晶体硅中流动还快达80％。
在此所使用的半导体器件名称并未受限于具体揭露出的具体实施例。在此所使用的半导体器件包括各种电子器件，该电子器件包括倒装晶片、倒装晶片/封装组件、晶体管、电容器、微处理器、随机存取存储器等等。一般而言，半导体器件指的是包含半导体的任何电性器件。
发明内容
在该半导体器件技术中，需要结合了SOI技术与应变硅技术的性能改善的器件。在此技术中，需要一种半导体器件，该器件包含形成应变硅层，而不在该衬底上形成SiGe晶格。
这些与其它需求由本发明的具体实施例满足，其提供包含半导体衬底以及在该半导体衬底上的压缩材料层的半导体器件。在该压缩材料层上形成应变硅层。
也可由本发明某些具体实施例满足上述的需求，这些具体实施例提供一种形成具有应变硅层的半导体器件的方法，其包含提供半导体衬底以及在该衬底上形成压缩材料层。在该压缩材料层上形成应变硅层。
本发明满足具有改善电性特征的改善高速半导体器件的需求。本发明的上述与其它特征、态样与优点，将在本发明以下详细说明合并附图中变得明显可见。
附图说明
图1A至1H说明使用SmartCut(智能剥离)工艺的SOI半导体器件的形成，该器件具有掩埋在氧化物层中的压缩材料层；
图2A至2G说明使用晶片接合技术的SOI半导体器件的形成，该器件具有掩埋在氧化物层中的压缩材料层；
图3A至3E说明在具有掩埋氧化物层中的压缩材料层的SOI半导体衬底上形成场效应晶体管；
图4A至4C说明在源极/漏极区域中形成具有应变硅沟道与较高程度的砷掺杂物的场效应晶体管。
具体实施方式
本发明能够生产具有SOI与应变硅技术两者优点的改良高速半导体器件。本发明进一步通过耦合SOI的降低寄生结电容的优点与应变硅技术来提供较高的速度。这些优点通过结合应变硅层与SOI半导体衬底而提供。
将结合在附图中所说明的半导体器件的形成而说明本发明。不过，这仅是示例性的，本申请发明并不局限在图式中所说明的具体器件的形成。
首先将说明使用Smart Cut技术在SOI衬底上形成半导体器件的方法。上部部分10由以下步骤所形成：如图1A图所示，设置单晶硅晶片12。如图1B所示，在硅晶片12上形成一层热生长的硅氧化物14。如图1C所示，将氢离子16注入到硅晶片12里达到预定深度18，以形成上部部分10。注入的氢离子会在受到注入的晶片中产生微穴、微气泡或微泡。当微穴的密度与尺寸将穴的距离减少到某一临限以下时，会发生穴内的裂缝并且裂缝经过渗透型过程而扩散。如以下所述，这最后会导致晶片12的裂开。
设置下部部分40，以接合到上部部分10。按如下过程形成下部部分40：半导体衬底20设有形成于其上的压缩材料层22(见图1D)。该压缩材料可以包括含磷离子增强化学气相沉积(PECVD)的硅氧氮化物(SiOxNy)，氮化硅(Si3N4)以及硼/磷掺杂的硅玻璃(BPSG)的多数压缩材料的任何一种。压缩材料层22可以由多种传统技术所沉积，包括化学气相沉积(CVD)。压缩材料22沉积成大约500埃至大约2000埃的厚度。
如图1E所示，BOX层26是由SIMOX(注氧隔离)工艺所形成。在SIMOX工艺中，氧离子24注入到半导体衬底20内。在本发明的某些具体实施例中，氧离子24是以从大约70keV至大约200keV范围的能量并且以大约1.0×1017cm-2至大约1.0×1018cm-2的范围的剂量而注入在半导体衬底20内。在注入以后，在包含惰性气体以及从大约0.2％至2.0％氧气的气氛中，下部部分40会在从约1250℃至1400℃的范围的温度上退火达大约4至大约6小时，以形成BOX层26。退火气氛中的氧会在下部部分40上形成薄氧化物层28。氧化物层28会改善后续氢离子注入上部部分10的黏结性。
如图1G所示，上部部分10与下部部分40在其所各自具有的氧化物层14与28的表面41处彼此接合。在某些具体实施例中，上部部分10与下部部分40的接合表面19、29会抛光成低表面粗糙度，例如2埃微米2RMS。如图1G所示，将下部部分10与上部部分40一起挤压，并且从约900℃至约1200℃范围的温度，在一惰性气氛中加热达约5分钟至约5小时，以熔合该下部部分10与上部部分40。
在某些具体实施例中，将氧化剂，譬如H2O2或者HNO3与H2O2水溶液滴设置在该上部部分10与下部部分40之间的界面中。氧化剂通过允许相当低温度的接合，经由在接合液体中提供掺杂物而具有较佳的应力补偿，并通过使用该接合液体中的掺杂物而限制污染物徙动来改进接合过程，其中该接合液体将产生具有紧密匹配衬底晶片的热扩张系数的接合层，该接合液体中的掺杂物将提供用于阻挡可动污染物扩散的接合层。
合并的晶片/半导体衬底42在约1100℃上退火达约2小时。此退火步骤造成微穴在掺杂氢的上部部分10中扩散，而造成晶片12裂开。上部部分10的整块硅部分44随后会离开下部部分40，而留下黏结的硅层21。因而如图1H所示，会得到在BOX层上形成有压缩材料层的SOI衬底。在某些具体实施例中，在形成半导体结构46以后(见图1H)，由于裂开的SOI结构呈现微粗糙状所以抛光该结构46。
SOI半导体结构46包含第一绝缘层26(下部BOX层)，与第二绝缘层48(氧化物层14与28(上部BOX层))，而压缩材料层22则插入其间。该第一绝缘层26与第二绝缘层48的各自厚度是从约500埃到约4000埃。在本发明的某些具体实施例中，在垂直方向上，压缩材料层22大致上放置于该第一绝缘层26与第二绝缘层48之间，虽然该压缩材料层22没有必需垂直地放置于该绝缘层26、48之间。该压缩材料层22致使硅层21中从大约0.2％至大约1.5％的晶格不匹配。
另一方法所解释的，是在SOI半导体衬底上产生应变硅层，并在BOX层之间形成压缩材料层的半导体器件。上部部分80由以下步骤所形成：如图2A所示，将轻微掺杂的外延硅层32生长在重掺杂的硅衬底上30。接着将氧化物层34形成在硅层32上。在某些具体实施例中，通过硅层32的热氧化来形成氧化物层34。在某些具体实施例中，氧化物层34譬如通过CVD(化学气相沉积)而沉积。
设置下部部分82以接合到上部部分80。下部部分82形成如下：如t图2C所示，轻微掺杂的硅半导体衬底20上形成有压缩材料层。如先前具体实施例所描述的，氧离子24通过SIMOX工艺注入到半导体衬底20内。如图2D所示，接着将半导体衬底20退火以形成BOX层26。如图2E所示，在惰性气体与约0.2％至约2％氧气的气氛中进行退火，以形成氧化物层28。在某些具体实施例中，例如通过CVD来沉积氧化物层28。在某些具体实施例中，在接合上部部分80与下部部分82以前，将接合表面84与86抛光。将上部与下部部分80、82一起挤压，以使各氧化物层34、28的接合表面84、86接触，并且如图2F所示，在约900℃至约1200℃，将合并的结构88退火5分钟至5小时，以影响接合。在某些具体实施例中，在上部与下部部分80、82接合以前，将一滴譬如过氧化氢或者硝酸以及双氧水溶液等氧化溶液沉积在接合表面84、86的其中之一上。
待氧化物层28、34熔合以后，该重掺杂的衬底30会譬如通过优先蚀刻重掺杂的衬底30以提供具有应变硅层32的SOI半导体器件90，其中通过插入在BOX层26、92之间的压缩材料层22引起应变。
该压缩材料层22包含磷的PECVD、BPSG、SiOxNy或者Si3N4。压缩材料层22的厚度从约500埃至约2000埃。下部BOX层26与上部BOX层92的各自厚度从约500埃至约4000埃。在本发明的某些具体实施例中，在垂直方向上，压缩材料层22大致上放置于下部BOX层26与上部BOX层92中间。压缩材料层22致使应变硅层32从约0.2％到约1.5％的晶格不匹配。
讨论一种形成譬如金属氧化物半导体场效应晶体管(MOSFET)的半导体器件的方法。在两BOX层26，92之间形成具有应变硅层32与压缩材料层22的SOI半导体器件94，设有一栅极氧化物层50与形成在该栅极氧化物层50上的栅极导电层51。栅极氧化物层50以传统的方法而形成，譬如通过硅层32的热氧化或者CVD(化学气相沉积)。栅极导电层51由传统材料所形成，譬如多晶硅或金属。如图3B所示，该结构94譬如通过光刻图形化而被图形化，以形成具有栅极导体52的栅极结构96。然后，最终的结构会经历掺杂物的注入，以形成源极/漏极延伸部分54。通过传统的方法进行掺杂物的注入，在某些具体实施例中，这些方法包括在半导体器件94上形成光刻胶掩膜以及传统的掺杂物的注入。
如图3D所示，接着将氮化硅层沉积在半导体结构94上并予以各向异性蚀刻，以形成侧壁间隔物56。如图3E图所示，半导体结构接着根据传统方法经历较重的掺杂以形成源极/漏极区域58。将最终结构94退火，以激活源极/漏极区域58，在具有应变硅沟道的SOI衬底上形成MOSFET半导体器件。
在其它方式中，应变硅层则形成在SiGe层上。当将砷(As)掺入包含形成在SiGe层上的应变硅层的半导体器件中时，As在SiGe中扩散地比在应变硅中还慢。图4A至4C显示了形成在具有SiGe层的半导体衬底20上的MOSFET半导体器件。浅沟隔离区域66会隔离MOSFET 98与邻近的MOSFET。由于硅晶格应变以匹配SiGe层60的晶格间距，所以SiGe层60会引起硅层62中的晶格应变。会在应变硅层62中形成轻微掺杂的源极/漏极延伸部分64。
如图4B所示，砷68以增加的剂量来注入，以补偿在SiGe层60中砷的缓慢扩散。随后将半导体器件98退火，以激活源极/漏极区域70。
如图4C所示，导电硅化物层72形成在栅极结构96以及源极/漏极区域70上。导电硅化物层的形成是通过将譬如钴或镍的金属沉积在半导体结构98上并且接着将半导体结构98退火，以使该金属与源极/漏极区域70与栅极导体52中的硅反应，从而形成金属硅化物72。如图4C所示，接着将未起反应的金属从半导体器件98移除。
增加剂量的砷离子会减少源极漏极区域以及源极/漏极延伸部分的薄层电阻，以减少寄生的源极/漏极电阻。增加剂量的砷离子也会减少硅/硅化物的接触电阻。此外，对SiGe层的低势垒高度则会进一步减少硅/硅化物的接触电阻。
本发明的方法提供一种具有绝缘体上硅与应变硅技术的高速性能的改良半导体器件。该半导体衬底上的压缩材料层允许形成应变硅层无须形成SiGe底层。
在本揭露中所显示的具体实施例仅用于说明。它们不应该推断来限制权利要求。本领于技术人员应当清楚的是，本发明包含没有具体说明在其中的各种具体实施例。

Claims (10)

1.一种半导体器件，包含：
半导体衬底(20)，
在该半导体衬底(20)上的压缩材料层(22)，以及
在该压缩材料层上(20)的应变硅层(21)。
2.如权利要求1所述的半导体器件，还包含插入在压缩材料层(22)与衬底(20)之间的第一绝缘层(26)。
3.如权利要求1所述的半导体器件，还包含插入在压缩材料层(22)与应变硅层(21)之间的第二绝缘层(48)。
4.如权利要求3所述的半导体器件，还包含在该衬底(20)与该压缩材料层(22)之间的绝缘层(26)。
5.如权利要求4所述的半导体器件，其中在垂直方向中，该压缩材料层(22)放置在该第一绝缘层(26)与第二绝缘层(48)之间。
6.一种形成具有应变硅层(21)的半导体器件的方法，包含：
设置半导体衬底(20)，
在该半导体衬底上(20)形成压缩材料层(22)，以及
在该压缩材料层上(22)形成应变硅层(21)。
7.如权利要求6所述的方法，其中该压缩材料层(22)由磷的离子增强化学气相沉积、硼/磷掺杂硅玻璃的沉积、SiOxNy或者Si3N4所形成。
8.如权利要求6所述的方法，还包含在半导体衬底(20)与压缩材料层(22)之间形成第一绝缘层(26)。
9.如权利要求8所述的方法，还包含在压缩材料层(22)与应变硅层(21)之间形成第二绝缘层(48)。
10.如权利要求9所述的方法，其中该第一绝缘层(26)与第二绝缘层(48)为掩埋氧化物层。
CNB2003801016755A 2002-10-18 2003-10-14 通过掩埋氧化物层中的压缩材料导入张力应变硅的半导体器件及其形成方法 Expired - Lifetime CN1320628C (zh)

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