TWI324787B - Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer - Google Patents

Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer Download PDF

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TWI324787B
TWI324787B TW092128684A TW92128684A TWI324787B TW I324787 B TWI324787 B TW I324787B TW 092128684 A TW092128684 A TW 092128684A TW 92128684 A TW92128684 A TW 92128684A TW I324787 B TWI324787 B TW I324787B
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layer
strained
semiconductor device
compressed material
oxide
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TW200416788A (en
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Derick J Wristers
Qi Xiang
James F Buller
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Advanced Micro Devices Inc
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support

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Description

1324787 玖、發明說明 [發明所屬之技術領域] 本發明係關於半導體裝置之製造’更尤其係關於包含 矽在絕緣體上（SOI)技術的改良半導體裝置。 [先前技術] 在半導體工業中持續研究的重要目標乃是當在半導體 裝置中之功率耗損減少時，半導體性能的增加。平面電晶 體’譬如金屬氧化物半導體場效電晶體（MOSFET)，係特別 適合在高密度的積體電路中使用。隨著MOSFET與其它裝 置尺寸的減少，該裝置之源極/汲極區域、通道區域與閘極 電極的尺寸亦會減少。 具有短通道長度之持續變λΙ、平面電晶體的尺寸有必要 提供非常淺的源極/没極接面（junction)。淺接面對避免植 入摻雜物橫向擴散入通道内有其必要性，此乃因為此擴散 不利於促成漏電流與貧乏的分解性能。厚度大約為1〇〇〇 埃或更小的淺源極/汲極接面，一般為短通道裝置之可接受 性能所需要。 石夕在絕緣體上（SOI)技術可用以形成高速、淺接面裝 置。此外’ SOI裝置藉由減少寄生接面電容而改善性能。 雖然SOI技術改善淺接面裝置的性能’但是需要較深接面 的裝置則不會從SOI受益。例如，當將對溫度敏感或需要 深植入的裝置形成於塊狀基板時，其會有較佳的表現。 在SOI基板中’氧化矽所製成的埋設氧化物（Β〇χ)薄 膜係形成於單晶矽上，且該氧化物薄膜上會形成單晶矽薄 5 92448修正本 1324787 膜。製造此SOI基板的種種方法係為已知。此方法係為氧 植入隔離（separati〇n-by_Implanted 〇xygen，siM〇x)，其中 氧係離子植入於單晶矽基板内，以形成埋設氧化物薄膜 (BOX) 〇 形成SOI基板的另一方法係為晶圓焊接其中具有氧 化矽表面層的兩半導體基板一起焊接於氧化矽表面;'以在 兩半導體基板之間形成BOX層。 另一 soi技術係為SmartCut(商品名），其同樣包含經 由氧化物層來焊接半導體基板。在Smart Cut(商品名）方法 中’其中之一半導體基板是在焊接之前摻雜以氫離子。隨 後，氫離子摻雜將會受到氫離子摻雜的基板自予以焊接的 基板分開，而在表面上留下薄矽層。 應變矽（strained silicon)技術同樣形成較高速度裝 置。形成應變矽電晶體的方法係藉著將矽鍺（SiGe)之漸變 層（graded layer)沈積於整片原材料狀矽晶圓（buik s出c〇n wafer)上。薄矽層接著則沈積於SiGe上。在siGe晶格中 原子之間的距離比在一般矽晶格中原子之間的距離還大。 因為當將一晶體形成於另一晶體時，不同晶體内的原子會 自然地傾向於彼此對齊，所以當矽沈積於SiGe頂部時，矽 原子則傾向於伸長或、應變（strain)"，以對齊SiGe晶格 (lattice)中的諸原子。在應變矽中的電子會遭受較少的阻 力’並且比在一般結晶石夕中流動還快達8 〇 %。 在此所使用的半導體裝置名稱並未受限於具體揭露出 的具體實施例。在此所使用的半導體裝置包括種種電子裝 6 92448修正本 f ’該電子裝置包括覆晶、覆晶/封裝組件、電晶體、電容 β、微處理器、隨機存取記憶體等等。—般而言，半導體 裝置指的是包含半導體的任何電性裝置。 [發明内容] 在該半導體裝置技術中’需要結合將·技術與應變 石夕技術之性能改善的裝置。在此技術中，需要一種半導體 裝置’該裝置包含形成應變矽層，而不將siGe晶格（lauice) 形成於該基板上0 這些與其它需求係由本發明的具體實施例所滿足，其 係提供包含半導體基板以及於該半導體基板上壓縮材料層 的半導體裝置。該壓縮材料層上係形成應變矽層。 較早陳述的需求同樣可由本發明某些具體實施例所滿 足，該些具體實施例提供一種形成具有應變矽層之半導體 裝置的方法，纟包含冑供半導體基板以及在該基板上形成 壓縮材料層。該壓縮材料層上則形成應變矽層。 本發明滿足具有改善電性特徵之改善高速半導體裝置 的需求。 本發明的上述與其它特徵、態樣與優點，將在本發明 以下詳細說明合併附圖中變得明顯可見。 [實施方式] 本發明能夠生產具有S0I與應變矽技術兩者優點之改 良高速半導體裝置。本發明進一步藉由耦合S0I之降低寄 生接面電容優點之應變矽技術來提供較高速度。這些優點 係藉著結合應變矽層與SOI半導體基板而提供。 7 92448修正本 /δ/ 、本發明將結合在附圖中所說明之半導體裝置的形成而 說明。不過，這僅僅由於本申請發明未侷限在圖式中所說 明之具體裝置的形成而作為實例。 首先將說明使用Smart Cut(商品名）技術而將半導體 農置形成於soi基板上的方法。上部部份（upper secti〇n)i〇 係由以下步驟所形成：如第丨A圖所示，設置單晶矽晶圓 12。如第1B圖所示，於矽晶圓12上形成受熱生長的矽氧 化物層14。如第1C圖所示，將氫離子16植入於矽晶圓 12裡達一預定深度18 ,以形成上部部份1〇。植入的氫離 子會在受到植入的晶圓中產生微穴、微氣泡或微泡。當微 八的雄、度與尺寸將穴的距離減少到某一臨限以下時，穴内 的裂縫則會發生並且經由一滲透型態的製程而擴散。如以 下所述’這最後會導致晶圓12的裂開。 設置下部部份（l〇wer section)40，以銲接到上部部份 10。下部部份40係形成如下：半導體基板2〇設有形成於 其上之壓縮材料層22(見第1D圖）^該壓縮材料可以包括 夕數壓縮材料的任何一種，包含矽氧氮化物（Si〇xNj、電 漿辅助化學氣相沉積（PECVD)的磷、氮化矽（Si3N4)以及硼/ 磷摻雜氧化矽玻璃（BPSG) ^壓縮材料層22可以由多數種 駕知技術所沈積，包括化學氣相沈積（CVD)。壓縮材料22 係沈積成大約500埃至大約2000埃的厚度。 如第1E圖所示，BOX層26係由SIMOX製程所形成。 在SIMOX製程令，氧離子24係植入於半導體基板2〇内。 在本發明的某些具體實施例中，氧離子24係以從大約 8 92448修正本 1324787
70keV至大約200keV範图的鈐旦并Q 軏圍的靶里並且以大約丨〇xl〇17cm_2 至大約1.0x10 cm之範圍的劑詈而括 宵量而植入於半導體基板20 内。在植入以後’在包含惰性裔興，、f n 滑性乳體以及從大約0.2%至2.0 %氧氣的氣氛中，下部部份合—似
I司伤40會在從約125(TC至140(TC 之範圍的溫度上退火達大約4至大約6小時以形成Β〇χ 二 6。退火氣氛中的氧會在下部部份4。上形成薄氧化物 層28。氧化物層28會改善後續氫 Λ [離于植入上部部份10的 黏結性。 =1G圖所示，將上部部份1()與下部部份4〇彼此 焊接在其所各自具有之氧化物層14與28的表面Μ。在某 些具體實施例中，上部部份1〇與下部部份4〇的焊接表面 Ή抱光成低表面粗糖度，…埃微米 y m2RMS)。如第1G圖所 將下°卩σ卩伤1 〇與上部部份 一起擠麼，並且從約_至約12〇『c範圍的溫度在 =性氣氛中加熱達約5分鐘至約5小時，以熔化該下部 部份10與上部部份40。 在某些具體實施例中，蔣氦/μ細后条， 只也例甲將氧化劑，譬如^…或者ην〇3 與Η2〇2水溶液滴設置在該上部部份1〇與下部部份4〇之間 的界面卜以藉由相#低溫度料接，經由在谭接液體令 ^供摻雜物而具較佳的應力⑽ess)補償，該谭接液體將產 y有緊密匹配基板晶圓之熱擴張係數的谭接層，而且藉 者使用該详接液體中的掺雜物而限制污染物徙動，該详接 液體將用於阻擋可動污染物擴散的焊接層。 合併的晶圓/半導體基板42在約· t上退火達約2 92448修正本 9 1^24787 J、時此退火步驟造成在摻雜氩上部部份i〇的微穴擴散， 而4成SB圓12裂開。上部部份10的塊狀矽部份44隨後會 離開下部部份4〇，而留下黏結的矽層21。因而如第1H圖 所不’會得到於Β〇χ層中形成壓縮材料層的s〇I基板。
在某些具體實施例中，在形成半導體結構46以後（見第1H 圖）’該結構46會因為裂開的SOI結構呈現微粗糙狀故予 以抛光。
SOI半導體結構46包含第一絕緣層26(下部BOX 層）’與第二絕緣層48(氧化物層14與28(上部BOX層））， 而壓縮材料層22則插入其間。該第一絕緣層26與第二絕 緣層48的厚度各從500埃到4000埃。在本發明的某些具 體實加例中’在垂直方向上’壓縮材料層大致上放置於 該第一絕緣層26與第二絕緣層48之間，雖然該壓縮材料 層22沒有必需垂直地放置於該絕緣層％、48之間。該壓 縮材料層22致使矽層21從大約0.2%至大約1.5%的晶格 不匹配。 另一方法所解釋的’係在SOI半導體基板上產生應變 石少層’並於BOX層之間形成壓縮材料層之半導體裝置。上 部部份80係由以下步驟所形成：如第2A圖所示，將輕微 摻雜的外延矽層32生長於重濃度摻雜的（heavily doped)矽 基板3〇上。接著將氧化物層34形成於矽層32上》在某些 具體實施例中，氧化物層34之形成係藉由矽層32的熱氧 化。在某些具體實施例中，氧化物層34譬如藉由CVD而 沈積。 10 92448修正本 丄: 叹置下部部份82以銲接到上部部份8〇。下部部份82 係形成如下·如第2C圖所示，輕微摻雜的矽半導體基板 20上形成有壓縮材料層。如先前具體實施例所描述的，氧 離子24係藉由SIM〇x製程而植入於半導體基板2〇内。 如第2D圖所示，接著將半導體基板2〇退火以形成Β〇χ 層26。如第2E圖所示，在惰性氣體與約〇 2%至約2%氧 氣的氣氛中進行退火，以形成氧化物層28。在某些具體實 施例中，在焊接上部部份8〇與下部部份82以前，將焊接 表面84與86拋光。將上部與下部部份8〇 ' 82 一起擠壓， 以使各氧化層34、28的焊接表面84、86接觸，並且如第 2F圖所不’在約9〇〇〇c至約12〇〇艽，將合併的結構a退 火900分鐘至5小時，以影響焊接。在某些具體實施例中， 在上部與下部部份8〇、82焊接以前，將一滴譬如過氧化氫 或者硝’酸以及雙養水溶液等氧化溶液沈積於焊接表面 84、86的其中之一上。 待氧化物層28、34熔化以後，該濃密摻雜的基板3〇 會·#如藉由優先蝕刻濃密摻雜的基板3〇以提供具有應變 矽層32的SOI半導體裝置9〇，其中藉由插入於Β〇χ層 26、92之間的壓縮材料層22引起應變。 該壓縮材料層22包含含磷的PECVD、BPSG、SiOxNy 或者SisN4。壓縮材料層22的厚度係從約5〇〇埃至約2〇〇〇 埃。下部BOX層26與上部box層92的厚度各從約500 埃至約4000埃。在本發明的某些具體實施例中，在垂直方 向上，壓縮材料層22大致上放置於下部Β〇χ層26與上部 11 92448修正本 1324787 BOX層92中間。壓縮材料層22 %到約⑸的晶格不匹配。便應變…2從約0.2 討論一種形成譬如金屬 (MOSFET)之半導體裝 導體場效電晶體 形成具有應變…與=二=X…之間 層2的卿半導體裝置 二=極氧化物層5。與形成於該閑極氧化層5。上的 間極氧化物層5〇以習知的方法而形成， 3如藉由石夕層32的熱氧化或者CVD。閘極導電層Η係由 習知材料所形成’譬如多晶石夕或金屬。如第圖所示， 該結構94係譬如藉由光微影圖案化而被圖案化，以形成具 有閘極導體52的閘極結構96。然後’最終的結構會經歷 摻雜物之植入，以形成源極/汲極延伸部份54。摻雜物的 植入乃藉由習知方法而進行，在某些具體實施例中，該些 方法包括;^半導體裝f 94 ±形成絲遮罩以及習知摻雜 物的植入。 如第3D圖所示，接著將氮化石夕層沈積於半導體結構 94上並予以非等向性蝕刻，以形成侧壁間隔件 spaCer)56。如第3E圖所示，半導體結構接著根據習知方 法經歷較密集的摻雜以形成源極/汲極區域58。將最終結 構94退火，以活化源極/汲極區域58，於具有應變矽通道 的SOI基板上形成MOSFET半導體裝置。
在其它態樣中，應變矽層則形成於SiGe層上。當將~ (As)捧雜入包含應變碎層形成於SiGe層上的半導體裝置 時，As在SiGe中擴散地比在應變矽中還慢。第4A至4C 12 92448修正本 工324787 圖顯示MOSFET半導體裝置形成於具有SiGe層的半導體 基板20上。淺溝隔離區域66會隔離MOSFET98與鄰近的 MOSFET。由於矽晶格應變以匹配SiGe層60的晶格間距， 所以SiGe層60會引起矽層62中的晶格應變。會形成於應 變石夕層62中輕微摻雜的源極/汲極延伸部份64。 如第4B圖所示，砷68係以一增加的劑量來植入，以 補償在SiGe層60中砷的緩慢擴散。隨後將半導體裝置％ 退火’以活化源極/没極區域70。 如第4C圖所示’導電矽化物層72係形成於閘極結構 96以及源極/汲極區域7〇上。導電矽化物層之形成係藉由 將譬如録或鎳之金屬沈積於半導體結構98上並且接著將 半導體結構98退火，以使該金屬與源極/汲極區域7〇與閘 極導體52中的矽反應，而形成金屬矽化物72。如第4C圖 所不’接著將未起反應的金屬自半導體裝置98移除。 增加劑量的砷離子會減少源極汲極區域以及源極/沒 極延伸部份的薄層電阻，以減少寄生的源極/汲極電阻。增 加劑量的砷離子同樣會減少矽/矽化物的接觸電阻。此外， 對SiGe層的低阻障層高度則會進一步減少矽/矽化物的接 觸電阻。 本發明的方法提供一種具有矽在絕緣體上與應變矽技 術之高速性能的改良半導體裝置。該半導體基板上的壓縮 材料層形成應變矽層無須形成SiGe底層。 在本揭露中所顯示的具體實施例僅用於說明。它們不 應該推斷來限制本申請專利範圍。將為一般熟諳該技藝者 13 92448修正本 1324787 所清楚的是，本發明包含沒有具體說明於其中的種種具體 實施例。 [圖式簡單說明] 第1A至1H圖說明使用SmanCut(商品名）製程之SOI 半導體裝置的形成，該裝置具有於埋設氧化物層中之壓縮 材料層。 第2A至2G圖說明使用晶圓焊接技術之s〇i半導體裝 置的形成，該裝置具有於埋設氧化物層中之壓縮材料層。 第3A至3E圖說明在埋設氧化物層中形成具有壓縮材 料層之SOI半導體基板上之場效電晶體。 第4A至4C圖說明在源極/沒極區域中形成具有應變 矽通道與較高程度之砷摻雜物之場效電晶體。 [支要元件符號說明] 10、80 上部部份 12 矽晶圓 14氧化物層 16 氫離子 18 2〇 22 26 28 3〇 34 41 48 預定深度 19 ' 84 > 86焊接表面 9〇 S01半導體基板21、62矽層 壓縮材料層 24 氧離； 第一絕緣層（下部BOX層） 氧化物層 碎基板 氧化物層 表面 第二絕緣層 29 焊接表面 32 外延矽層 40、82下部部份 46 半導體結構 5〇 閘極氧化物層 92448修正本 14 1324787
51 閘極導電層 52 閘極導體 54、 64 源極/汲極延伸部份 56 側壁間隔件 58、 70 源極/没極區 60 SiGe 層 66 淺溝隔離區域 68 石申 72 導電矽化物層 88 合併的結構 92 上部BOX層 94 SOI半導體結構 96 閘極結構 98 MOSFET 15 92448修正本

Claims (1)

1324787 2第92丨28684號專利申請案 (98年1〇月如日）必林 拾、申請專利範圍： k 一種半導體裝置，包含： 半導體基板（20); 在該半導體基板（20)上之壓縮材料層（22); 在該壓縮材料層上（22)之應變矽層（21)，該應變矽 層奋猎由該壓縮材料層而產生應變；以及 插入於該壓縮材料層（22)與該基板（2〇)之間之第— 氧化砂層（26)。 2. 如申請專利範圍第〗項之半導體裝置，復包含插入於該 壓縮材料層（22)與該應變矽層（21)之間之第二氧化矽層 (48)。 3. 如申請專利範圍第1項之半導體裝置，其中在垂直方向 中’該壓縮材料層（22)係放置於該第一氧化珍層（26)與 該第二氧化矽層（48)之間。 4. 一種形成具有應變矽層（21)之半導體裝置的方法，包 含： 設置半導體基板（20); 形成壓縮材料層（22)於該半導體基板（2〇)上； 形成應變矽層（21)於該壓縮材料層（22)上，該應變 矽層係藉由該壓縮材料層而產生應變；以及 在該半導體基板（20)與該壓縮材料層（22)之間形成 第一氧化矽層（26)。 5.如申請專利範圍第4項之方法，其中該壓縮層（22)係從 碟的電漿輔助化學氣相沈積 '糊/填摻雜石夕玻璃之沈 】6 92448修正本 1324787 第92128684號專利申請案 (98年10月」〇日） 積、SiOxNy或者Si3N4所形成。 6. 如申請專利範圍第4項之方法，復包含在該壓縮材料層 (22)與該應變矽層（21)之間形成第二氧化矽層（48)。 7. 如申請專利範圍第6項之方法，其中該第一氧化矽層 (26)與該第二氧化矽層（48)係為埋設氧化物層。 17 92448修正本
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Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1309989B1 (en) * 2000-08-16 2007-01-10 Massachusetts Institute Of Technology Process for producing semiconductor article using graded expitaxial growth
US6940089B2 (en) * 2001-04-04 2005-09-06 Massachusetts Institute Of Technology Semiconductor device structure
US7060632B2 (en) * 2002-03-14 2006-06-13 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7307273B2 (en) * 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US7335545B2 (en) * 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US20030227057A1 (en) * 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
JP3664704B2 (ja) * 2002-10-03 2005-06-29 沖電気工業株式会社 半導体装置
KR100498475B1 (ko) * 2003-01-07 2005-07-01 삼성전자주식회사 모스 전계 효과 트랜지스터 구조 및 그 제조 방법
US6916694B2 (en) * 2003-08-28 2005-07-12 International Business Machines Corporation Strained silicon-channel MOSFET using a damascene gate process
US7144818B2 (en) * 2003-12-05 2006-12-05 Advanced Micro Devices, Inc. Semiconductor substrate and processes therefor
JP2006041135A (ja) * 2004-07-26 2006-02-09 Sumitomo Bakelite Co Ltd 電子デバイスおよびその製造方法
CN100527416C (zh) * 2004-08-18 2009-08-12 康宁股份有限公司 应变绝缘体上半导体结构以及应变绝缘体上半导体结构的制造方法
US7112848B2 (en) * 2004-09-13 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Thin channel MOSFET with source/drain stressors
US7078722B2 (en) * 2004-09-20 2006-07-18 International Business Machines Corporation NFET and PFET devices and methods of fabricating same
US7204162B2 (en) * 2004-11-23 2007-04-17 Delphi Technologies, Inc. Capacitive strain gauge
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
US7528056B2 (en) * 2007-01-12 2009-05-05 International Business Machines Corporation Low-cost strained SOI substrate for high-performance CMOS technology
US7737498B2 (en) * 2008-05-07 2010-06-15 International Business Machines Corporation Enhanced stress-retention silicon-on-insulator devices and methods of fabricating enhanced stress retention silicon-on-insulator devices
US8084822B2 (en) * 2009-09-30 2011-12-27 International Business Machines Corporation Enhanced stress-retention fin-FET devices and methods of fabricating enhanced stress retention fin-FET devices
US8361867B2 (en) * 2010-03-19 2013-01-29 Acorn Technologies, Inc. Biaxial strained field effect transistor devices
US9059201B2 (en) 2010-04-28 2015-06-16 Acorn Technologies, Inc. Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation
US8361868B2 (en) 2010-04-28 2013-01-29 Acorn Technologies, Inc. Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation
US9406798B2 (en) 2010-08-27 2016-08-02 Acorn Technologies, Inc. Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
US10833194B2 (en) 2010-08-27 2020-11-10 Acorn Semi, Llc SOI wafers and devices with buried stressor
US8395213B2 (en) 2010-08-27 2013-03-12 Acorn Technologies, Inc. Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
US8536032B2 (en) 2011-06-08 2013-09-17 International Business Machines Corporation Formation of embedded stressor through ion implantation
US8981523B2 (en) 2012-03-14 2015-03-17 International Business Machines Corporation Programmable fuse structure and methods of forming
US9362400B1 (en) 2015-03-06 2016-06-07 International Business Machines Corporation Semiconductor device including dielectrically isolated finFETs and buried stressor
US9524969B1 (en) 2015-07-29 2016-12-20 International Business Machines Corporation Integrated circuit having strained fins on bulk substrate
CN113035716B (zh) * 2021-02-08 2022-07-22 西安电子科技大学 基于22nm工艺的SONOS结构抗辐照FDSOI场效应管及其制备方法
WO2023049172A1 (en) 2021-09-22 2023-03-30 Acorn Semi, Llc MULTI-FINGER RF nFET HAVING BURIED STRESSOR LAYER AND ISOLATION TRENCHES BETWEEN GATES

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5362667A (en) 1992-07-28 1994-11-08 Harris Corporation Bonded wafer processing
CA2062134C (en) * 1991-05-31 1997-03-25 Ibm Heteroepitaxial layers with low defect density and arbitrary network parameter
US5146298A (en) * 1991-08-16 1992-09-08 Eklund Klas H Device which functions as a lateral double-diffused insulated gate field effect transistor or as a bipolar transistor
US5461243A (en) * 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
JP3427114B2 (ja) 1994-06-03 2003-07-14 コマツ電子金属株式会社 半導体デバイス製造方法
US6043166A (en) 1996-12-03 2000-03-28 International Business Machines Corporation Silicon-on-insulator substrates using low dose implantation
JP3645390B2 (ja) * 1997-01-17 2005-05-11 株式会社東芝 半導体装置およびその製造方法
US5897362A (en) 1998-04-17 1999-04-27 Lucent Technologies Inc. Bonding silicon wafers
JP4476390B2 (ja) 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR100532367B1 (ko) 1998-09-16 2006-01-27 페어차일드코리아반도체 주식회사 보호 다이오드를 내재한 수평형 확산 모스 트랜지스터 및 그 제조방법
US6174820B1 (en) 1999-02-16 2001-01-16 Sandia Corporation Use of silicon oxynitride as a sacrificial material for microelectromechanical devices
US20020089032A1 (en) * 1999-08-23 2002-07-11 Feng-Yi Huang Processing method for forming dislocation-free silicon-on-insulator substrate prepared by implantation of oxygen
US6339232B1 (en) 1999-09-20 2002-01-15 Kabushika Kaisha Toshiba Semiconductor device
US6319775B1 (en) * 1999-10-25 2001-11-20 Advanced Micro Devices, Inc. Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device
JP3607194B2 (ja) * 1999-11-26 2005-01-05 株式会社東芝 半導体装置、半導体装置の製造方法、及び半導体基板
JP4406995B2 (ja) * 2000-03-27 2010-02-03 パナソニック株式会社 半導体基板および半導体基板の製造方法
JP2001338988A (ja) * 2000-05-25 2001-12-07 Hitachi Ltd 半導体装置及びその製造方法
US6890835B1 (en) * 2000-10-19 2005-05-10 International Business Machines Corporation Layer transfer of low defect SiGe using an etch-back process
JP2002164520A (ja) * 2000-11-27 2002-06-07 Shin Etsu Handotai Co Ltd 半導体ウェーハの製造方法
US6723661B2 (en) * 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
JP3995428B2 (ja) * 2001-03-29 2007-10-24 株式会社東芝 半導体基板の製造方法及び半導体装置の製造方法
US6603156B2 (en) * 2001-03-31 2003-08-05 International Business Machines Corporation Strained silicon on insulator structures
WO2003015138A2 (en) * 2001-08-09 2003-02-20 Amberwave Systems Corporation Optimized buried-channel fets based on sige heterostructures
DE10231964A1 (de) * 2002-07-15 2004-02-19 Infineon Technologies Ag Halbleiterbauelement mit stressaufnehmender Halbleiterschicht sowie zugehöriges Herstellungsverfahren

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WO2004040619A2 (en) 2004-05-13
CN1320628C (zh) 2007-06-06
AU2003299550A1 (en) 2004-05-25
AU2003299550A8 (en) 2004-05-25
KR20050062628A (ko) 2005-06-23
CN1706038A (zh) 2005-12-07
KR101018835B1 (ko) 2011-03-04
EP1552554A2 (en) 2005-07-13

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