TW492084B - Manufacturing method of the semiconductor device having self-aligned metal source/drain - Google Patents

Abstract

The present invention provides a manufacturing method of the semiconductor device having self-aligned metal source/drain, which comprises the following steps: forming an insulation layer and a semiconductor layer on the semiconductor substrate; forming a shallow trench isolation layer to isolate an active layer on the predetermined position of the semiconductor layer, wherein the shallow trench isolation layer and the insulation layer form a continuous insulation layer; forming a gate structure on the semiconductor layer; forming a gate insulation sidewall layer on both sides of the gate structure; use the gate insulation sidewall layer for use as the mask to etch back the semiconductor layer till reaching the buried insulation layer to form a source/drain opening; forming a metal source/drain on the source/drain opening.

Description

V. Description of the invention (1) This month, "τ" is about a semiconducting element called "A rare I ancient A", a method of making materials, and it is about the peg with self-aligned metal source / dip handle. You ... It uses self-aligned metal source / drain; the design and electrode of the component to reduce the activation temperature and reduce the parasitic resistance of the pass-through doped source / traditional silicon doped source / drain, since 1 Resistance, so that when the characteristic size of the integrated circuit element is two / battery ::: Drain electric power, Shi Xi doped source / drain needs to be very high V active resistance, 随 at 90 0- 1 1 00 t, so As for the "degree of guanidine", generally high-K gate-mediated lightning; Jinchengbucha #, low-temperature metal gate and body circuit component size process bottlenecks. ~ Missing 2 has become a reduction product. At present, silicon (Si I icon on 彳 nsnlqtnr Qnr Λ ^ ^, 、, useful for elephant limbs) in the field of integrated circuit process technology is being widely used. The application of μ 1 a to a semiconductor material on an insulating layer forms an electric solar limb. This technology is increasingly important in the field of integrated circuit development. The integrated circuit components are fabricated on the second and second layers. Compared with the thicker 1C components, the same 1C components can get lower parasitic capacitance and larger Dantong force, so the flow rate is faster. fast. Furthermore, field-effect transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), located on the stone layer of the SOI structure have more advantages than MOSFETs fabricated on a 5-system silicon substrate, including the effect of short pass chirp. Resistance, steeper subthreshold slope, current drive, higher package density, reduced parasitic capacitance, J-step process steps, etc. In addition, recent advances in silicon layer quality, buried material quality, and yield have made it possible to manufacture very large integrated circuit components below 0 · 丨 micron. As the so J structure effectively reduces parasitics

Page 4 492084 V. Description of the invention (2), and at the same time increase the tolerance of collapse of the structural butt joint, so the SOI technology is suitable for integrated circuits with south efficiency and south density. Figure 1 shows the structure of a semiconductor device with a metal source / drain published by Hitachi Ltd. D i g h H i s a m o t 〇 et al. Published in Symposium on VLSI Technology Digest of Technical Pagers ^ p. 208-209, 20 00 "a Compact FD-SOI MOSFETs Farication Process Featuring SixGei'x Gate and

Damascene-Dummy SAC ", the final structure please refer to Figure 丨, buried oxide layer 10, semiconductor layer (silicon layer on the insulator, S〇) 2, shallow trench

Isolation layer 14, gate structure 16, gate insulation sidewall layer 丨 8, first insulation layer 20, second insulation layer 2, 2, polycrystalline silicon layer 24, and tungsten contact plug 26, among which polycrystalline The silicon layer 24 and the tungsten contact plug 26 serve as both a source / drain and a contact plug. It can be seen from the figure that the contact plug of this structure has the same size as the source / drain, that is, the contact plug is too large in size, and the stomach produces high coupling capacitance. To solve the above problem, The self-aligned metal source / drain of the metal source / drain takes temperature and reduces parasitic resistance. It is an object of the present invention to provide a method for manufacturing a semiconductor device. It uses a conventional silicon doped source / drain to reduce the activity. Therefore, the present invention provides a method for manufacturing a semiconductor device, which includes forming a buried insulating layer and a semiconductor trench forming a shallow trench isolation layer to isolate a self-aligned layer. The following steps of the metalloid source / drain: layer on the semiconductor substrate; the active region is located in this semiconductor layer, and the shallow trench is isolated

V. Description of the invention (3) The layer forms the gate structure of this buried insulating layer-the gate structure; the insulating layer here; the upper layer of the semiconductor layer; the side wall of the gate is insulated by this gate: 3 sides form the gate The buried insulating layer is formed on the electrode insulation side to form a source / and the semiconductor layer is etched back to the mask to form a metal source / drain. Opening; and opening at the source / drain region To make the present invention better, the following exemplifies preferred embodiments, and features and advantages can be more clearly understood. Sub-theta θ, the detailed description of the diagram, the diagram is briefly explained. The first diagram is a display of the dry mouth & once there is a semi-conductor element published by Hitachi Ud. Sectional view of the structure. ^ t-2E is a cross-sectional view showing a manufacturing process of a semiconductor device with a self-aligned full source / drain in accordance with an embodiment of the present invention.说明 Description of Fengfeng metal symbols 6 2 ~ Buried insulating layer; 6 6 ~ Shallow trench isolation layer 6 7 ~ Gate dielectric layer; 6 9 ~ Gate shielding layer; 7 4 ~ Source / and electrode area opening 78 ~ Metal Source / drain; 8 2 ~ tungsten layer. 60 ~ substrate; 64 ~ semiconductor layer; G ~ gate structure; 6 8 ~ gate electrode 7 2 ~ extended source / drain; 7 6 ~ gate insulating sidewall layer 8 0 ~ titanium nitride layer; embodiment of the present invention A method of manufacturing a component is provided. One type has a self-aligning metal source / drain which uses a self-aligning metal source / drain to replace the pass:

492084

Silicon doped source / drain to reduce activation temperature and reduce parasitic resistance. Please refer to FIG. 2A, a buried insulating layer 62 and a semiconductor layer 64 are formed on a semiconductor substrate 60. In this embodiment, a wafer with a stone evening (S0I) on an insulator is used as an example. As a starting material, implanted oxygen (SIM0X) or Smart Cut® technology can be used for isolation, but it is not limited to this. The semiconductor layer (SOI layer) 64 is generally a silicon material having a thickness of less than about 1,000 A. The buried insulating layer 6 2 is generally composed of silicon oxide. Next, a shallow trench isolation layer 66 is formed on the conductor layer 64 to isolate an active region. The trench isolation layer and the buried insulating layer form a continuous insulating layer. A gate junction is then formed on the semiconductor layer 64 as shown in FIG. 2B. The gate structure G is composed of a gate dielectric layer 67, a gate electrode 68, and a gate shielding layer 69. Among them, the gate dielectric layer 67 may be composed of silicon nitride 'silicon oxynitride' or a high-k dielectric material, the gate electrode 68 may be a polycrystalline silicon layer or a metal layer, and the gate shielding layer 6 9 It can be a silicon nitride layer or a silicon dioxide layer, but it is not limited thereto. e. Second, as shown in FIG. 2C, source and drain extensions 74 are formed on the semiconductor layer 64. The extended source / drain / can be completed by ion implantation (Extension). After that, a gate insulating sidewall layer 72 is formed on both sides of the gate structure G, and the gate insulating sidewall layer 72 can be a silicon oxide layer. Or a silicon nitride layer. Then, as shown in FIG. 2D, the gate insulating sidewall layer 72 is used as a mask to etch the semiconductor layer 64 to the buried insulating layer 62 to form a source / drain opening and etch back the semiconductor layer. The process of 64 is made using, for example, anisotropic dry etching or reactive ion etching (Reactive ion etching (RIE)). 5. Description of the Invention (5) process, but it is not limited thereto. As shown in FIG. 2E, a metal: and / or a pole 78 are formed in the source / drain region opening 76. The metal source / drain 78 can be composed of a titanium nitride layer 80 and a tungsten layer 82, and nitrided. The titanium layer 80 can be formed by low-pressure chemical vapor deposition or plasma-assisted chemical 2 deposition. The tungsten layer 82 can be formed by chemical vapor deposition or physical vapor deposition, but is not limited thereto. After the above embodiments, the conventional method of forming a metal contact plug can be implemented: an insulating layer, a contact window opening, and a formation. The electrical layer is equal to the step of forming a metal contact plug. The embodiment of switching the invention uses a self-aligned metal source / drain to replace the traditional electrode. The required activation temperature is at 7 .... 900_110 (rc, source / drain), and the second source resistance of metal source is lower than traditional silicon doped source / drain 5 due to the extremely large integrated circuit element k for the extended source of 0 · 1 / Dip pole makes 亓 DU M @ / k • Bei Yuan also maintains the characteristics of the server for 4 years and can work with the subsequent formation of metal 彡 6 Ding. There is no fHit h program from Hitachi. The traditional method can be used to form the contact plug in one piece. Er Er Ltd. == master < structure and still have a strong female + k I?-Large t The present invention has been disclosed as above with a preferred embodiment, The lack of pots is not limited to the present invention. Any ..., its sub-African uses and scope, can be used as: ^ t, 'without departing from the spirit and scope of the present invention; Therefore, the protection of Jiaming profit-seeking target range of the present invention shall prevail.

0503-5957TWF-ptd

Claims (1)

492084 VI. Application Patent Scope 1 · A method for manufacturing a semiconductor device with self-aligned metal source / drain, including the following steps: forming a buried insulating layer and a semiconductor layer on a semiconductor substrate; at a predetermined position of the semiconductor layer Forming a shallow trench isolation layer to isolate an active area, the shallow trench isolation layer and the buried insulating layer forming a continuous insulating layer; forming a gate structure on the semiconductor layer; on both sides of the gate structure A gate insulating sidewall layer is formed on the sidewall; the semiconductor insulating layer is etched back to the buried insulating layer using the gate insulating sidewall layer as a mask to form a source / drain opening; and a metal source / drain is formed in the source / drain region opening pole. 2. The method according to item 1 of the patent application scope, further comprising forming an extended source /; and an electrode on the semiconductor layer by ion implantation after forming the gate structure. 3. The method according to item 1 of the scope of patent application, wherein the gate structure is composed of a gate dielectric layer, a polycrystalline silicon layer, and a silicon nitride shielding layer. 4. The method according to item 1 of the scope of patent application, wherein the gate insulating sidewall layer is an oxide second layer or a nitrided layer. 5. The method according to item 1 of the scope of patent application, wherein the semiconductor layer is etched back using an anisotropic dry etching process. 6. The method according to item 1 of the scope of patent application, wherein the metal source / electrode is composed of a titanium nitride layer and a tungsten layer. 7. A method of manufacturing a semiconductor device with a self-aligned metal source / drain, including the following steps: 0503-5957TWF-ptd Page 9 492084 6. The scope of the patent application forms a buried insulating layer and a semiconductor layer on a semiconductor substrate; a shallow trench isolation layer is formed at a predetermined position of the semiconductor layer to isolate a first active region. The shallow trench isolation layer and the buried insulating layer form a continuous insulating layer; a gate structure is formed on the semiconductor layer; and an extended source / drain is formed on the semiconductor layer. Forming a gate insulating sidewall layer on both side walls of the gate structure; using the gate insulating sidewall layer as a mask to etch back the semiconductor layer to the buried insulating layer to form a source / drain opening; and at the source / drain The region opening forms a metal source / drain. 8. The method according to item 7 of the scope of patent application, wherein forming the extended source / drain is performed by ion implantation. ‘9. The method as described in item 7 of the scope of patent application, wherein the gate structure is composed of a gate dielectric layer, a polycrystalline silicon layer, and a silicon nitride shielding layer. 10. The method according to item 7 of the scope of patent application, wherein the gate insulating sidewall layer is a silicon oxide layer or a silicon nitride layer. Π. The method according to item 7 of the scope of patent application, wherein the semiconductor layer is etched back using an anisotropic dry etching process or a reactive ion etching process. 1 2. The method according to item 7 of the scope of patent application, wherein the metal source / drain is composed of a titanium nitride layer and a tungsten layer. 0503-5957TW? -Ptd Page 10