CN1438711A - 具有超薄的应变矽通道的金氧半导体场效晶体管及其制作方法 - Google Patents
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Abstract
本发明提供一种利用超薄的应变矽层作为通道层的金氧半导体场效晶体管，且可结合SOI技术可将超薄的应变矽层制作于绝缘层上。金氧半导体场效晶体管包括有：矽基材；绝缘层，形成于矽基材的表面上；矽层，形成于绝缘层表面上，且具有伸张应变的晶格特性，用作通道层；闸极绝缘层，形成于矽层的表面上；闸极层，限定形成于闸极绝缘层的表面上；以及源/汲极区，形成于闸极层两侧的矽层内。
Description
技术领域
本发明涉及一种金氧半导体场效晶体管(以下简称MOSFET)及其制造工艺，特别涉及一种具有超薄的应变矽通道(strained-silicon channel)的MOSFET及其结合SOI技术的制作方法。
背景技术
在现今MOSFET制程中，为了提高组件的积集度并增加驱动能力，必须尽量将闸极的线宽设计缩短，但是当晶体管的信道长度缩短至某一定程度之后便会衍生出短信道效应(short channel effect)。为了有效抑制短信道效应，第一种解决的方法是增加矽基板的掺杂浓度，但是会导致接面漏电流增加、通道的载子迁移率降低以及寄生电容等问题。第二种方法是浅化源/汲极区的掺杂轮廓以使接面深度变浅，但是仍会遭遇到漏电流、寄生电阻以及制程热预算等限制。第三种方法是降低闸极氧化层的厚度，不但可改善短信道效应还可增加驱动能力，不过却易直接穿遂闸极而导致漏电流增加，而且闸极氧化层的可靠度不易控制。有鉴于此，目前MOSFET制程采用一种具有伸张应变(tensile-strained)的晶格特性的矽层作为电晶体的信道，可有效增加电子在信道层的迁移率，以解决上述的问题。
美国专利第6,310,367号揭露一种以应变Si层作为信道的MOSFET。如图1所示的矽基底10上包含有：具有松弛(relaxed)晶格特性的SiGe层12夹设于源/汲极区11之间，具有伸张应变特性的Si层13形成于SiGe层12的表面上，SiO2层14形成于源/汲极区11表面上并于Si层13上方构成一沟槽，Ta2O5层15覆盖于沟槽的底部与侧壁上，TiN层16形成于Ta2O5层15的表面上，以及铝金属层17填满沟槽。其中，铝金属层17与TiN层16是作为闸极层，Ta2O5层15是用作闸极绝缘层，Si层13是用作通道层，而SiGe层12是用作缓冲层。如此一来，具有伸张应变特性的Si层13可提高通道层的电子迁移率，以使MOSFET的操作速度加快。不过，为了能够在SiGe层12上制作出具有伸张应变特性的Si层13，SiGe层12的缓冲厚度必须大于2微米，以使晶格达到完全松弛的状态。然而在矽基底10上制作如此厚的SiGe层12，会使源/汲极区11之间的寄生电容增加，进而影响到MOSFET的操作速度。
美国专利第6,326,667号专利揭露一种将应变Si层制作在绝缘层上的MOSFET。如图2所示，矽基底20上依序堆叠形成有SiO2绝缘层22、具有晶格松弛特性的SiGe层24、具有晶格应变特性的Si层26、闸极绝缘层27以及闸极层28。此外，源/汲极区29形成于闸极层28两侧的Si层26内。此种技术可以结合应变Si信道以及SOI的优点，以降低短通道效应、基材漏电流以及源/汲极区的寄生电容等问题。
请参阅图3A至图3D，其显示习知利用SOI(磊晶矽绝缘层上，silicon-on-insulator)技术制作Si层与SiGe层的剖面示意图。首先，如图3A所示，于矽基材30上长成应变SiGe层31，且随着应变SiGe层31的厚度增加至一定程度，其表面会形成一松弛SiGe层32，然后藉由氢离子布植制程33可于应变SiGe层31与松弛SiGe层32之间形成一切割线。接着，如图3B所示，提供晶圆34，其表面上包含有SiO2层36，再利用晶圆接合技术将晶圆34与矽基材30接合，以使SiO2层36与松弛SiGe层32的界面黏合。跟着，如图3C所示，利用热处理方式将切割线处劈裂，使松弛SiGe层32自矽基材30分离而形成于晶圆34上，以构成SGOI(SiGe-on-insulator)基底35，其厚度约200-300nm。最后，如图3D所示，利用化学机械研磨(chemical mechanical olishing，CMP)方法将松弛SiGe层32的表面平坦化处理的后，可于表面上长成应变Si层38。
发明内容
本发明则提出一种利用应变矽层作为通道层的MOSFET，且结合SOI技术可将超薄的应变矽层制作于绝缘层上。
本发明的MOSFET包括有：矽基材；绝缘层，其形成于矽基材的表面上；矽层，其形成于绝缘层表面上，且具有伸张应变的晶格特性，用作通道层；闸极绝缘层，形成于矽层的表面上；闸极层，界定形成于闸极绝缘层的表面上；以及源/汲极区，形成于闸极层两侧的矽层内。
本发明还提供了这种晶体管的制作工艺，包括下列步骤：
提供矽基材，其表面上包含有SiGe层，且该SiGe层具有松弛的晶格特性；
于该SiGe层上形成Si层，且该Si层具有伸张应变的晶格特性；
提供晶圆，其表面上包含有绝缘层；
利用晶圆接合技术，将该晶圆的绝缘层与该矽基材的Si层接合；
将该Si层自该SiGe层上切离，以使该Si层形成于该晶圆的绝缘层表面上。
附图说明
图1显示习知以应变Si层作为通道的MOSFET的剖面示意图。
图2显示习知将应变Si层制作在绝缘层上的MOSFET的剖面示意图。
图3A至图3D显示利用SOI技术制作Si层与SiGe层的剖面示意图。
图4显示本发明实施例1的MOSFET的剖面示意图。
图5A至图5C显示本发明利用SOI技术制作应变Si层的剖面示意图。
图6显示本发明实施例2的MOSFET的剖面示意图。
图中组件的标号说明：习知技术(图1-图3D)矽基底-10； SiGe层-12；源/汲极区-11； Si层-13；SiO2层-14； Ta2O5层-15；TiN层-16； 铝金属层-17；矽基底-20； SiO2绝缘层-22；SiGe层-24； Si层-26；闸极绝缘层-27； 闸极层-28；源/汲极区-29； 矽基材-30；应变SiGe层-31； 松弛SiGe层-32；氢离子布植制程-33； 晶圆-34；SiO2层-36； SGOI基底-35；应变Si层-38。本发明技术(图4-图6)矽基底-40； 绝缘层-42；应变Si层-44； 闸极绝缘层-46；闸极层-48； 侧壁子结构-49；源/汲极区-47； 矽基材-50；应变SiGe层-52； 松弛SiGe层-54；应变Si层-56； 晶圆-60；绝缘层-62； 上升式源/汲极结构-45。
具体实施方式
本发明提出一种利用应变Si层作为通道层的MOSFET，且结合SOI技术可将厚度小于20nm的应变Si层制作于绝缘层上，以提供作一般MOSFET的制程使用。
以下结合具体实施例详细介绍本发明的实施过程及所具有的有益效果，但不构成对本发明实施范围的限定。
实施例1
请参阅图4，其显示本发明实施例1的MOSFET的剖面示意图。矽基底40上包含有：绝缘层42，应变Si层44形成于绝缘层42上，闸极绝缘层46形成于应变Si层44上，闸极层48限定形成于闸极绝缘层46上，侧壁子结构49形成闸极层48的两侧壁上，以及源/汲极区47形成于闸极层48两侧的应变Si层44内。其中，绝缘层42是由SiO2、SI3N4或其它绝缘材质所构成，而应变Si层44具有伸张应变的晶格特性，且厚度小于20nm。相较于整体Si层于室温下的电子迁移率为400cm2/Vs，由于应变Si层44具有伸张应变的晶格特性，可提高电子与电动的迁移率，验证得知其于室温下的电子迁移率可达3000cm2/Vs，可有效改善短通道效应的问题，并使MOSFET的操作速度加快。因此在本发明的MOSFET中，不必藉由对通道层进行重掺杂制程来解决短通道效应，可避免产生原本担心的杂质散射、无规则分布的掺质所导致的起始电压起伏等问题。
请参阅图5A至图5C，其显示利用SOI技术制作应变Si层的剖面示意图。首先，如图5A所示，于矽基材50上长成应变SiGe层52，且随着应变SiGe层52的厚度增加至一定程度，其表面会形成一松弛SiGe层54。然后，于松弛SiGe层54的表面上形成应变Si层56，其厚度小于20nm。接下来，如图5B所示，提供晶圆60，其表面上包含有绝缘层62，再利用晶圆接合技术将晶圆60与矽基材50接合，以使绝缘层62与应变Si层56的界面黏合。跟着，如图5C所示，利用热处理或其它切离处理方式，将应变Si层56自松弛SiGe层54表面上分离而形成于晶圆60的绝缘层62上。最后，可利用CMP方法将应变Si层56的表面平坦化。
实施例2
实施例1的源/汲极区47是形成于超薄的应变Si层44中，为避免超薄的源/汲极区47导致高电阻而降低驱动电流，实施例2提供一种具有上升式源/汲极结构的MOSFET。请参阅图6，其显示本发明实施例2的MOSFET的剖面示意图。于制作完成闸极层48与侧壁子结构49之后，可在源/汲极区47上方分别制作上升式源/汲极结构45。一种制作方法是利用沉积多晶矽层与回蚀刻多晶矽层的步骤，仅使多晶矽层残留在源/汲极区47上方，以用作为上升式源/汲极结构45。另一种方法是以选择性的磊晶成长方式，仅在源/汲极区47上方成长磊晶层，以用作为上升式源/汲极结构45。
以上实施方案仅用以更加清楚地解释本发明，对本发明的实施范围不构成任何限定。任何熟习此技艺者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当以权利要求书为准。
Claims (10)
1、一种金氧半导体场效晶体管，包括有：
矽基材；
绝缘层，形成于该矽基材的表面上；
矽层，形成于该绝缘层表面上，且具有伸张应变的晶格特性，用作通道层；
闸极绝缘层，形成于该矽层的表面上；
闸极层，限定形成于该闸极绝缘层的表面上；以及
源/汲极区，形成于该闸极层两侧的矽层内。
2、如权利要求1所述的金氧半导体场效晶体管，其中所述矽层的厚度小于20nm。
3、如权利要求1所述的金氧半导体场效晶体管，其中所述绝缘层是由SiO2、Si3N4或其它绝缘材质所构成。
4、如权利要求1所述的金氧半导体场效晶体管，另包含有上升式的源/汲极结构，分别形成于该源/汲极区的上方。
5、一种金氧半导体场效晶体管制程，包括下列步骤：
提供矽基材，其表面上包含有SiGe层，且该SiGe层具有松弛的晶格特性；
于该SiGe层上形成Si层，且该Si层具有伸张应变的晶格特性；
提供晶圆，其表面上包含有绝缘层；
利用晶圆接合技术，将该晶圆的绝缘层与该矽基材的Si层接合；
将该Si层自该SiGe层上切离，以使该Si层形成于该晶圆的绝缘层表面上。
6、如权利要求5所述的金氧半导体场效晶体管制程，其中该Si层的厚度小于20nm。
7、如权利要求5所述的金氧半导体场效晶体管制程，另包括下列步骤：
于该Si层的表面上形成闸极绝缘层；
于该闸极绝缘层上限定形成闸极层；以及
于该闸极层两侧的Si层内形成源/汲极区。
8、如权利要求7所述的金氧半导体场效晶体管制程，另包括步骤：于形成该源/汲极区之后，于该源/汲极区上方形成上升式的源/汲结构。
9、如权利要求8所述的金氧半导体场效晶体管制程，其中该上升式的源/汲结构的制作方法包括下列步骤：
沉积一多晶矽层；以及
回蚀刻该多晶矽层，以使该多晶矽层残留在该源/汲极区上方。
10、如权利要求8所述的金氧半导体场效晶体管制程，其中所述上升式的源/汲结构的制作方法是以选择性的磊晶成长方式，在该源/汲极区上方成长一磊晶层。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/068,928 | 2002-02-07 | ||
| US10/068,928 US7202139B2 (en) | 2002-02-07 | 2002-02-07 | MOSFET device with a strained channel |
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| Publication Number | Publication Date |
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| CN1438711A true CN1438711A (zh) | 2003-08-27 |
| CN1191639C CN1191639C (zh) | 2005-03-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB031021379A Expired - Lifetime CN1191639C (zh) | 2002-02-07 | 2003-01-31 | 一种金属氧化物半导体场效应晶体管及其制作方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7202139B2 (zh) |
| CN (1) | CN1191639C (zh) |
| TW (1) | TWI226704B (zh) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| FR2874455B1 (fr) * | 2004-08-19 | 2008-02-08 | Soitec Silicon On Insulator | Traitement thermique avant collage de deux plaquettes |
| US6995430B2 (en) | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
| US20030227057A1 (en) * | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
| US6900521B2 (en) * | 2002-06-10 | 2005-05-31 | Micron Technology, Inc. | Vertical transistors and output prediction logic circuits containing same |
| EP1439570A1 (en) * | 2003-01-14 | 2004-07-21 | Interuniversitair Microelektronica Centrum ( Imec) | SiGe strain relaxed buffer for high mobility devices and a method of fabricating it |
| DE10314989A1 (de) * | 2003-04-02 | 2004-10-14 | Robert Bosch Gmbh | Verfahren zur Herstellung von mikromechanischen Strukturen sowie mikromischanische Struktur |
| US6909186B2 (en) * | 2003-05-01 | 2005-06-21 | International Business Machines Corporation | High performance FET devices and methods therefor |
| US20050070070A1 (en) * | 2003-09-29 | 2005-03-31 | International Business Machines | Method of forming strained silicon on insulator |
| JP2005223109A (ja) * | 2004-02-05 | 2005-08-18 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| US6972461B1 (en) * | 2004-06-30 | 2005-12-06 | International Business Machines Corporation | Channel MOSFET with strained silicon channel on strained SiGe |
| TWI274402B (en) * | 2005-06-17 | 2007-02-21 | Powerchip Semiconductor Corp | Non-volatile memory and fabricating method thereof |
| DE102006019934B4 (de) * | 2006-04-28 | 2009-10-29 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Ausbildung eines Feldeffekttransistors |
| US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
| GB2467935B (en) * | 2009-02-19 | 2013-10-30 | Iqe Silicon Compounds Ltd | Formation of thin layers of GaAs and germanium materials |
| US8796759B2 (en) | 2010-07-15 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin-like field effect transistor (FinFET) device and method of manufacturing same |
| US11348944B2 (en) | 2020-04-17 | 2022-05-31 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor wafer with devices having different top layer thicknesses |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US4142925A (en) * | 1978-04-13 | 1979-03-06 | The United States Of America As Represented By The Secretary Of The Army | Method of making silicon-insulator-polysilicon infrared image device utilizing epitaxial deposition and selective etching |
| US4771016A (en) * | 1987-04-24 | 1988-09-13 | Harris Corporation | Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor |
| US5013681A (en) * | 1989-09-29 | 1991-05-07 | The United States Of America As Represented By The Secretary Of The Navy | Method of producing a thin silicon-on-insulator layer |
| CA2062134C (en) | 1991-05-31 | 1997-03-25 | Ibm | Heteroepitaxial layers with low defect density and arbitrary network parameter |
| US5234535A (en) * | 1992-12-10 | 1993-08-10 | International Business Machines Corporation | Method of producing a thin silicon-on-insulator layer |
| US5344524A (en) * | 1993-06-30 | 1994-09-06 | Honeywell Inc. | SOI substrate fabrication |
| JP3265493B2 (ja) * | 1994-11-24 | 2002-03-11 | ソニー株式会社 | Ｓｏｉ基板の製造方法 |
| SG63832A1 (en) * | 1997-03-26 | 1999-03-30 | Canon Kk | Substrate and production method thereof |
| US5891769A (en) | 1997-04-07 | 1999-04-06 | Motorola, Inc. | Method for forming a semiconductor device having a heteroepitaxial layer |
| US5906951A (en) | 1997-04-30 | 1999-05-25 | International Business Machines Corporation | Strained Si/SiGe layers on insulator |
| US6162705A (en) * | 1997-05-12 | 2000-12-19 | Silicon Genesis Corporation | Controlled cleavage process and resulting device using beta annealing |
| CA2295069A1 (en) | 1997-06-24 | 1998-12-30 | Eugene A. Fitzgerald | Controlling threading dislocation densities in ge on si using graded gesi layers and planarization |
| JP4439020B2 (ja) | 1998-03-26 | 2010-03-24 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
| DE19859429A1 (de) | 1998-12-22 | 2000-06-29 | Daimler Chrysler Ag | Verfahren zur Herstellung epitaktischer Silizium-Germaniumschichten |
| TW447018B (en) | 1999-12-13 | 2001-07-21 | United Microelectronics Corp | Method for manufacturing raised source/drain |
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2002
- 2002-02-07 US US10/068,928 patent/US7202139B2/en not_active Expired - Lifetime
-
2003
- 2003-01-16 TW TW092100857A patent/TWI226704B/zh not_active IP Right Cessation
- 2003-01-31 CN CNB031021379A patent/CN1191639C/zh not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| TWI226704B (en) | 2005-01-11 |
| US7202139B2 (en) | 2007-04-10 |
| CN1191639C (zh) | 2005-03-02 |
| US20050003599A1 (en) | 2005-01-06 |
| TW200305284A (en) | 2003-10-16 |
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