CN1592538A - 电路装置 - Google Patents

电路装置 Download PDF

Info

Publication number
CN1592538A
CN1592538A CNA2004100577621A CN200410057762A CN1592538A CN 1592538 A CN1592538 A CN 1592538A CN A2004100577621 A CNA2004100577621 A CN A2004100577621A CN 200410057762 A CN200410057762 A CN 200410057762A CN 1592538 A CN1592538 A CN 1592538A
Authority
CN
China
Prior art keywords
grafting material
circuit arrangement
conductive pattern
metal powder
scolding tin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2004100577621A
Other languages
English (en)
Inventor
成瀬俊道
小暮喜广
长谷川贵之
小林初
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN1592538A publication Critical patent/CN1592538A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3463Solder compositions in relation to features of the printed circuit board or the mounting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01327Intermediate phases, i.e. intermetallics compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/047Soldering with different solders, e.g. two different solders on two sides of the PCB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Die Bonding (AREA)
  • Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)

Abstract

一种提高焊锡等焊料连接可靠性的电路装置。本发明的电路装置(10A)具有:导电图形(11)、使电路元件(12)固定结合在导电图形(11)上的接合材料(14)、覆盖电路元件(12)的密封树脂(18)。并且作为接合材料(14)使用含有Bi的游离铅焊锡。与一般的焊锡相比由于Bi的熔化温度高,在安装电路装置(10A)时可抑制接合材料(14)的熔化。并且为提高接合材料(14)的润湿性也可以在接合材料(14)中混入Ag等。

Description

电路装置
技术领域
本发明涉及一种电路装置,特别涉及在电路装置内部使用焊锡等接合材料把电路元件进行固定结合的电路装置。
背景技术
一般的电路装置中为固定结合内设的元件而多使用焊锡。并且作为使电路元件自身固定结合的外部电极也多使用焊锡。参照图11说明采用接合材料110的电路装置100的一例。
作为电路元件半导体元件102A和片状元件102B内设在电路装置100内。半导体元件102A面朝上固定结合在支承衬底101上,并通过金属细线103与表面电极104电连接。片状元件102B通过由焊锡形成的接合材料110固定结合在表面电极104上。并且电路元件102由密封树脂107覆盖。
在支承衬底101的表面形成的表面电极104与在支承衬底101的背面形成的背面电极105贯通支承衬底101而连接。电路装置100通过固定结合在背面电极105上的外部电极111而固定结合在形成于安装衬底106表面上的导电路108上。
近年来游离Pb(铅)焊锡的实用化在急速进展(参照专利文献1和专利文献2)。特别是露出在外部的外部电极111,多使用游离铅焊锡。
专利文献1:特开2002-76605号公报
专利文献2:特开2002-261104号公报
发明内容
在熔化外部电极111安装电路装置100的反射流焊接工序中接合材料110有时熔化。若接合材料110熔化则其体积膨胀10%左右,所以在密封整体的密封树脂107上产生裂纹。另外,由熔化的接合材料侵入结构要素相互之间的界面和该裂纹会引起短路。特别是片状元件102B其两端的电极通过接合材料110固定结合的。因此存在熔化的接合材料110沿片状元件102B的下部侵入引起短路的问题。另外有时熔化的接合材料110还沿片状元件102B的上部侵入。
因为外部电极111若采用游离Pb焊锡时则反射流焊接工序时的温度高,所以上述问题明显发生。其原因是与一般的Sn-Pb共晶焊锡相比一般游离Pb焊锡的熔点高。例如具有代表性游离铅焊锡之一的Sn-3.0Ag-0.5Cu系列的焊锡的熔点是217℃左右。因此把这种游离Pb焊锡作为外部电极111采用时,则反射流焊接工序时的环境温度是250℃左右。电路装置100暴露在这种高温的环境中,则电路装置100内部的接合材料110熔化。
本发明是鉴于上述问题点而开发的,本发明的主要目的在于提供一种提高接合材料连接可靠性的电路装置。
另外,本发明的电路装置具备:电路元件、导电图形、用于接合所述电路元件与所述导电图形的接合材料,所述接合材料含有Bi。
另外,本发明中所述电路元件、所述导电图形和所述接合材料由密封树脂覆盖。
另外,本发明具备固定结合在所述导电图形上的外部电极,所述外部电极由游离铅焊锡构成。
另外,本发明中所述接合材料含有Bi、Ag和Cu。
另外,本发明中所述导电图形具有通过由树脂构成的绝缘层层积的多层配线结构,所述接合材料熔化的温度比所述外部电极熔化的温度高,且比所述绝缘层热解的温度低。
另外,本发明的电路装置具备:电路元件、导电图形、用于接合所述电路元件与所述导电图形的接合材料,在所述接合材料中混入金属粉。
另外,本发明中所述金属粉熔化的温度比所述接合材料熔化的温度高。
另外,本发明中所述金属粉采用与形成所述接合材料的金属生成金属间化合物的金属。
另外,本发明中所述金属粉采用Cu、Ni、Fe、Al、Ag、Au、Sb或Bi。
另外,本发明中所述金属粉是由不同大小的粒子所构成。
另外,本发明中所述电路元件是两端形成有电极层的片型元件,所述电极层与所述导电图形通过所述接合材料连接,所述电极层的至少一部分与所述接合材料成为一体。
根据本发明,作为在电路装置内部进行电路元件的固定结合的接合材料使用含有Bi的游离铅焊锡。因此外部电极的材料即使在采用了熔化温度高的游离铅焊锡时,在进行电路装置的安装的反射流焊接工序中也能抑制接合材料的熔化。这是因为Bi的熔化温度是270度左右高温。由此能防止由装置内部接合材料熔化导致的裂纹发生和短路。
另外根据本发明,通过在电路装置内部进行电路元件的固定结合的接合材料中混入金属粉,能抑制熔化的接合材料流出。这是因为在接合材料熔化时大部分的焊锡成分与金属粉生成了金属间化合物。
在熔化外部电极的反射流焊接工序中,即使在接合材料熔化时熔化的也仅是形成接合材料的焊锡成分。在接合材料中含有的金属粉不熔化仍以固体存在。因为由于仅是在接合材料中含有的焊锡熔化,接合材料熔化后的膨胀量降低,所以抑制树脂裂纹的发生。
附图说明
图1(A)~图1(C)是表示本发明电路装置的剖面图;
图2(A)~图2(C)是表示本发明电路装置的剖面图;
图3(A)是表示本发明电路装置的立体图,图3(B)~图3(C)是表示本发明电路装置的剖面图;
图4(A)~图4(B)是表示在本发明电路装置中使用的接合材料构成的模式图;
图5(A)~图5(D)是表示本发明电路装置的剖面图;
图6(A)~图6(C)是表示本发明电路装置制造方法的剖面图;
图7(A)~图7(C)是表示本发明电路装置制造方法的剖面图;
图8是表示本发明电路装置制造方法的剖面图;
图9(A)~图9(C)是表示本发明电路装置制造方法的剖面图;
图10(A)~图10(C)是表示本发明电路装置制造方法的剖面图;
图11是表示现有电路装置的剖面图。
具体实施方式
参照图1(A),本实施例的电路装置10A是通过密封树脂18密封半导体元件12A和片状元件12B的结构。片状元件12B通过接合材料14固定结合在导电图形11上。本实施例中作为接合材料14可以采用含有Bi的焊锡。
导电图形11铜等金属构成,露出背面并埋入密封树脂18。并且各导电图形11通过分离槽19实现电分离,在该分离槽19内填充树脂。并且导电图形11的侧面成弯曲状,通过该形状提高导电图形11与密封树脂18的结合。
电路元件12在此采用半导体元件12A和片状元件12B。
作为半导体元件12A采用LSI芯片、裸露的晶体管芯片、二极管等。半导体元件12A通过接合材料14使其背面固定结合在导电图形11上。半导体元件12A的表面电极与导电图形11通过金属细线15电连接。并且半导体元件12A的背面绝缘时也可以使用绝缘性结合剂代替接合材料14来固定结合半导体元件12A。
片状元件12B是采用片状电阻和片状电容等。片状元件12B两端的电极通过接合材料14固定结合在导电图形11上。另外片状元件12B采用电感、热敏电阻、天线、振荡器等两端具有电极部的元件。
接合材料14是焊锡等焊料,其具有把电路元件12固定结合在导电图形11上的作用。本实施例中作为接合材料14采用以Bi为主的焊锡。因为Bi是熔化温度非常高的金属,所以能解决伴随接合材料14熔化的各种问题。另外本实施例中接合材料14采用含有金属粉的焊锡。详情后述。
密封树脂18由通过塑料注射成型的热可塑性树脂或通过转移成型的热固化性树脂形成。在此,密封树脂18具有密封整体的作用,同时还具有机械支承整体的作用。
外部电极17由焊锡等焊料构成,形成在导电图形11的背面。一般地,构成外部电极17的焊锡采用熔点比装置内部固定结合电路元件12的接合材料14低。由此,在熔化外部电极17进行电路装置10A安装的反射流焊接工序中能防止接合材料14熔化。并且有时外部电极17使用游离铅焊锡。具体地应用Sn-Ag系列、Sn-Ag-Cu系列、Sn-Cu系列、Sn-Zn系列或在它们中添加了Bi和In的游离铅焊锡。例如,游离铅焊锡之一的Sn-Ag-Cu系列焊锡的熔点是216℃左右。
参照图1(B)说明另一实施例的电路装置10B。该图所示电路装置10B的基本结构与上述电路装置10A相同,不同点在于具有支承衬底21。
支承衬底21采用散热性优良、机械强度好的材料。在此,可采用金属衬底、印刷电路板、挠性衬底、复合衬底等。另外,在采用由金属等导电性材料构成的衬底时要在其表面上设置绝缘层进行与导电图形11的绝缘。
第一导电图形11A和第二导电图形11B形成在支承衬底21的表面和背面上。并且第一导电图形11A和第二导电图形11B贯通支承衬底21电连接。并且在第二导电图形11B上形成外部电极17。第一导电图形11A通过接合材料14与电路元件12连接。在第二导电图形11B的背面形成有由焊锡等焊料构成的外部电极17。
参照图1(C),电路装置10C的导电图形11具有多层的配线结构。具体地,由第一导电图形11A和第二导电图形11B构成的双层导电图形通过由树脂构成的绝缘层22层积。在此,还可以由三层以上的配线结形成。并且第一导电图形11A和第二导电图形11B贯通绝缘层22电连接。
本实施例的要点在于作为在装置内部进行固定结合电路元件的接合材料14使用含有Bi(铋)游离铅焊锡。具体地,作为构成外部电极17的外部电极使用游离铅焊锡时由于游离铅焊锡的熔化温度高,所以进行电路装置10的安装的反射流焊接的温度也在250度以上。因此作为接合材料14使用熔化温度比该反射流焊接温度低的焊锡时,在反射流焊接工序中熔化接合材料14。
本实施例通过作为接合材料14采用含有Bi的游离铅焊锡来解决该问题。Bi的熔点是271.4度,所以即使在以250左右的高温进行反射流焊接时接合材料14也不熔化。根据实验,含90%以上重量比Bi的接合材料14高温进行反射流焊接时也不熔化。并且为提高与导电图形11的材料铜等金属的润湿性,也可以把Ag、Cu或Sn添加到Bi中。例如,89.3Bi-9.2Ag-1.8Cu的游离铅焊锡的熔化温度是258度,作为接合材料14的材料是合适的。并且该组成的游离铅焊锡具有耐腐蚀性和耐氧化性,性能价格比也优良。
另外,以Bi为主的游离铅焊锡比其他金属脆。但在本实施例中密封树脂18把包括接合材料14的整体密封。因此通过该密封树脂18能弥补以Bi为主的游离铅焊锡的脆性。
并且,本实施例所用接合材料14的熔化温度最好比树脂材料变质的温度低。在此所说的树脂材料是指在图1(B)中的支承衬底21或图1(C)中的绝缘层22。例如接合材料14采用熔化温度500度的左右的焊锡时,在熔化接合材料14固定电路元件12结合的反射流焊接工序中绝缘层22产生热解。或者有时绝缘层22炭化。而以Bi为主的本实施例的接合材料14其熔化温度是260℃左右。若是这种程度熔化温度的接合材料14,则以300度左右的温度就能进行反射流焊接,所以能使树脂材料不变质而进行电路元件12的固定结合。
参照图2,说明省略外部电极17而形成的电路装置。在此,省略连接在导电图形11上的外部电极17而形成各电路装置。即图1所示的电路装置是BGA(Ba ll Grid Array)结构,图2所示的这些电路装置呈LGA(Land Grad Array)结构。
具体地,图2(A)中表示其剖面的电路装置10A是从图1(A)所示的电路装置10A省略外部电极17而成。并且,图2(B)所示的电路装置10B是从图1(B)所示的电路装置10B中省略了外部电极17而成。另外,图2(C)所示的电路装置10C是从图1(C)所示的电路装置10C省略外部电极17而成。
另外,具有LGA构造的上述结构的电路装置能通过在安装的安装衬底侧形成的焊锡通过反射流焊接工序安装。
参照图3(A),电路装置10D中使导电图形11形成在电路衬底9的表面上。电路衬底9是金属衬底时在电路衬底9的表面上形成绝缘层8。并且通过接合材料14电路元件12固定结合在导电图形11规定的位置上。在电路衬底9的周边部引线7固定结合在导电图形11上。引线7起到装置整体的外部端子的作用。
参照图3(B),在此,通过密封树脂18密封半导体元件12A和片状元件12B。即使在这种结构中作为固定结合片状元件12B和半导体元件12A的接合材料14,可通过使用以Bi为主材料的焊锡,抑制密封树脂18上裂纹的发生和短路等问题。
参照图3(C),在此,用壳体件6密封在电路衬底9表面上形成的电路。即使在如这样的树脂密封以外形式的密封中也能通过使用以Bi为主的接合材料14来抑制由焊锡流动导致的短路等问题。
参照图4,说明混入金属粉的接合材料14。图4(A)是进行熔化前的膏状接合材料14的模式图,图4(B)是熔化后接合材料14的模式图。
参照图4(A),在此把焊锡粉14B和金属粉14C混入在助熔剂14A内。一般的焊锡膏在助熔剂14A中混入焊锡粉14B。本实施例的接合材料14中是在该焊锡膏中混入金属粉14C。在此,混入到接合材料14中的焊锡粉14B与金属粉14C的重量比在1∶1~3∶2的范围内是合适的。只要是该范围内的重量比在熔化接合材料14时几乎所有的焊锡粉14B都通过生成金属间化合物14D而被消耗。因此能抑制熔化的焊锡成分的流出。上述的重量比随使用的金属粉的粒子直径分布和表面积比的不同而不同。
焊锡粉14B可以采用通常的铅共晶焊锡或游离铅焊锡。作为游离铅焊锡能把Sn-Ag-Cu系列和Sn-Sb系列的焊锡粉14B适用于本实施例。并且还能适用如上述的Bi为主体的焊锡。
助熔剂14A最好是低卤素的或无卤素的。通过采用这种助熔剂能抑制由残留助熔剂导致的图形腐蚀。另外,作为助熔剂14含有热固化性树脂的助熔剂是合适的。由此能把疏松的内部用树脂填充。因此能提高接合材料14自身的机械强度。在此,所说的“疏松”是指在内部形成的空隙。金属粉14C的材料最好是与使用的焊锡粉14B生成金属间化合物的金属。通过形成金属间化合物,焊锡成分与金属粉14C形成一体,所以能抑制熔化的焊锡成分的流出。金属粉14C的具体材料可以采用Cu、Ni、Fe、Al、Ag、Au、Sb或Bi等。并且作为金属粉14C可采用这些金属的混合物或合金。这些金属对焊锡的润湿性也优良。因此即使在使用状况下焊锡成分熔化时,也能通过金属粉14C的润湿性防止焊锡扩展。因此能防止由熔化的焊锡导致的电路装置内部的短路。
金属粉14C的粒子直径是把从1微米以下的超微粒子到数十微米左右大小粒子混合的尺寸是合适的。微粒子成分的金属粉14C其粒子细且比面积大。因此通过把微粒子成分的金属粉14C包含在接合材料14中,提高了防止接合材料14流动的效果。对此,数十微米左右的大粒子的金属粉14C其自身的机械强度大。因此通过把大粒子的金属粉14C包含在接合材料14中能提高接合材料14的强度。
具体地,例如,金属粉14C的粒子大小分布,在由Cu构成的金属粉的情况下,最小粒子直径是0.5μm,最大粒子直径是15μm。并且表示粒子大小分布的曲线中粒子直径5μm是峰值。若采用这种粒子直径分布的金属粉14C,则能起到上述的效果。
图4(B)是表示通过反射流焊接工序进行加热熔化后的接合材料14的结构的模式图。在该反射流焊接工序中焊锡粉14B熔化,但金属粉14C仍然以固体存在。熔化且液化的焊锡成分在金属粉14C的表面生成金属间化合物14E。具体地,粒子直径数微米左右的金属粉其大部分成为金属间化合物。在金属粉的表层附近生成具有Cu6Sn5组成的金属间化合物。并且在金属粉的内部生成具有Cu3Sn组成的金属间化合物。在上述重量比(焊锡粉∶金属粉=1∶1~3∶2)的情况下,熔化的焊锡粉14C的大部分成为金属间化合物14E。因此以焊锡14D状态存在的很少,所以防止熔化焊锡成分流出。
另外,接合材料14由于含有导电性优良且电阻小的金属粉14C,所以其热的传导率高,电阻也低。另外,由于与导电图形和电路元件的连接界面维持金属接合,所以能进一步降低接合材料14的电阻。
另外,有时在进行熔化的接合材料14上残留少量的助熔剂14A。本实施例中也可以使用含有热固化性树脂的助熔剂14A。这时可通过残留助熔剂14A增强接合材料14的机械强度。
下面参照图5说明使用混入金属粉的接合材料14来安装片状元件12B的方法。
首先,参照图5(A),在导电图形11的表面上涂敷接合材料14。在此涂敷的是如图4(A)所示的膏状的接合材料14。混入金属粉的接合材料14由于粘度高,所以在隆起的状态形成在导电图形11的表面上。在接合材料14中含有的焊锡粉与金属粉的重量比与上述的比例相比其金属粉的比例大。具体地,把焊锡粉与金属粉的重量比定为10∶13~30∶26。即,把金属粉的量增加了30%左右。通过增加在接合材料14中含有的金属粉的量,在后面的反射流焊接工序中使熔化的片状元件的电极层吸收进接合材料14内。其详细情况后述。
参照图5(B),接着把片状元件12B载置在接合材料14的上部。片状元件12B在其两端具有电极。该电极由内侧的第一电极层20A和外侧的第二电极层20B构成。第一电极层20A由Ag等贵金属构成。第二电极层20B由Sn(锡)等对焊锡润湿性优良的材料构成。
以下,参照图5(C)和图5(D),通过反射流焊接工序把片状元件12B固定结合。
图5(C)表示了反射流焊接工序中间阶段的状态。在接合材料14中含有的焊锡粉例如为Sn-Ag-Cu系列焊锡时,其熔化温度是220℃左右。在该工序中,为可靠地熔化焊锡粉,其反射流焊接温度是250℃左右。而构成第二电极层20B的Sn的熔化温度是231℃。因此在该反射流焊接温度下把接合材料14和第二电极层20B这两者熔化。该图表示熔化的第二电极层20B与接合材料14形成一体的情况。另外,第一电极层20A由熔化温度高的Ag和Au构成因此不熔化。
若通过反射流焊接工序把接合材料14熔化,则在接合材料14中含有的几乎所有的焊锡成分成为形成于金属粉14C表面上的金属间化合物14E。并且接合材料14含有大量的金属粉14C。因此在金属粉14C的所有表面上形成金属间化合物14E中,焊锡成分不足。由此,在表面上存在未生成金属间化合物的金属粉14C。或者,还存在仅部分生成金属间化合物的金属粉14C。并且由于,几乎所有的焊锡成分都成为金属间化合物14E,所以在金属粉14C之间形成了微细的间隙。另外,有某种程度量的焊锡成分附着在金属粉14C的表面上。
参照图5(D),构成第二电极层20B的Sn进入到接合材料14中,具体的是,熔化的Sn通过各金属粉14C的间隙浸透到接合材料14的内部。并且Sn与在在表面上未形成与焊锡的金属间化合物的金属粉14C的表面接触。并且含有Sn的金属间化合物14E在金属粉14C的表面生成。因此在反射流焊接工序时即使片状元件12B的电极被熔化,熔化的电极成分也进入到接合材料14中。这样,防止由熔化的电极成分流出导致的短路。
另外,混入金属粉14C的接合材料14即使在熔化的状态其粘度也高。因此通过使用本实施例的接合材料14来固定结合片状元件,能抑制曼哈顿现象。在此所谓的曼哈顿现象是指在进行反射流焊接时片状元件一侧的电极上浮的现象。
另外,大量含有金属粉14C的接合材料14在表面上形成有凹凸。因此提高密封整体的密封树脂与接合材料14C的结合强度。并且,片状元件12B的电极在反射流焊接时未熔化时,没有必要如上述那样增加金属粉14C的量。
下面参照图6及其以后的图说明图1所说明结构电路装置的制造方法。首先参照图6到图8说明图1(A)所示结构电路装置10A的制造方法。
首先参照图6(A),准备由铜等金属构成的导电箔。然后如图6(B)所示,除成为导电图形的位置之外形成抗蚀层PR。通过用湿蚀等除去方法除去从抗蚀层PR露出的导电箔30的表面,形成分离槽19。通过形成分离槽19使各导电图形11形成凸状。参照图6(C),通过接合材料14把半导体元件12A和片状元件12B固定结合在希望的导电图形11上。在此,使用的接合材料14可以使用以上述Bi为主的游离铅焊锡。并且也可以使用参照图4说明的混入金属粉14C的焊锡。另外,半导体元件12A的表面电极与导电图形11通过金属细线15电连接。
其次,参照图7(A),以填充分离槽19,覆盖电路元件的方式形成密封树脂18。该密封树脂18的形成可以通过使用热固化性树脂的转移成型或使用了热可塑性树脂的塑料注射成型进行。
其次,参照图7(B),通过从背面把导电箔30整个除去,使填充在分离槽19内的密封树脂18在背面露出,把各导电图形11电分离。然后通过进行形成保护层16和形成外部电极17,完成如图7(C)所示的电路装置10。
其次,参照图8,把在上述工序中制造的电路装置10固定结合在安装衬底31上的导电路32上。这可以通过反射流焊接工序进行。即,通过使电路装置10A的环境温度上升至在构成外部电极17的焊锡熔化的温度进行电路装置10的安装。在此,构成外部电极17的外部电极即使是采用熔点高的游离铅焊锡时,也能回避由接合材料14导致的问题。具体地通过接合材料14由以Bi为主材料的焊锡构成,能抑制接合材料14通过反射流焊接工序熔化。这是由于Bi的熔化温度比反射流焊接温度高的缘故。另外,通过把金属粉混入在接合材料14,即使在反射流焊接工序中在接合材料14中含有焊锡熔化时也能抑制树脂裂纹的发生。这是由于在接合材料14中含有几乎所有的焊锡成分在金属粉表面形成金属间化合物熔化的焊锡成分少的缘故。
其次,参照图9和图10说明图1(C)所示具有多层结构的电路装置10C的结构。首先参照图9(A),准备层积有第一导电箔33和第二导电箔34的层积板。并且参照图9(B),通过有选择地除去第一导电箔形成第一导电图形11A。另外,第一导电图形11A的希望位置和第二导电箔34贯通绝缘层22连接。
其次,参照图9(C),把半导体元件12A和片状元件12B用接合材料14固定结合在第一导电图形11A上。并且参照图10(A),以覆盖半导体元件12A和片状元件12B方式形成密封树脂18。
然后,参照图10(B),通过部分除去背面的第二导电箔34而形成第二导电图形11B。另外通过形成背面的保护层23和外部电极17而完成如图1(C)所示的电路装置10C。然后把电路装置10C在反射流焊接工序中安装在安装衬底31上,得到如图10(C)所示的安装结构。电路装置的安装与图8所示的工序相同。

Claims (11)

1.一种电路装置,其特征在于,其具备:电路元件、导电图形、用于接合所述电路元件与所述导电图形的接合材料,所述接合材料含有Bi。
2.如权利要求1所述的电路装置,其特征在于,所述电路元件、所述导电图形和所述接合材料由密封树脂覆盖。
3.如权利要求1所述的电路装置,其特征在于,其具备固定结合在所述导电图形上的外部电极,所述外部电极由游离铅焊锡形成。
4.如权利要求1所述的电路装置,其特征在于,所述接合材料含有Bi、Ag和Cu。
5.如权利要求3所述的电路装置,其特征在于,所述导电图形具有通过由树脂构成的绝缘层层积的多层配线结构,所述接合材料熔化的温度比所述外部电极熔化的温度高,且比所述绝缘层热解的温度低。
6.一种电路装置,其特征在于,其具备:电路元件、导电图形、用于接合所述电路元件与所述导电图形的接合材料,在所述接合材料中混入金属粉。
7.如权利要求6所述的电路装置,其特征在于,所述金属粉熔化的温度比所述接合材料熔化的温度高。
8.如权利要求6所述的电路装置,其特征在于,所述金属粉采用与形成所述接合材料的金属生成金属间化合物的金属。
9.如权利要求6所述的电路装置,其特征在于,所述金属粉采用Cu、Ni、Fe、Al、Ag、Au、Sb或Bi。
10.如权利要求6所述的电路装置,其特征在于,所述金属粉是由不同大小的粒子构成。
11.如权利要求6所述的电路装置,其特征在于,所述电路元件是两端形成有电极层的片型元件,所述电极层与所述导电图形通过所述接合材料连接,所述电极层的至少一部分与所述接合材料成为一体。
CNA2004100577621A 2003-08-26 2004-08-17 电路装置 Pending CN1592538A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP208741/2003 2003-08-26
JP2003208741 2003-08-26
JP2004220780A JP2005095977A (ja) 2003-08-26 2004-07-28 回路装置
JP220780/2004 2004-07-28

Publications (1)

Publication Number Publication Date
CN1592538A true CN1592538A (zh) 2005-03-09

Family

ID=34220643

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2004100577621A Pending CN1592538A (zh) 2003-08-26 2004-08-17 电路装置

Country Status (5)

Country Link
US (1) US7224066B2 (zh)
JP (1) JP2005095977A (zh)
KR (1) KR100629826B1 (zh)
CN (1) CN1592538A (zh)
TW (1) TWI290011B (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104254909A (zh) * 2012-04-27 2014-12-31 日产自动车株式会社 半导体装置的制造方法、隔热负荷夹具及其设置方法
CN105453708A (zh) * 2013-08-06 2016-03-30 本田技研工业株式会社 电子电路连接结构
CN105531075A (zh) * 2013-09-20 2016-04-27 住友金属矿山株式会社 Bi基钎料合金和使用其的电子部件的接合方法以及电子部件安装基板
CN107614185A (zh) * 2015-05-29 2018-01-19 株式会社村田制作所 接合用构件和接合方法
CN111996413A (zh) * 2020-08-21 2020-11-27 中国电子科技集团公司第三十八研究所 一种铅锡基焊料合金的制备方法及制得的焊料合金
CN117976637A (zh) * 2024-04-01 2024-05-03 甬矽半导体(宁波)有限公司 凸块封装结构和凸块封装结构的制备方法

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4456503B2 (ja) * 2004-12-24 2010-04-28 富士通メディアデバイス株式会社 電子部品の製造方法
JP4817418B2 (ja) 2005-01-31 2011-11-16 オンセミコンダクター・トレーディング・リミテッド 回路装置の製造方法
US7417312B2 (en) * 2005-04-22 2008-08-26 International Rectifier Corporation Use of solder paste for heat dissipation
JP4821537B2 (ja) * 2006-09-26 2011-11-24 株式会社デンソー 電子制御装置
US9214442B2 (en) * 2007-03-19 2015-12-15 Infineon Technologies Ag Power semiconductor module, method for producing a power semiconductor module, and semiconductor chip
JP2008246515A (ja) * 2007-03-29 2008-10-16 Tamura Seisakusho Co Ltd リフロー装置
KR101011199B1 (ko) * 2007-11-01 2011-01-26 파나소닉 주식회사 실장 구조체
JP2010103206A (ja) * 2008-10-22 2010-05-06 Panasonic Corp 半導体装置及びその製造方法
JP5517694B2 (ja) * 2010-03-29 2014-06-11 株式会社 日立パワーデバイス 半導体装置
JP2011251329A (ja) * 2010-06-04 2011-12-15 Sumitomo Metal Mining Co Ltd 高温鉛フリーはんだペースト
TWI419290B (zh) * 2010-10-29 2013-12-11 Advanced Semiconductor Eng 四方扁平無引腳封裝及其製作方法
JP5978630B2 (ja) * 2012-01-26 2016-08-24 Tdk株式会社 電子回路モジュール部品及び電子回路モジュール部品の製造方法
KR20140121211A (ko) * 2013-04-05 2014-10-15 부산대학교 산학협력단 고융점 무연 솔더 조성물, 고융점 무연 솔더 합금 제조방법 및 이의 용도
JP2015072996A (ja) 2013-10-02 2015-04-16 新光電気工業株式会社 半導体装置
JP5779666B2 (ja) * 2014-01-06 2015-09-16 株式会社 日立パワーデバイス 自動車用パワーモジュール、自動車
US9570381B2 (en) 2015-04-02 2017-02-14 Advanced Semiconductor Engineering, Inc. Semiconductor packages and related manufacturing methods
WO2018055667A1 (ja) * 2016-09-20 2018-03-29 三菱電機株式会社 半導体装置
CN115989579A (zh) * 2020-10-07 2023-04-18 株式会社东芝 接合体、陶瓷电路基板及半导体装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4098452A (en) * 1975-03-31 1978-07-04 General Electric Company Lead bonding method
JPS5572046A (en) * 1978-11-25 1980-05-30 Toshiba Corp Solder for semiconductor
JP2516123B2 (ja) * 1991-10-15 1996-07-10 株式会社フジクラ 金属と固体電解質との接合方法
JP3301908B2 (ja) * 1996-02-23 2002-07-15 京セラ株式会社 配線基板及びその製造方法
JPH10135377A (ja) * 1996-11-01 1998-05-22 Hitachi Ltd モールド型半導体装置
JP2001176927A (ja) * 1999-12-20 2001-06-29 Hitachi Ltd 半導体装置及びそれを用いた電子装置
JP2001237272A (ja) * 2000-02-23 2001-08-31 Hitachi Ltd 半導体装置及びこれを用いた電子装置
JP2003017847A (ja) * 2001-04-02 2003-01-17 Seiko Instruments Inc 電子回路装置及びその製造方法
JP3800977B2 (ja) * 2001-04-11 2006-07-26 株式会社日立製作所 Zn−Al系はんだを用いた製品
CN100475996C (zh) * 2001-05-28 2009-04-08 霍尼韦尔国际公司 高温无铅焊料用组合物、生产方法及元件
EP1266975A1 (de) * 2001-06-12 2002-12-18 ESEC Trading SA Bleifreies Lötmittel
JP2003007922A (ja) * 2001-06-19 2003-01-10 Sanyo Electric Co Ltd 回路装置の製造方法
US20050029666A1 (en) * 2001-08-31 2005-02-10 Yasutoshi Kurihara Semiconductor device structural body and electronic device
JP2003234433A (ja) * 2001-10-01 2003-08-22 Matsushita Electric Ind Co Ltd 半導体装置、半導体装置の実装方法、ならびに実装体およびその製造方法
JP4368081B2 (ja) * 2001-12-18 2009-11-18 三洋電機株式会社 チップ部品を実装した回路装置
JP2003211289A (ja) * 2002-01-21 2003-07-29 Fujitsu Ltd 導電性接合材料、それを用いた接合方法及び電子機器
US6854633B1 (en) * 2002-02-05 2005-02-15 Micron Technology, Inc. System with polymer masking flux for fabricating external contacts on semiconductor components
JP2004017093A (ja) * 2002-06-17 2004-01-22 Toshiba Corp 鉛フリーはんだ合金、及びこれを用いた鉛フリーはんだペースト

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104254909A (zh) * 2012-04-27 2014-12-31 日产自动车株式会社 半导体装置的制造方法、隔热负荷夹具及其设置方法
CN104254909B (zh) * 2012-04-27 2017-03-01 日产自动车株式会社 半导体装置的制造方法、隔热负荷夹具及其设置方法
CN105453708A (zh) * 2013-08-06 2016-03-30 本田技研工业株式会社 电子电路连接结构
CN105453708B (zh) * 2013-08-06 2018-02-02 本田技研工业株式会社 电子电路连接结构
CN105531075A (zh) * 2013-09-20 2016-04-27 住友金属矿山株式会社 Bi基钎料合金和使用其的电子部件的接合方法以及电子部件安装基板
CN107614185A (zh) * 2015-05-29 2018-01-19 株式会社村田制作所 接合用构件和接合方法
CN107614185B (zh) * 2015-05-29 2020-09-08 株式会社村田制作所 接合用构件和接合方法
CN111996413A (zh) * 2020-08-21 2020-11-27 中国电子科技集团公司第三十八研究所 一种铅锡基焊料合金的制备方法及制得的焊料合金
CN111996413B (zh) * 2020-08-21 2021-07-09 中国电子科技集团公司第三十八研究所 一种铅锡基焊料合金的制备方法及制得的焊料合金
CN117976637A (zh) * 2024-04-01 2024-05-03 甬矽半导体(宁波)有限公司 凸块封装结构和凸块封装结构的制备方法
CN117976637B (zh) * 2024-04-01 2024-07-05 甬矽半导体(宁波)有限公司 凸块封装结构和凸块封装结构的制备方法

Also Published As

Publication number Publication date
US7224066B2 (en) 2007-05-29
TW200509760A (en) 2005-03-01
TWI290011B (en) 2007-11-11
KR20050022303A (ko) 2005-03-07
KR100629826B1 (ko) 2006-09-29
JP2005095977A (ja) 2005-04-14
US20050046032A1 (en) 2005-03-03

Similar Documents

Publication Publication Date Title
CN1592538A (zh) 电路装置
CN1084917C (zh) 导电胶体材料及其应用
CN1080616C (zh) 焊料、用焊接法贴装的电子元件及电路板
KR100758760B1 (ko) 회로 장치 및 그 제조 방법
CN1128469C (zh) 将电子器件连接到柔性电路载体的方法及柔性电子载体
TWI233684B (en) Electronic device
US8501583B2 (en) Method for connecting between substrates, flip-chip mounting structure, and connection structure between substrates
CN1444269A (zh) 多层半导体器件及其制造方法
CN1535103A (zh) 接线板
JPH1145618A (ja) 導電ペースト構造およびその製造方法
CN1443625A (zh) 焊料
CN101965632A (zh) 半导体的安装结构体及其制造方法
CN101048258A (zh) 无Pb焊料合金
CN1701437A (zh) 电子装置
CN1666334A (zh) 反应焊接材料
KR100808746B1 (ko) 회로 장치의 제조 방법
CN1519076A (zh) 焊接方法、通过该焊接方法连接的元件和连接结构
US8466546B2 (en) Chip-scale package
CN100454529C (zh) 用于形成互连结构的焊膏以及由焊膏形成的互连结构
JP5113390B2 (ja) 配線間接続方法
US11581239B2 (en) Lead-free solder paste as thermal interface material
US20200230750A1 (en) Lead-free solder paste for thermal via filling
CN1266989C (zh) 锡焊方法及焊接结构体
CN113275787B (zh) 作为热界面材料的无铅焊料膏
CN2711900Y (zh) 针格阵列电气封装体及其载板

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C12 Rejection of a patent application after its publication
RJ01 Rejection of invention patent application after publication