CN1574307A - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN1574307A CN1574307A CNA2004100489283A CN200410048928A CN1574307A CN 1574307 A CN1574307 A CN 1574307A CN A2004100489283 A CNA2004100489283 A CN A2004100489283A CN 200410048928 A CN200410048928 A CN 200410048928A CN 1574307 A CN1574307 A CN 1574307A
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- China
- Prior art keywords
- term
- short
- conductor wiring
- plating
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 120
- 238000007747 plating Methods 0.000 claims abstract description 120
- 239000004020 conductor Substances 0.000 claims description 204
- 239000000463 material Substances 0.000 claims description 34
- 230000002093 peripheral effect Effects 0.000 claims 5
- 238000009713 electroplating Methods 0.000 description 37
- 230000015572 biosynthetic process Effects 0.000 description 17
- 239000000758 substrate Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 13
- 239000004744 fabric Substances 0.000 description 12
- 229910000679 solder Inorganic materials 0.000 description 11
- 230000009931 harmful effect Effects 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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- General Physics & Mathematics (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
一种半导体器件,包括基材、具有多个电极的半导体元件、连接半导体元件的电极的多根导体布线、附于导体布线的电镀用短线、及在基材上形成的多层布线层。附于第一导体布线的电镀用短线和附于与第一导体布线相邻的单根或多根第二导体布线的电镀用短线,存在于不同的导体布线层。
Description
技术领域
本发明涉及半导体器件,尤其涉及在信号传送时抗噪性能优良、而且在信号高速传送时能发挥出色效果的半导体器件。
背景技术
近些年来,随着电子设备的小型化、高速化的发展,也开始要求半导体器件高密度、高性能、高速度。其中作为半导体器件的实际安装形态,有一种不是在周围的端子而是能在整个面上将端子配置成栅格状的栅网阵列型,它作为高密度安装的主流受到人们的关注并正在开发中。栅网阵列型的半导体器件通常大多采用布线基板,以适应上述要求。这是由于,如采用布线基板,则能将布线层三维层迭,除能对众多的布线进行高密度的布线之外,布线的自由度也大,另外电气性能也易增强。
作为公知的BGA(球栅阵列ball·grid·array)型半导体器件,可以举出JP-A-6-112354所揭示的一个例子。
上述公知的半导体器件中,如图17所示,先将半导体元件装在布线连接基板50上,利用金属线键合或凸点的金属凸起使半导体元件1上的电极2和基板50的导体布线5上的焊点电气连接。布线基板50由多层布线层组成,通孔6沿垂直方向使位于不同布线层的导体布线之间互相连接,在电路上连通。此后,用树脂封装,在装上称为焊球的电极端子后,再在图中虚线处3将布线连接基板50切成一块一块单块基板。
该切下的基板为图18A、图18B示出的单片部分。在上述图中,51、52为布线层。导体布线5的焊点9上为了确连接性能进行镀层处理。对于此时的镀层,一般从成本、处理速度等角度考虑大多采用电镀。由此,如图1 7所示,电镀用的电镀引线8通过电镀用短线7附于导体布线5上,对电极端的焊点9进行电镀。再从易于形成布线图形的角度考虑,这些电镀引线8附于最上层或最下层的布线上。虽然上述电镀引线8在图17示出的连接基板50的状态下是与所有的导体布线50连接,在电气上全部短接,但在对该焊点9的电镀完成后切成一块块基板时,由于对于信号传送而言是不需要的,若将各导体布线5短接,则信号就不能传送。因此,在沿虚线处3切断连接基板50时也同样要切断,使得各导体布线5在电气上保持独立,切断后附在图18A、图18B的各导体布线上的电镀用短线7依旧残留着。
但是,这种公知的构成中,存在如下的问题。
首先,各基板的导体布线5在传送信号时,残留的电镀用短线7在电气上是根本无用的。但若将其完全除去,则必须采用化学电镀,考虑到生产成本、制造能力,这是不现实的。
以下,叙述由于残留电镀用短线7所引发的问题。
第一点,如图17及图18A所示,如电镀用短线7集中在基板的最上层或最下层上,则噪声恐怕会从两边相邻的导体布线10及11经电镀用短线7窜入附带着该电镀用短线7的导体布线5,或由于附于导体布线10及11上的其它电镀用短线12及13与电镀用短线7间的干扰,噪声也会窜入。特别是在采用BGA等布线基板的半导体器件上,大多为高密度布线,由于今后随着功能的增强,输入输出端子数呈现越来越多的趋向,所以提高布线密度是一个方面的问题,而将来除了这一担心之外,问题很可能会发展到电镀用短线之间的电气短路或迁移而造成电气破坏。另外,在提高信号速度时,由于频率增高,或信号振幅减小,所以就对噪声相应地变得敏感,估计这样的问题会变得更加显著。
第二点,为电镀用短线7本身的长度。一般都知道,从电镀用短线上产生电磁发射。该发射噪声对其它信号造成波形失真、延迟等问题。还有,当传输的信号速度一高,根据频率或信号种类,电镀用短线7具有电容特性,所以有可能对导体布线中传送的信号带来不良影响,又在布线基板进行阻抗匹配时,由于这一短线将产生不需要的反射,无法得到原本想要的阻抗。另外,发射无用的噪声也造成能量的损耗。
这样,公知的半导体器件对于以上有关电镀用短线的问题,完全没有采取相应的措施。
发明内容
本发明正是为解决上述公知的半导体器件所存在的问题,其目的在于提供一种半导体器件,它不增加成本,主要是通过在设计上下工夫,防止由于来自电镀用短线的噪声或电镀用短线本身产生的发射噪声而造成的信号波形失真,同时还防止从外部通过电镀用短线窜入的噪声,通过这样最终能获得优良的信号传送性能。
为达到这一目的,本发明的半导体器件具有以下的结构。
本发明的半导体器件包括具有多个电极的半导体元件、连接所述半导体元件的电极的多根导体布线、附于所述导体布线上的电镀用短线、及在基材上形成的多层布线层,附于第一导体布线上的电镀用短线和附于与所述第一导体布线相邻的单根或多根第二导体布线上的电镀用短线,存在于不同的导体布线层。
由此,因为传送信号的导体布线及电镀用短线和相邻的导线布线的电镀用短线远离,故能防止噪声从电镀用短线窜入。
最好第一导体布线与接地或电源连接。
由此,能防止电镀用短线对连接接地或电源的第一导体布线带来不良的影响。
根据本发明,最好第一导体布线传送的信号为数字信号。
由此,能有效防止上述噪声。
根据本发明,最好上述数字信号的频带在100MHz及以上。
由此,能有效防止上述噪声。
根据本发明,最好附于第一导体布线的电镀用短线和附于第二导体布线的电镀用短线间的距离比附于第一导体布线的电镀用短线和与附于该第一导体布线的电镀用短线存在于同一布线层的其它电镀用短线的最小布线距还要大。
由此,除了上述防噪措施外,还能更有效地防止电镀用短线之间的干扰。
本发明的其它实施形态为,包括具有电极的半导体元件、连接所述半导体元件的电极的导体布线、附于所述导体布线上的电镀用短线、及在基材上形成的多层布线层,所述导体布线遍及多层布线层而形成,从导体布线向基材的周围形成所述电镀用短线,同时还根据导体布线的布置,形成于能使电镀用短线长度为最短的布线层。
再有,本发明的其它实施形态为,包括设在基材上的具有电极的半导体元件、连接所述半导体元件的电极的导体布线、附于所述导体布线上的电镀用短线、及在基材上形成的多层布线层,从所述电极开始向着和基材上设置半导体元件的面相反一侧的面遍及多层布线层、并从所述电极开始向着基材的周围形成所述导体布线,而在所述相反一侧面的布线层上从导体布线向基材的周围形成所述电镀用短线。
再有,本发明的其它实施形态为,包括设在基材上的具有电极的半导体元件、连接所述半导体元件的电极的导体布线、附于所述导体布线上的电镀用短线、及在基材上形成的多层布线层,从所述电极开始向着和基材上设置半导体元件的面相反一侧的面遍及多层布线层,并从基材的周围向基材的中间形成所述导体布线,而在所述半导体元件侧一面的布线层上从导体布线开始向着基材的周围形成所述电镀用短线。
根据上述构成,因为能使电镀用短线的长度为最短,所以能有效地防止来自电镀用短线的电磁发射或噪声、及电镀用短线之间的电气干扰。另外,布线基板上的阻抗匹配也方便,信号失真也能减小。
再有,本发明的其它实施形态为,包括具有多个电极的半导体元件、连接所述半导体元件的电极的多根导体布线、及附于所述导体布线的电镀用短线,所述电镀用短线形成的线宽比所述导体布线的线宽要小。
在这种情况下,最好是附于第一导体布线上的、同时与第二导体布线相邻配置的电镀用短线形成的线宽比所述第一及/或第二导体布线的线宽要小。
再有,本发明的其它实施形态为,包括具有多个电极的半导体元件、连接所述半导体元件的电极的多根导体布线、及附于所述导体布线的电镀用短线,附于上述导线布线并相邻的电镀用短线之间形成的线距比相邻的导体布线之间的线距要大。
在这种情况下,最好是附于第一导体布线上的、同时与第二导体布线相邻配置的电镀用短线和所述第二导体布线之间形成的线距比所述第一导线和第二导线的线距要大。
由此,能有效地防止电镀用短线产生的电磁发射或噪声的影响、及电镀用短线之间的电气干扰。
如上所述,根据本发明,能提供一种能防止电镀用短线引起的电磁发射或噪声并能降低电镀用短线之间的电气干扰的、电气性能优良的半导体器件。
附图说明
图1为本发明的半导体器体的实施例1中布线基板的平面图。
图2A及图2B为表示本发明的半导体器件的实施例1中布线基板的布线图形。
图3A及图3B为表示本发明的半导体器件的实施例1中布线基板的其它布线图形。
图4A-图4G为表示本发明实施例1中布线基板的制造方法示例。
图5A及图5B为表示本发明的半导体器件的实施例2中布线图形例子的示意图。
图6为表示本发明的半导体器件的实施例3中布线图形例子的示意图。
图7A及图7B为表示本发明的半导体器件的实施例4中布线图形例子的示意图。
图8A及图8C为表示本发明的半导体器件的实施例5中布线图形例子的示意图。
图9为表示本发明的半导体器件的实施例6中布线图形例子的示意图。
图10为表示本发明的半导体器件的实施例6中布线基板的其它布线图形的示意图。
图11为表示本发明的半导体器件的实施例7中布线图形例子的示意图。
图12为表示本发明的半导体器件的实施例8中布线图形例子的示意图。
图13为表示本发明的半导体器件的实施例9中布线图形例子的示意图。
图14为表示本发明的半导体器件的实施例10中布线图形例子的示意图。
图15为表示本发明的半导体器件的实施例11中布线图形例子的示意图。
图16为表示本发明的半导体器件的实施例12中布线图形例子的示意图。
图17为表示公知的半导体器件的布线基板的平面图。
图18A及图18B为表示公知的半导体器件的布线图形例子的示意图。
具体实施方式
(实施例1)
图1为本发明的半导体器件的实施例1中布线基板的平面图。图2A为图1的半导体器件的局部放大图,为将图1的布线基板切成单块部分的上层的图形例子,而且是在图1示出的4个方向中,仅示出一个方向的图形作为代表。图2B为下层的图形例子。
图1中,半导体元件1有电极端子2。本例中,半导体元件1安装在布线基板上,但表示的是还未用树脂封装的状态。然而,和上述公知的情况一样,在经过封装并安装焊球之后,最终沿虚线所示的每条边的切断位置3切断。
在图2A及图2B上,51为形成上层的布线层,52为形成下层的布线层。布线基板利用金属线4等和半导体元件1电气连接,布线基板上有导体布线5、沿垂直方向连接不同布线层的导体布线之间的通路6、和附于导体布线的电镀用短线7。因电镀用短线7在基板切断前与图1的电镀引线8连接,故能用其进行电镀,若用阻焊剂等将设在图2的导体布线5的连接端的焊点9以外部分遮盖后进行电镀,则只有焊点9被电镀,从而能保护金属线4和导体布线间连接用的界面。在导体布线5为铜材时,作为电镀处理通常是在电镀镍后再进行电镀金的处理。另外,本例中,关于半导体元件1和布线基板间的连接结构,作为一个例子是示出了用金属线4进行连接的方式,但连接方法、材质等并不限于此,只要是能将两者电气连接的,则任何方法及材质均可。由于在以后所有的实施例中上述各部分的结构及其关系都相同,故以后将不再赘述。
实施例1中,导线布线5与半导体元件1的模拟端子连接,与该导线布线5的电镀用短线7相邻的导体布线10及11的电镀用短线12及13和电镀用短线7不是在同一的布线层51,而是设在另外的布线层52。这时,可以设在紧挨着的底下一层,或底下两层的一层,只要是不同的布线层都可,还有,布线基板的全部层数只要是多层就属于本实施例1的范畴。14为下层的导体布线,24为焊球。
根据本实施例1,只要在其它的层上存在至少相邻的导体布线10、5、11的电镀用短线12、7、13即可,极端的情况如图3A及图3B所示,也可以是导体布线5以外残留的所有导体布线的电镀用短线都在不同的布线层。但总之,由于电镀用短线的形成通常和各层的导体布线的图形一样地一起进行,所以工序道数和不采用实施例时一样。即如本实施例1的情况那样,在下层上设置模拟的导体布线5的两边的导体布线10及11的电镀用短线12及13的情况下,如图2B所示,只要预先准备好电镀用短线12及13作为下层52的布线图形的一部分,和导体布线14的图形形成同时进行。这样,在将电镀用短线12、13设在上层以外的布线层52的情况下,这些电镀用短线12、13在图1的连接基板的状态下借助通路6和电镀用引线8连接。
关于实现本实施例1的半导体器件用的制造方法,则完全属于公知技术的范围,不同之处仅在于将电镀用短线设在哪一层上而已。图4A-图4F表示本实施例1的布线基板的制造方法例子。详细来说,首先对图4A示出的敷铜箔的绝缘层15,如图4B所示,用光刻胶16形成布线图形,然后如图4C所示,除去内层铜箔17的不需要的部分。若如图4C所示两面的图形已完成,则如图4D所示,在其上面压紧外层用敷铜箔的绝缘层18,再如图4E所示,用钻头开出通孔19,又如图4F所示,在这部分上镀铜20,使其与最上层的外层铜箔21电气导通。再如图4G所示,只要最上层和最下层形成和刚才的内层同样的布线图形就可。22为最下层的外层铜箔。
以上是典型的4层基板的制造方法,但归根结底该制造方法是一个实例,本实施例1中,在各层形成布线图形时,只要将电镀用短线12及13设在想要设的层上就可。例如仅仅图4G的最下一层的外层铜箔22如图2B所示那样形成配置图形,除此以外的层只与上述同样形成布线图形,即使这样也与本实施例1相当。
根据以上的构成,传送模拟信号的导体布线5的电镀用短线7和至少两边的导体布线10及11的电镀用短线12及13,因为各自的布线层不同,因此上述电镀用短线之间不相邻,这些电镀用短线之间的间隔加宽,另外电镀用短线12及13和导体布线5之间的距离也增大。因此,尽管从电镀用短线12及13产生电磁发射或噪声,仍能防止其对传送模拟信号的导体布线5带来的不良影响。
因而,能提供一种噪声小、对模拟信号传送波形的失真也小的半导体器件。
(实施例2)
图5A及图5B为本发明的半导体器件的实施例2中布线基板的布线图形例子。图中的编号除导体布线25外,其余和图1、图2A及图2B中使用的相同。本实施例2和实施例1不同之处为,该导体布线、即和相邻的导线布线在不同布线层形成的特定的导体布线其传送信号为接地或电源。即在图5A及图5B中,特定的导体布线25与接地或电源连接。
根据以上的构成,由于接地或电源的导体布线25的电镀用短线7至少和两边的导体布线10、11的电镀用短线12、13中在不同的布线层51、52上,因此电镀用短线之间不相邻,加大电镀用短线之间的间隔,另外电镀用短线12、13和导体布线25之间的距离也增大。因此,即使从电镀用短线12、13产生电磁发射或噪声,也能防止对接地及电源的导体布线25带来的不良影响。
因而能提供在接地和电源上噪声小的半导体器件。
(实施例3)
图6表示本发明的半导体器件的实施例3中的布线图形例子。图中的编号除导体布线26外,其余和图1、图2A及图2B中使用的相同。本实施例3和实施例1不同之处在于,该导体布线26的传送信号为数字信号。
根据以上的构成,由于数字信号的导体布线26的电镀用短线7至少和两边的导体布线10、11的电镀用短线12及13(图中未示出)在不同的布线层,因此两者不相邻,两者的间距加宽,另外导体布线10、11的电镀用短线和导体布线26之间的距离也增大。
数字信号含高次谐波分量,实际含有名义上的频率的几倍至10倍的谐波分量。在产生噪声时,该高频分量对噪声敏感,所以结果对信号的影响颇大。但由于采用上述的构成,即便从导体布线10、11的电镀用短线产生电磁发射或噪声,仍能防止对传送数字信号的导体布线26带来的不良影响。
因此,能提供噪声小并且数字信号传送波形的失真也小的半导体器件。
以上,实施例1、2、3中分别对不同的信号的种类进行了说明,这些实施例1、2、3之本质为,只要用至少1根导体布线的电镀用短线和其两边的电镀用短线来实现就可,本发明也包括在1块半导体器件的各根导体布线上同时实现上述实施例1、2、3的情况。
(实施例4)
图7A及图7B表示本发明的半导体器件的实施例4中布线图形例子。本实施例4与实施例3不同之处在于,传送频带大于100MHz。100MHz以上的数字信号特别易受噪声影响。因此,采用这样的结构,即只选择在数字信号中传送100MHz以上的导体布线27上所附的电镀用短线7、和其两边的导体布线10、11上所附的电镀用短线12、13,设置在不同的布线层51、52。
根据以上的构成,因为传送数字信号中的100MHz以上信号的导体布线27的电镀用短线7和其两边的导体布线10、11的电镀用短线12、13的布线层不同,所以上述电镀用短线之间不相邻,这些电镀用短线之间的间隔加宽,另外导体布线27与其两边的导体布线10、11的电镀用短线12、13之间的距离也加大。
如为频率100MHz以上的高速信号,作为其谐波分量考虑到要传送约1GHz的信号,故要优先采取抗噪声的措施。此时,因数字信号中限定上述100MHz以上的信号选取导线布线距,故能力求实现较上述实施例3更有效的措施。
即,与图6的布线图形例子相比,图7的布线图形例子中,仅将100MHz以上信号的导体布线27的电镀用引线7设置在不同的布线层上。因此,即便从别的电镀用短线12、13产生电磁放射或噪声,仍能防止对传送100MHz以上数字信号的导体布线27带来不良影响。
因而,能提供噪声小、对数字信号传送波形的失真小的半导体器件用的布线基板。
(实施例5)
图8A-图8C为表示本发明的半导体器件的实施例5中布线图形例子。本实施例5中和实施例1至4的不同之处如下。即采用下述的结构,使导体布线5的电镀用短线7和附于导体布线5两边的导体布线10及11上而且存在于不同布线层的电镀用短线29A及29B之间的距离,比从该导体布线5的电镀用短线7起至形成导体布线5的同一布线层内附于其它的导体布线上的电镀用短线28A或28B间的最小间隔还要大。
即采用下述的结构,使电镀用短线7、和不同布线层52的电镀用短线29A、29B之间的间隔31,大于从与导体布线5同一布线层51内的电镀用短线7至电镀用短线28A或28B的电镀用短线之间的最小间隔30。在本例中,以导体布线5为例,但不管传送信号的种类,是模拟、数字、电源及接地等均可。
根据以上的构成,由于某导体布线5的电镀用短线7和其两边的导体布线10、11的电镀用短线29A及29B在不同的布线层上,加上与其的距离比在同一布线层中与最接近的电镀用短线28A及28B的距离大,故该两边的导体布线10、11的电镀用短线29A、及29B就位于离导体布线5的电镀用短线7足够远的位置。因此,即使从电镀用短线29A及29B产生电磁发射及噪声,仍能防止其对导体布线5的不良影响。
因而,能提供噪声小、并且传送波形的失真也小的半导体器件用布线基板。
(实施例6)
由于本实施例6和所述的实施例1-4仅在布线图形上不同,故只对这部分内容进行阐述。图9为本发明的半导体器件的实施例6的剖面图,1为半导体元件,5为导体布线,4为金属线,6为通路。
箭头48表示一连串的信号路径,该信号路径48从半导体元件1至金属线4,数次通过导体布线5、通路6,至焊球24。半导体元件1用树脂49封装。23为阻焊剂。本实施例6中,利用4层基板构成电路。
而且,本实施例6中,为了使电镀用短线7的长度L最短,选择第四层作为有该电镀用短线7存在的布线层。即在第二层设置用虚线表示的假想的电镀用短线35的情况下,其长度为从布线基板的四周至通路6的距离,但因为设置在第四层时,电镀用短线7的长度L为从布线基板的四周至通路6的距离,所以明显地缩短。
本实施例6中,对于附于所有导体布线上的电镀用短线,逐一采用这种选择方法。图10为本实施例6的半导体器件的剖面图,表示逐一设置最短的电镀用短线的例子。导体布线5A其电镀用短线7A设在第二层,导体布线5B其电镀用短线7B设在第三层。与此相比,如层数或布线数越多,则其选择的路径分支增加,但处理方法同上。
根据以上的构成,电镀用短线7、7A、7B以最短的长度附于各导体布线5上,使从电镀用短线7、7A、7B的电磁发射、或噪声等电气影响抑制在最低限度。另外,在进行阻抗控制时,由于能忽略不计电镀用短线7、7A、7B的电气影响,所以也能容易实现。
因而,能提供噪声或电磁发射小、并且能耗少的半导体器件。
(实施例7)
图11为本发明的半导体器件的实施例7的剖面图。
本实施例7中,导体布线5在布线基板上向着其外部依照信号路径的箭头48沿一个方向布线。6为通路。即从和半导体元件1上的电极2的端子连接的焊点9至相反一侧的焊球24以最短的距离布线。再在本例中,以最短的距离将电镀用短线7C和最下层的导体布线端连接。因此,例如与连接其它布线层的布线端的情况相比,电镀用短线7C最短。L是其长度。使上述情况在至少一根导体布线5上实现。
根据以上的构成,电镀用短线7C以最短的长度附于各导体布线上,导体布线上电镀用短线的影响最小,根据这一效果,两边的电镀用短线之间的影响也变得最小。特别是电镀用短线,由于相对于传送的频率即波长的布线长度一长,对具有电容性或电感性,将对所附的导电布线产生电气影响,所以信号速度一高,波长就短,相对来说电镀用短线的布线长度的影响增大,恐怕会助长这一影响。即,使原来应有的传送波形失真。本实施例7具有能防止这些不良影响的作用。另外在进行阻抗控制时,因能忽略不计电镀用短线的电气影响,所以也能容易实现。
因而,能提供传送信号时传送波形失真小的半导体器件。
(实施例8)
图12为本发明的半导体器件的实施例8的剖面图。图中的编号全部和图11中所用的相同。本实施例8中,导体布线5通过通路6向着布线基板的中心沿箭头48所示的一个方向布线。即,从通路6至焊球24以最短的距离布线。这里,将电镀用短线7C以最短距离与最上层的导体布线连接。因此,这里例如和其它布线层的布线端连接的情况相比,电镀用短线也最短。这些至少在一根的导体布线上实现。
其作用也和先前实施例7的情况一样,在于能减少从电镀用短线7对其所附的导体布线5本身的影响或对相邻电镀用短线的影响。另外,在进行阻抗控制时,因能忽略不计电镀用短线7C的电气影响,故也能容易实现。
因而,能提供在传送信号时传送波形失真小的半导体器件。
(实施例9)
图13表示本发明的半导体器件的实施例9的布线图形。
本实施例9中,电镀用短线7的布线宽度比其所附的导体布线的布线宽度小。9为设在导体布线5的连接端的焊点。如上所述,若不改变布线宽度,单纯加大布线距,则将产生与加大的一侧相反的一侧之间的布线距变窄的情况,但这样使电镀用短线7的布线宽度减小时没有上述的担忧,由于仅使该布线宽度减小,所以有能将其两侧的布线距加大的优点。而且,能够减小线宽,将能提高电镀用短线7的阻值。由于短线本身不是信号的路径,所以该阻值和导体布线传输的信号无直接关系。
利用这一构成,相邻的电镀用短线7之间的布线距加宽,相邻的电镀用短线7和导体布线间的距离也增大。另外,由于电镀用短线的布线宽度减小,这部分的电阻变大,即使从外部窜入噪声电压,但影响所附的导体布线的电流的绝对量也变小。故而,能降低从两边的导体布线经电镀用短线7的噪声和相反从该电镀用短线7经相邻的电镀用短线窜入导体布线的电磁发射或噪声。
因而,本发明能提供在传送信号时传送信号波形失真小的半导体器件。
(实施例10)
图14表示本发明的半导体器件的实施例10的布线图形。本实施例10中和实施例9相比,不同之处在于,电镀用短线的布线宽度限于与导体布线5并排的电镀用短线39,比该电镀用短线39所附的导体布线的布线宽度窄。在电镀用短线39和相邻的导体布线5大致并排设置时,虽然该导体布线5来的噪声窜入电镀用短线39,对附着该电镀用短线39的导体布线带来使信号波形失真的不良影响的可能性增大,但电镀用短线39若和该电镀用短线39并排的导体布线5相比,线宽度变细,则能有效地减少这一不良影响。另外,半导体元件的端子数目一多,由于布线密度就更高,因此上述问题更显著,与信号的误动作也有关联,但根据本实施例能防止上述现象。
利用这一构成,能减少从两边的导体布线5、5来的经电镀用短线39的噪声、和相反从该电镀用短线39窜入相邻的导体布线5、5的发射或噪声。
因而,能提供传送信号时传送波形失真小的半导体器件。
(实施例11)。
图15为本发明的半导体器件的实施例11的布线图形,本实施例11中,相邻的电镀用短线7、7之间的布线距41比这些短线7、7所附的导体布线5、5之间的布线距40要大。通常的布线中,由于焊点9的间隔在导体布线中最小,越向基板的四周,布线空间越大,因此电镀用短线7、7之间的间隔41能比导体布线的间隔40宽。因此,接受来自电镀用短线7的噪声的可能性降低。例如来自两边的导体布线或两边的电镀用短线的噪声窜入电镀用短线7,有可能对其所附的导体布线5上的信号波形带来造成失真的不良影响,但电镀用短线的布线距一大,该影响就减弱。另外,半导体元件的端子数一多,由于布线密度就更高,信号波形的失真等更加显著,与信号的误动作也有关联,但根据本实施例能防止上述现象。
利用这一构成,能减少从两边的导体布线5、5经电镀用短线7来的噪声、及相反从该电镀用短线7经相邻的电镀用短线7窜入导体布线5的发射或噪声。
因而,能提供传送信号时传送波形失真小的半导体器件。
(实施例12)
图16表示本发明的半导体器件的实施例12的布线图形。本实施例12中和实施例11相比,不同之处在于,电镀用短线和导体布线5的布线距限于和相邻的导体布线5并排的电镀用短线39,比该电镀用短线39所附的导体布线5和其它的导体布线5间的布线距要大。
在电镀用短线39和相邻的导体布线5几乎并排时,来自该导体布线5的噪声窜入电镀用短线39,对该电镀用短线39所附的导体布线5上的信号带来波形失真的不良影响的可能性增大。但是,若电镀用短线39之间的布线距41比其所附的导体布线5和其它的导体布线5间的间隔40要大,则能有效地减少这一不良影响。另外,半导体元件1的端子数一多,由于布线密度就更高,所以上述问题更显著,与信号的误动作也有关联,但根据本实施例能防止上述现象。
利用这一构成,能减少从两边的导体布线5、5经电镀用短线39来的噪声、及相反从该电镀用短线39窜入导体布线5的发射或噪声。
因而,能提供在传送信号时传送波形失真小的半导体器件。
Claims (12)
1.一种半导体器件,其特征在于,包括
基材、具有多个电极的半导体元件、连接所述半导体元件的电极的多根导体布线、附于所述导体布线上的电镀用短线、及在所述基材上形成的多层布线层,
附于第一导体布线上的电镀用短线、和附于与所述第一导体布线相邻的单根或多根的第二导体布线上的电镀用短线,存在于不同的导体布线层上。
2.如权利要求1所述的半导体器件,其特征在于,
第一导体布线与接地或电源连接。
3.如权利要求1所述的半导体器件,其特征在于,
第一导体布线上传送的信号是数字信号。
4.如权利要求3所述的半导体器件,其特征在于,
数字信号的频带大于等于100MHz。
5.如权利要求1所述的半导体器件,其特征在于,
附于第一导体布线的电镀用短线和附于第二导体布线的电镀用短线间的距离比附于第一导体布线的电镀用短线和存在于与该第一导体布线所附的电镀用短线同一布线层的其它电镀用短线的最小布线距还要大。
6.一种半导体器件,其特征在于,包括
具有周围部分的基材、具有电极的半导体元件、连接所述半导体元件的电极的导体布线、附于所述导体布线的电镀用短线、及在所述基材上形成的多层布线层,
所述导体布线遍及多层布线层而形成,
从导体布线开始向着基材的所述周围部分形成所述电镀用短线,同时还根据导体布线的配置,形成于能使该电镀用短线的长度为最短的布线层。
7.一种半导体器件,其特征在于,包括
具有两个面和周围部分的基材、设在该基材一面上的具有电极的半导体元件、连接所述半导体元件的电极的导体布线、附于所述导体布线的电镀用短线、及在基材上形成的多层布线层,
从所述电极开始向着和基材上设置半导体元件的一面相反一侧的面遍及多层布线层、并且从所述电极向基材的所述周围部分形成所述导体布线,
而在所述相反一侧的面的布线层上从导体布线向着基材的周围部分形成所述电镀用短线。
8.一种半导体器件,其特征在于,包括
具有两个面和中间部、分及周围的基材、设在该基材一面上的具有电极的半导体元件、连接所述半导体元件的电极的导体布线、附于所述导体布线的电镀用短线、及在基材上形成的多层布线层,从所述电极起向着和基材上设置半导体元件的一面相对一侧的面遍及多层布线层、并且从基材的所述周围向所述中间部分形成所述导体布线,而在所述半导体元件侧的一面的布线层上从导体布线向基材的所述周围形成所述电镀用短线。
9.一种半导体器件,其特征在于,包括
具有多个电极的半导体元件、连接所述半导体元件的电极的多根导体布线、及附于所述导体布线的电镀用短线,
所述电镀用短线形成的线宽比所述导体布线的线宽要小。
10.如权利要求9所述的半导体器件,其特征在于,包括
第一导体布线、第二导体布线、及附于所述第一导体布线的电镀用短线,
所述第一导体布线和电镀用短线与第二导体布线相邻配置,
所述电镀用短线形成的线宽比所述第一及/或第二导体布线的线宽要小。
11.一种半导体器件,其特征在于,包括
具有多个电极的半导体元件、连接所述半导体元件的电极的多根导体布线、及附于所述导体布线的电镀用短线,
与相邻的导体布线之间的线距相比,附于这些导体布线并相邻的电镀用短线之间形成的线距要大。
12.如权利要求11所述的半导体器件,其特征在于,包括
第一导体布线、第二导体布线、及附于所述第一导体布线的电镀用短线,
所述第一导体布线和电镀用短线与第二导体布线相邻配置,
所述电镀用短线和所述第二导体布线间形成的线距比所述第一导体布线和第二导体布线之间的线距要大。
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JP2003165819 | 2003-06-11 | ||
JP2003165819A JP2005005409A (ja) | 2003-06-11 | 2003-06-11 | 半導体装置 |
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CNA2004100489283A Pending CN1574307A (zh) | 2003-06-11 | 2004-06-11 | 半导体器件 |
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US (1) | US7164196B2 (zh) |
JP (1) | JP2005005409A (zh) |
KR (1) | KR20040106252A (zh) |
CN (1) | CN1574307A (zh) |
TW (1) | TWI245380B (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102640575A (zh) * | 2009-12-03 | 2012-08-15 | 国际商业机器公司 | 使用电阻性耦合减少芯片封装体中的电镀余线反射 |
CN106971998A (zh) * | 2015-10-29 | 2017-07-21 | 飞思卡尔半导体公司 | 利用布设的基板 |
CN107205315A (zh) * | 2016-03-18 | 2017-09-26 | 慧荣科技股份有限公司 | 印刷电路板以及组件制造方法 |
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US20060043565A1 (en) * | 2004-08-27 | 2006-03-02 | Chia Chok J | Laser removal of plating tails for high speed packages |
JP4676859B2 (ja) * | 2005-10-07 | 2011-04-27 | 日本シイエムケイ株式会社 | 電子部品パッケージ用プリント配線板及びその製造方法 |
US8830690B2 (en) * | 2008-09-25 | 2014-09-09 | International Business Machines Corporation | Minimizing plating stub reflections in a chip package using capacitance |
US8402406B2 (en) * | 2010-12-28 | 2013-03-19 | International Business Machines Corporation | Controlling plating stub reflections in a chip package |
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EP0582052A1 (en) | 1992-08-06 | 1994-02-09 | Motorola, Inc. | Low profile overmolded semiconductor device and method for making the same |
JP3023265B2 (ja) | 1992-09-26 | 2000-03-21 | 日本特殊陶業株式会社 | 集積回路用パッケージ本体 |
JP3290754B2 (ja) | 1993-05-26 | 2002-06-10 | 株式会社東芝 | 半導体搭載用多層基板 |
JP3253765B2 (ja) * | 1993-06-25 | 2002-02-04 | 富士通株式会社 | 半導体装置 |
US5467252A (en) * | 1993-10-18 | 1995-11-14 | Motorola, Inc. | Method for plating using nested plating buses and semiconductor device having the same |
KR0184076B1 (ko) * | 1995-11-28 | 1999-03-20 | 김광호 | 상하 접속 수단이 패키지 내부에 형성되어 있는 3차원 적층형 패키지 |
JP3340610B2 (ja) | 1996-01-22 | 2002-11-05 | 日本特殊陶業株式会社 | 電子部品用パッケージ本体及びその製造方法 |
SG99939A1 (en) * | 2000-08-11 | 2003-11-27 | Casio Computer Co Ltd | Semiconductor device |
US6632343B1 (en) * | 2000-08-30 | 2003-10-14 | Micron Technology, Inc. | Method and apparatus for electrolytic plating of surface metals |
US6608375B2 (en) * | 2001-04-06 | 2003-08-19 | Oki Electric Industry Co., Ltd. | Semiconductor apparatus with decoupling capacitor |
JP3939504B2 (ja) * | 2001-04-17 | 2007-07-04 | カシオ計算機株式会社 | 半導体装置並びにその製造方法および実装構造 |
US6800944B2 (en) * | 2001-12-19 | 2004-10-05 | Texas Instruments Incorporated | Power/ground ring substrate for integrated circuits |
-
2003
- 2003-06-11 JP JP2003165819A patent/JP2005005409A/ja active Pending
-
2004
- 2004-06-07 US US10/861,487 patent/US7164196B2/en active Active
- 2004-06-07 TW TW93116289A patent/TWI245380B/zh not_active IP Right Cessation
- 2004-06-11 CN CNA2004100489283A patent/CN1574307A/zh active Pending
- 2004-06-11 KR KR1020040042939A patent/KR20040106252A/ko not_active Application Discontinuation
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102640575A (zh) * | 2009-12-03 | 2012-08-15 | 国际商业机器公司 | 使用电阻性耦合减少芯片封装体中的电镀余线反射 |
CN102640575B (zh) * | 2009-12-03 | 2015-01-07 | 国际商业机器公司 | 使用电阻性耦合减少芯片封装体中的电镀余线反射 |
CN106971998A (zh) * | 2015-10-29 | 2017-07-21 | 飞思卡尔半导体公司 | 利用布设的基板 |
CN106971998B (zh) * | 2015-10-29 | 2021-10-26 | 恩智浦美国有限公司 | 利用布设的基板 |
CN107205315A (zh) * | 2016-03-18 | 2017-09-26 | 慧荣科技股份有限公司 | 印刷电路板以及组件制造方法 |
CN107205315B (zh) * | 2016-03-18 | 2020-04-28 | 慧荣科技股份有限公司 | 印刷电路板以及组件制造方法 |
Also Published As
Publication number | Publication date |
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TW200428610A (en) | 2004-12-16 |
US7164196B2 (en) | 2007-01-16 |
TWI245380B (en) | 2005-12-11 |
KR20040106252A (ko) | 2004-12-17 |
US20040253825A1 (en) | 2004-12-16 |
JP2005005409A (ja) | 2005-01-06 |
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