CN1519930B - 半导体器件、电子设备及它们的制造方法和电子仪器 - Google Patents
半导体器件、电子设备及它们的制造方法和电子仪器 Download PDFInfo
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- CN1519930B CN1519930B CN2004100032333A CN200410003233A CN1519930B CN 1519930 B CN1519930 B CN 1519930B CN 2004100032333 A CN2004100032333 A CN 2004100032333A CN 200410003233 A CN200410003233 A CN 200410003233A CN 1519930 B CN1519930 B CN 1519930B
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Abstract
一种半导体器件、电子设备及它们的制造方法和电子仪器,通过将突出电极(24),(36)分别结合于在承载基板(11)上设置的连接台(12c),承载基板(21),(31)的端部分别配置在半导体芯片(13)上,将承载基板(21),(31)分别安装在承载基板(11)上。根据本发明实现不同种类组件的三维安装结构。
Description
技术领域
本发明涉及半导体器件、电子设备、电子仪器、半导体器件的制造方法和电子设备的制造方法,尤其适用于半导体组件等的层叠结构中。
背景技术
原来的半导体器件中,为实现半导体芯片安装时的节省空间,例如特开平10-284683号公报所公开的那样,有边插入同种类的承载基板边三维安装半导体芯片的方法。
但是,在边插入同种类的承载基板边三维安装半导体芯片的方法中,难以层叠不同种类组件,由于难以层叠不同种类芯片,出现不能提高节省空间的有效性的问题。
发明内容
因此本发明的目的是提供可实现不同种类组件的三维安装结构的半导体器件、电子设备、电子仪器、半导体器件的制造方法和电子设备的制造方法。
为解决上述问题,根据本发明的一个形态的半导体器件,其特征在于包括:具有包含相邻的2边的第一区域和以一个对角线为边界与上述第一区域相邻、和上述第一区域外形对称的第二区域的矩形承载基板;搭载在上述承载基板上的半导体芯片;沿着上述第一区域的上述2边按L字状设置的第一突出电极群;配置在上述第二区域以使得其与上述第一突出电极群的配置不对称的第二突出电极群。
由此,可将突出电极群单面配置在承载基板上,经突出电极群支持承载基板,并且可在突出电极群的形成面侧上设置沿着承载基板的至少一边的突出电极的未配置区域。
因此,端部配置在第一承载基板上安装的第一半导体芯片上、安装第二半导体芯片的第二承载基板可支持在第一承载基板上,可抑制高度增加,并且可层叠不同种类组件。
根据本发明的一个形态的半导体器件,其特征在于包括:矩形的承载基板;搭载在上述承载基板上的半导体芯片;沿着在上述承载基板的第一顶点处相交的至少2个边设置的突出电极的未配置区域;沿着在与上述第一顶点相对的上述承载基板的第二顶点处相交的至少2个边设置的突出电极群。
由此,可将顶点配置在第一承载基板上安装的第一半导体芯片上、安装第二半导体芯片的第二承载基板支持在第一承载基板上,可在同一第一半导体芯片上配置多个承载基板,从而可进一步缩小安装面积。
根据本发明的一个形态的半导体器件,其特征在于包括:矩形的承载基板;搭载在上述承载基板上的半导体芯片;沿着上述承载基板的至少第一边设置的突出电极的未配置区域;沿着与上述第一边相对的上述承载基板的第二边和与上述第二边相交的至少第三边设置的突出电极群。
由此,可将边配置在第一承载基板上安装的第一半导体芯片上、安装第二半导体芯片的第二承载基板支持在第一承载基板上,可在同一第一半导体芯片上配置多个承载基板,从而可进一步缩小安装面积。
根据本发明的一个形态的半导体器件,其特征在于上述突出电极群按コ字状配置。
由此,即便承载基板的端部配置在半导体芯片上的情况下,也可由承载基板的至少4个角支持承载基板,可层叠不同种类组件,并且可稳定保持承载基板。
根据本发明的一个形态的半导体器件,其特征在于包括:承载基板;避开占据上述承载基板的端部配置的半导体芯片的搭载区域,来配置在上述承载基板上的突出电极。
由此,可支持承载基板的端部配置在半导体芯片上的承载基板。因此,可在同一半导体芯片上配置多个承载基板,可层叠不同种类组件,并且可缩小安装面积。
根据本发明的一个形态的半导体器件,其特征在于包括:承载基板;搭载在上述承载基板上的半导体芯片;设置在上述承载基板上的多个连接台电极;配置在上述多个连接台电极的一部分上的突出电极。
由此,即便连接台电极根据规定规格配置在承载基板上的情况下,可跨规定范围去除突出电极引起的突出部。因此,可实现承载基板的通用化,并且可在半导体芯片上配置承载基板的端部,抑制制造工序的复杂化,并且可在同一半导体芯片上配置多个承载基板。
根据本发明的一个形态的半导体器件,其特征在于包括:第一承载基板;搭载在上述第一承载基板上的第一半导体芯片;矩形的第二承载基板;搭载在上述第二承载基板上的第二半导体芯片;沿着在上述第二承载基板的第一顶点处相交的至少2个边设置的突出电极的未配置区域;沿着在与上述第一顶点相对的上述第二承载基板的第二顶点处相交的至少2个边设置、上述第一半导体芯片配置在上述突出电极的未配置区域下面、结合于上述第一承载基板上的突出电极群。
由此,第二承载基板的顶点配置在第一半导体芯片上、安装第二半导体芯片的第二承载基板可支持在第一承载基板上,可在同一第一半导体芯片上配置多个第二承载基板,从而可层叠不同种类芯片,并且可缩小安装面积。
另外,根据本发明的一个形态的半导体器件,其特征在于包括:第一承载基板;搭载在上述第一承载基板上的第一半导体芯片;矩形状的第二承载基板;搭载在上述第二承载基板上的第二半导体芯片;沿着上述第二承载基板的至少第一边设置的突出电极的未配置区域;沿着与上述第一边相对的上述第二承载基板的第二边和与上述第二边相交的至少第三边设置、上述第一半导体芯片配置在上述突出电极的未配置区域下面、结合于上述第一承载基板上的突出电极群。
由此,第二承载基板的边配置在第一半导体芯片上、安装第二半导体芯片的第二承载基板可支持在第一承载基板上,在同一第一半导体芯片上可配置多个第二承载基板,从而可层叠不同种类的芯片,并且可缩小安装面积。
根据本发明的一个形态的半导体器件,其特征在于包括:第一承载基板;搭载在上述第一承载基板上的第一半导体芯片;矩形状的第二半导体芯片;沿着在上述第二半导体芯片的第一顶点处相交的至少2个边设置的突出电极的未配置区域;沿着在与上述第一顶点相对的上述第二半导体芯片的第二顶点处相交的至少2个边设置、上述第一半导体芯片配置在上述突出电极的未配置区域下面、结合于上述第一承载基板上的突出电极群。
由此,可不在第一半导体芯片和第二半导体芯片之间插入承载基板,将第二半导体芯片的顶点配置在第一半导体芯片上的第二半导体芯片支持在第一承载基板上。从而,可抑制半导体芯片层叠时的高度增加,并且可在同一第一半导体芯片上配置多个第二半导体芯片,可层叠不同种类芯片,并且可缩小安装面积。
根据本发明的一个形态的半导体器件,其特征在于包括:第一承载基板;搭载在上述第一承载基板上的第一半导体芯片;矩形状的第二半导体芯片;沿着上述第二半导体芯片的至少第一边设置的突出电极的未配置区域;沿着与上述第一边相对的上述第二半导体芯片的第二边和与上述第二边相交的至少第三边设置、上述第一半导体芯片配置在上述突出电极的未配置区域下面、结合于上述第一承载基板上的突出电极群。
由此,可不在第一半导体芯片和第二半导体芯片之间插入承载基板,将第二半导体芯片的边配置在第一半导体芯片上的第二半导体芯片支持在第一承载基板上,可抑制半导体芯片层叠时的高度增加,并且可在同一第一半导体芯片上配置多个第二半导体芯片。
另外,根据本发明的一个形态的电子设备,其特征在于包括:第一承载基板;搭载在上述第一承载基板上的第一电子部件;矩形状的第二承载基板;搭载在上述第二承载基板上的第二电子部件;沿着在上述第二承载基板的第一顶点处相交的至少2个边设置的突出电极的未配置区域;沿着在与上述第一顶点相对的上述第二承载基板的第二顶点处相交的至少2个边设置、上述第一电子部件配置在上述突出电极的未配置区域下面、结合于上述第一承载基板上的突出电极群。
由此,可将顶点配置在第一电子部件上、安装了第二电子部件的第二承载基板支持在第一承载基板上,可在同一第一电子部件上配置多个承载基板,从而进一步缩小安装面积。
另外,根据本发明的一个形态的电子设备,其特征在于包括:第一承载基板;搭载在上述第一承载基板上的第一电子部件;矩形状的第二承载基板;搭载在上述第二承载基板上的第二电子部件;沿着上述第二承载基板的至少第一边设置的突出电极的未配置区域;沿着与上述第一边相对的上述第二承载基板的第二边和与上述第二边相交的至少第三边设置、上述第一电子部件配置在上述突出电极的未配置区域下面、结合于上述第一承载基板上的突出电极群。
由此,可将边配置在第一电子部件上、安装了第二电子部件的第二承载基板支持在第一承载基板上,可在同一第一电子部件上配置多个承载基板,从而进一步缩小安装面积。
根据本发明的一个形态的电子仪器,其特征在于包括:第一承载基板;搭载在上述第一承载基板上的第一半导体芯片;矩形状的第二承载基板;搭载在上述第二承载基板上的第二半导体芯片;沿着在上述第二承载基板的第一顶点处相交的至少2个边设置的突出电极的未配置区域;沿着在与上述第一顶点相对的上述第二承载基板的第二顶点处相交的至少2个边设置、上述第一半导体芯片配置在上述突出电极的未配置区域下面、结合于上述第一承载基板上的突出电极群;搭载上述第一承载基板的母基板。
由此,可将顶点配置在第一半导体芯片上的多个第二承载基板支持在第一承载基板上,可提高电子仪器的功能性,并且使电子仪器小型化、轻量化。
根据本发明的一个形态的电子仪器,其特征在于包括:第一承载基板;搭载在上述第一承载基板上的第一半导体芯片;矩形状的第二承载基板;搭载在上述第二承载基板上的第二半导体芯片;沿着上述第二承载基板的至少第一边设置的突出电极的未配置区域;沿着与上述第一边相对的上述第二承载基板的第二边和与上述第二边相交的至少第三边设置、上述第一半导体芯片配置在上述突出电极的未配置区域下面、结合于上述第一承载基板上的突出电极群;搭载上述第一承载基板的母基板。
由此,可将边配置在第一半导体芯片上的多个第二承载基板支持在第一承载基板上,可提高电子仪器的功能性,并且使电子仪器小型化、轻量化。
根据本发明的一个形态的半导体器件的制造方法,其特征在于包括:在第一承载基板上安装第一半导体芯片的工序;在第二承载基板上安装第二半导体芯片的工序;避开上述第二承载基板的至少一边的周围来在上述第二承载基板上形成突出电极群的工序;上述第二承载基板的至少一边配置在上述第一半导体芯片上、上述突出电极群结合于第一承载基板的工序。
由此,通过将突出电极群结合在第一承载基板上,可将顶点配置在第一半导体芯片上的第二承载基板支持在第一承载基板上。因此,通过调整突出电极群的配置位置可层叠不同种类芯片,抑制制造工序的复杂化,并且提高节省空间的有效性。
根据本发明的一个形态的半导体器件的制造方法,其特征在于包括:在第一承载基板上安装第一半导体芯片的工序;在第二承载基板上安装第二半导体芯片的工序;避开上述第二承载基板的至少一顶点的周围来在上述第二承载基板上形成突出电极群的工序;上述第二承载基板的至少一顶点配置在上述第一半导体芯片上、上述突出电极群结合于第一承载基板的工序。
由此,通过将突出电极群结合在第一承载基板上,可将边配置在第一半导体芯片上的第二承载基板支持在第一承载基板上。因此,通过调整突出电极群的配置位置可层叠不同种类芯片,抑制制造工序的复杂化,并且提高节省空间的有效性。
附图说明
图1是表示第一实施例的半导体器件的结构的截面图;
图2是表示第二实施例的突出电极的配置方法的平面图;
图3是表示第三实施例的突出电极的配置方法的平面图;
图4是表示第四实施例的突出电极的配置方法的平面图;
图5是表示第五实施例的突出电极的配置方法的平面图;
图6是表示第六实施例的突出电极的配置方法的平面图;
图7是表示第七实施例的突出电极的配置方法的平面图;
图8是表示第八实施例的半导体器件的制造方法的截面图;
图9是表示第九实施例的半导体器件的结构的截面图;
图10是表示第十实施例的半导体器件的结构的截面图;
图11是表示第十一实施例的半导体器件的结构的截面图。
具体实施方式
下面参考附图说明本发明的实施例的半导体器件、电子设备和它们的制造方法。
图1是表示第一实施例的半导体器件的结构的截面图。该第一实施例是,在通过ACF结合安装半导体芯片(或半导体模)13的半导体组件PK11上,分别层叠线焊连接堆叠结构的半导体芯片(或半导体模)23a~23c的半导体组件PK12和线焊连接堆叠结构的半导体芯片(或半导体模)33a~33c的半导体组件PK13。
图1中,半导体组件PK11上设置承载基板11,承载基板11的两面上分别形成连接台12a,12c的同时,承载基板11内形成内部布线12b。并且,承载基板11上倒片安装半导体芯片13,半导体芯片13上设置有用于倒片安装的突出电极14。并且,半导体芯片13上设置的突出电极14经各向异性导电片15ACF(各向异性导电膜)结合于连接台12c上。另外,在承载基板11的背面设置的连接台12a上设置有用于将承载基板11安装于母基板上的突出电极16。
这里,通过ACF结合把半导体芯片13安装在承载基板11上,使得不需要用于线焊、模压密封的空间,可实现三维安装时的空间节省,并且可实现将半导体芯片13结合在承载基板11上时的低温化,可降低实际使用时的承载基板11的翘曲。
另一方面,半导体组件PK12、PK13上分别设置有承载基板21,31。并且,承载基板21,31的背面上分别形成连接台22a,22a’,32a,32a’,同时承载基板21,31的表面上分别形成连接台22c,32c,承载基板21,31内分别形成有内部布线22b,32b。这里,连接台22a,32a上分别配置突出电极24,36,连接台22a’,32a’不配置突出电极24,36,原样留下来。
并且,承载基板21,31上分别经粘合层24a,34a各自面朝上安装半导体芯片23a,33a,半导体芯片23a,33a分别经导电性线25a,35a各自线焊连接连接台22c,32c。另外,半导体芯片23a,33a上避开导电性线25a,35a分别面朝上安装半导体芯片23b,33b,半导体芯片23b,33b分别经粘合层24b,34b各自固定在半导体芯片23a,33a上,同时分别经导电性线25b,35b各自线焊连接连接台22c,32c。此外,半导体芯片23b,33b上避开导电性线25b,35b分别面朝上安装半导体芯片23c,33c,半导体芯片23c,33c分别经粘合层24c,34c各自固定在半导体芯片23b,33b上,同时分别经导电性线25c,35c各自线焊连接连接台22c,32c。
另外,在承载基板21,31的背面分别设置的连接台22a,32a上分别设置将承载基板21,31分别保持在半导体芯片13上、分别将承载基板21,31安装在承载基板11上的突出电极24,36。这里,突出电极24,36最好避开半导体芯片13的配置区、存在于承载基板21,31的至少4个角上。由此,承载基板21,31的端部分别配置在半导体芯片13上、分别将承载基板21,31安装在承载基板11上的情况下,也可在承载基板11上稳定保持承载基板21,31。
另外,通过将未配置突出电极24,36的剩余下来的连接台22a’,32a’分别设置在承载基板21,31上,可调整突出电极24,36的配置位置。因此,即便变更承载基板11上安装的半导体芯片13的种类和大小的情况下,可不变更承载基板21,31的构成,重新配置突出电极24,36,可实现承载基板21,31的通用化。
并且,通过在承载基板11上设置的连接台12c上分别结合突出电极24,36,可将承载基板21,31的端部分别配置在半导体芯片13上,将承载基板21,31分别安装在承载基板11上。由此,可在同一半导体芯片13上配置多个半导体组件PK12,PK13,可缩小安装面积,并且实现不同种类半导体芯片13,23a~23c,33a~33c的三维安装。
这里,作为半导体芯片13,例如是CPU等的逻辑运算元件,作为半导体芯片23a~23c,33a~33c,例如是DRAM,SRAM,EEPROM,闪存储器等的存储元件。由此,可抑制安装面积的增大,并且实现各种功能,同时可容易实现存储元件的堆叠结构,容易增加存储容量。
将承载基板21,31分别安装在承载基板11上的情况下,承载基板21,31的背面可紧密结合于半导体芯片13上,承载基板21,31的背面可离开半导体芯片13。
承载基板21和承载基板31可以是侧壁紧密结合,也可以是侧壁离开。这里,通过紧密结合承载基板21和承载基板31的侧壁可提高半导体组件PK11上安装的半导体组件PK12,PK13的安装密度,实现节省空间。另一方面,通过分离承载基板21和承载基板31的侧壁可使半导体芯片13产生的热从半导体组件PK12,PK13之间的间隙逃离,提高半导体芯片13产生的热的散热性。
在半导体芯片23a~23c,33a~33c的安装面侧的承载基板21,31的整个一面上分别设置密封树脂27,37,通过该密封树脂27,37分别密封半导体芯片23a~23c,33a~33c。用密封树脂27,37分别密封半导体芯片23a~23c,33a~33c时,例如可通过使用环氧树脂等的热固化树脂的模压成型等进行。
作为承载基板11,21,31,例如可使用两面基板、多层布线基板、叠放基板、带基板或膜基板等,作为承载基板11,21,31的材质,可使用例如聚酰胺树脂、玻璃环氧树脂、BT树脂、芳族聚酰胺和环氧树脂的共聚物或陶瓷等。作为突出电极14,24,36,可使用例如Au块、用焊锡材料等覆盖的Cu块或Ni块、或焊锡球等,作为导电性线25a~25c,35a~35c,可使用例如Au线、Al线等。另外,上述实施例中,说明了为将承载基板21,31分别安装在承载基板11上,将突出电极24,36分别安装在承载基板24,36的连接台22a,32a上的方法,但可将突出电极24,36设置在承载基板11的连接台12c上。
上述实施例中,说明了通过ACF结合将半导体芯片13安装在承载基板11上的方法,但可使用例如NCF(非导电膜)结合等的其他粘合剂结合,也可使用焊锡结合和合金结合等的金属结合。说明了将半导体芯片23a~23c,33a~33c分别安装在承载基板21,31上的情况下,使用线焊连接方法,但可将半导体芯片23a~23c,33a~33c倒片安装在承载基板21,31上。另外,上述实施例中,举例说明了在承载基板11上仅安装1个半导体芯片13的方法,但可在承载基板11上安装多个半导体芯片。
半导体组件Pk11,PK12,PK13之间的间隙中可填充树脂。由此,可提高半导体组件PK11,PK12,PK13的耐冲击性,即便突出电极26,36的根基上集中残余应力的情况下,可防止突出电极26,36中诱发裂纹,从而提高半导体组件PK11,PK12,PK13的可靠性。
图2是表示本发明的第二实施例的突出电极的配置方法的平面图。该第二实施例是将承载基板42a~42d作4分割地配置在半导体芯片41上。
图2中,承载基板42a~42d上沿着在各承载基板42a~42d的顶点A1~D1处分别相交的2个边分别按L字状配置突出电极43a~43d。并且,沿着在与承载基板42a~42d的顶点A1~D1分别相对的顶点A1’~D1’处相交的2个边,分别设置突出电极43a~43d的未配置区域。
并且,承载基板42a~42d的顶点A1’~D1’分别配置在半导体芯片41上,承载基板42a~42d上设置的突出电极43a~43d结合于搭载半导体芯片41的下层基板上。由此,通过调整突出电极43a~43d的配置位置可在同一半导体芯片41上配置多个承载基板42a~42d,可抑制制造工序的复杂化,并且提高节省空间的有效性。
图3是表示本发明的第三实施例的突出电极的配置方法的平面图。该第三实施例在半导体芯片51上2分割地配置承载基板52a,52b。
图3中,承载基板52a,52b上沿着各承载基板52a,52b的边A2,B2和与边A2,B2分别相交的边分别按コ字状配置突出电极53a,53b。并且,沿着与承载基板52a,52b的边A2,B2分别相对的边A2’,B2’分别设置突出电极53a,53b的未配置区域。
并且,承载基板52a,52b的边A2’,B2’分别配置在半导体芯片51上,承载基板52a,52b上设置的突出电极53a,53b结合于搭载半导体芯片51的下层基板上。由此,通过调整突出电极53a,53b的配置位置可在同一半导体芯片51上配置多个承载基板52a,52b,可抑制制造工序的复杂化,并且提高节省空间的有效性。
图4是表示本发明的第四实施例的突出电极的配置方法的平面图。该第四实施例是将承载基板62a~62c作3分割地配置在半导体芯片61上。
图4中,在承载基板62a的周围,避开承载基板62a的边A3的周围配置突出电极63a。另外,在承载基板62b,62c的周围,分别避开各承载基板62b,63c4的顶点B3,C3的周围分别配置突出电极63b,63c。
并且,承载基板62a的边A3配置在半导体芯片61上,承载基板62a上设置的突出电极63a结合于搭载半导体芯片61的下层基板上。承载基板62b,63c4的顶点B3,C3分别配置在半导体芯片61上,承载基板62b,63c上设置的突出电极63b,63c结合于搭载半导体芯片61的下层基板上。
由此,通过调整突出电极63a~63c的配置位置,可在同一半导体芯片61上配置大小或种类不同的多个承载基板62a~62c,可抑制制造工序的复杂化,并且提高节省空间的有效性。
图5是表示本发明的第五实施例的突出电极的配置方法的平面图。该第五实施例是将承载基板72a~72c作3分割地配置在半导体芯片71上以使得承载基板72b跨在半导体芯片71上。
图5中,在承载基板72a,72c上沿着各承载基板72a,72c的边A4,C4和与边A4,C4分别相交的边,按コ字状分别配置突出电极73a,73c。并且沿着分别与承载基板72a,72c的边A4,C4相对的边A4’,C4’分别设置突出电极73a,73c的未配置区域。另一方面,承载基板72b上沿着承载基板72b的彼此相对的边B4,B4’配置突出电极73b,在边B4,B4’之间设置突出电极73b的未配置区域。
并且,承载基板72a,72c的边A4’,C4’分别配置在半导体芯片71上,承载基板72a,72c上分别设置的突出电极73a,73c结合于搭载半导体芯片71的下层基板上。并且,承载基板72b上设置的突出电极73b结合于搭载半导体芯片71的下层基板上,以使承载基板72b跨在半导体芯片71上。
由此,即便在3分割地将承载基板72a~72c配置在半导体芯片71上时,可分别支持各承载基板72a~72c的4个角,并且可在同一半导体芯片71上配置多个承载基板72a~72c,可抑制制造工序的复杂化,并且可提高节省空间的有效性。
图6是表示本发明的第六实施例的突出电极的配置方法的平面图。该第六实施例是将承载基板82a~82d和半导体芯片81的方向不同地将承载基板82a~82d作4分割配置在半导体芯片81上。
图6中,承载基板82a~82d上避开各承载基板82a~82d的顶点A5~D5周围分别配置突出电极83a~83d。并且例如,在半导体芯片81相对承载基板82a~82d以45度倾斜的状态下,将承载基板82a~82d的顶点A5~D5分别配置在半导体芯片81上,将突出电极83a~83d结合于搭载半导体芯片81的下层基板上。由此,通过调整突出电极83a~83d的配置位置可在同一半导体芯片81上改变方向地配置多个承载基板82a~82d,可抑制制造工序的复杂化,并且提高节省空间的有效性。
图7是表示本发明的第七实施例的突出电极的配置方法的平面图。该第七实施例是将半导体芯片91a~91d作4分割地配置在承载基板92上。
图7中,承载基板92上分别避开承载基板92的顶点A6~D6周围配置突出电极93。并且,将承载基板92配置在半导体芯片91a~91d上,使突出电极93结合于搭载半导体芯片91a~91d的下层基板上。由此,通过调整突出电极93的配置位置可在多个半导体芯片91a~91d上配置同一承载基板92,可抑制制造工序的复杂化,并且提高节省空间的有效性。
图8是表示本发明的第八实施例的半导体器件的制造方法的截面图。该第八实施例,通过把端部放置在半导体芯片103上的方式,将半导体组件PK22,PK23安装在半导体组件PK21上。
图8(a)中,半导体组件PK21上设置承载基板101,承载基板101的两面上分别形成有连接台102a,102b。并且,承载基板101上倒片安装半导体芯片103,半导体芯片103上设置用于倒片安装的突出电极104。并且,半导体芯片103上设置的突出电极104经各向异性导电片105,ACF结合在连接台102b上。
另一方面,半导体组件PK22、PK23上分别设置承载基板111,121,承载基板111,121的背面上分别形成连接台112,122,连接台112,122上分别设置焊锡球等的突出电极113,123。另外,承载基板111,121上分别安装半导体芯片,安装了半导体芯片的承载基板111,121的整个一面分别由密封树脂114,124进行密封。此外,承载基板111,121上可安装线焊连接的半导体芯片,也可倒片安装半导体芯片,也可安装半导体芯片的层叠结构。
并且,半导体组件PK21上分别层叠半导体组件PK22、PK23的情况下,向承载基板101的连接台102b上供给焊剂焊药(flux)或焊锡膏。
接着如图8(b)所示,在半导体组件PK21上彼此分离地安装半导体组件PK22、PK23,进行回流处理,使得将突出电极113,123分别结合于连接台102b上。
由此,通过调整承载基板111,121上配置的突出电极113,123的配置位置,可在同一半导体芯片103上配置多个半导体组件PK22、PK23,抑制制造工序的复杂化,并且可缩小安装面积。通过在半导体组件PK21上分别层叠半导体组件PK22、PK23,可仅选择安装检查过的合格品的半导体组件PK21,PK22,PK23,可提高制造成品率。
接着如图8(c)所示,在承载基板101的背面设置的连接台102a上形成用于将承载基板101安装在母基板上的突出电极106。
图9是表示本发明的第九实施例的半导体器件的结构的截面图。该第九实施例是通过将半导体芯片221,231的端部分别配置在半导体芯片213上,将半导体芯片213,221,231分别倒片安装在承载基板211上。
图9中,在承载基板211的两面上分别形成连接台212a,212c,同时承载基板211内形成有内部布线212b。并且,承载基板211上倒片安装半导体芯片213,半导体芯片213上设置有用于倒片安装的突出电极214。而且,半导体芯片213上设置的突出电极214经各向异性导电片215,ACF结合于连接台212c上。将半导体芯片213安装在承载基板211上时,除了使用ACF结合的方法,此外也可使用例如NCF结合等的其他粘合剂结合,可使用焊锡结合、合金结合等的金属结合。另外,在承载基板211背面上设置的连接台2412a上设置有将承载基板211安装在母基板上的突出电极216。
另一方面,半导体芯片221,231上分别设置电极垫222,232的同时,电极垫222,232分别露出地分别设置有绝缘膜223,233。并且,电极垫222,233上分别设置有,用于以半导体芯片221,231的端部分别保持在半导体芯片213上的方式分别倒片安装半导体芯片221,231的突出电极224,234。
这里,突出电极224,234可分别避开半导体芯片213的搭载区域来配置,例如,可以将突出电极224,234分别按コ字状、L字状或G字状排列。并且承载基板211上设置的连接台212c上分别结合突出电极224,234,半导体芯片221,231的端部分别配置在半导体芯片213上,半导体芯片221,231分别倒片安装在承载基板211上。
由此,即便在半导体芯片213,221,231的种类或大小不同的情况下,可不在半导体芯片213,221,231之间插入承载基板,且可将半导体芯片221,231倒片安装在半导体芯片213上。因此,可抑制半导体芯片213,221,231层叠时的高度增加,并且缩小安装面积,提高节省空间的有效性。
另外,将半导体芯片221,231安装在承载基板211上时,半导体芯片221,231可紧密结合于半导体芯片213上,半导体芯片221,231也可从半导体芯片213离开。另外,将半导体芯片221,231安装在承载基板211上时,可使用例如ACF结合、NCF结合等的粘合剂结合,也可使用焊锡结合、合金结合等的金属结合。作为突出电极212,214,224,234,可使用金块、用焊锡材料等覆盖的Cu块或Ni块、或焊锡球等。另外,半导体芯片221,231和承载基板211之间的间隙中可填充密封树脂。
图10是表示本发明的第十实施例的半导体器件的结构的截面图。该第十实施例中,以堆叠结构的半导体芯片321a~321c,331a~331c的端部分别配置在半导体芯片313上的方式,将堆叠结构的半导体芯片321a~321c,331a~331c倒片安装在承载基板311上。
图10中,承载基板311两面上分别形成连接台312a,312c的同时,承载基板311内形成有内部布线312b。并且,承载基板311上倒片安装半导体芯片313,半导体芯片313上设置有用于倒片安装的突出电极314。而且,半导体芯片313上设置的突出电极314经各向异性导电片315,ACF结合于连接台312c上。另外,将半导体芯片313安装在承载基板311上时,除了使用ACF结合的方法,此外也可使用例如NCF结合等的其他粘合剂结合,可使用焊锡结合、合金结合等的金属结合。此外,承载基板311背面上设置的连接台312a上设置有用于将承载基板311安装在母基板上的突出电极316。
另一方面,半导体芯片321a~321c,331a~331c上分别设置电极垫322a~322c,332a~332c的同时,各电极垫322a~322c,332a~332c分别露出地,分别设置有绝缘膜323a~323c,333a~333c。并且,半导体芯片321a~321c,331a~331c上例如对应各电极垫322a~322c,332a~332c的位置分别形成贯通孔324a~324c,334a~334c,各贯通孔324a~324c,334a~334c内分别经绝缘膜325a~325c,335a~335c和导电膜326a~326c,336a~336c各自形成有贯通电极327a~327c,337a~337c。并且分别形成了贯通电极327a~327c,337a~337c的半导体芯片321a~321c,331a~331c分别经贯通电极327a~327c,337a~337c层叠,在半导体芯片321a~321c,331a~331c之间的间隙中分别注入有树脂328a,328b,338a,338b。
并且,半导体芯片321a,331a上分别形成的各贯通电极327a,337a上分别设置有突出电极329,339,以便于以半导体芯片321a~321c,331a~331c的层叠结构的端部分别保持在半导体芯片313上的方式,分别倒片安装半导体芯片321a~321c,331a~331c的层叠结构。
这里,突出电极329,339可避开半导体芯片313的搭载区域配置,例如将突出电极329,339分别按コ字状、L字状、G字状排列。并且承载基板311上设置的连接台312c上分别结合突出电极329,339,以堆叠结构的半导体芯片321a~321c,331a~331c的端部分别配置在半导体芯片313上的方式,堆叠结构的半导体芯片321a~321c,331a~331c分别倒片安装在承载基板311上。
由此,可不在半导体芯片321a~321c,331a~331c的层叠结构和半导体芯片313之间插入承载基板,并将半导体芯片321a~321c,331a~331c的层叠结构分别倒片安装在半导体芯片313上,可抑制层叠时高度增加,并且可层叠多个和半导体芯片313不同种类的半导体芯片321a~321c,331a~331c。
将半导体芯片321a~321c,331a~331c的层叠结构安装在承载基板311上时,可使用例如ACF结合、NCF结合等的粘合剂结合,也可使用焊锡结合、合金结合等的金属结合。作为突出电极314,314,329,329,可使用例如金块、用焊锡等覆盖的Cu块或Ni块、或焊锡球等。上述实施例中,说明了将半导体芯片321a~321c,331a~331c的3层结构分别安装在承载基板311上的方法,但在承载基板311上安装的半导体芯片的层叠结构可以是2层或4层以上。半导体芯片321a,331a和承载基板311之间的间隙中可填充密封树脂。
图11是表示本发明的第十一实施例的半导体器件的结构的截面图。该第十一实施例是以多个W-CSP(晶片级-芯片大小组件)的端部分别配置在半导体芯片413上的方式,将W-CSP安装在承载基板411上。
图11中,在半导体组件PK31上设置承载基板411,在承载基板411的两面上分别形成连接台412a,412c的同时,承载基板411内形成有内部布线412b。并且,承载基板411上倒片安装半导体芯片413,半导体芯片413上设置有用于倒片安装的突出电极414。而且,半导体芯片413上设置的突出电极414经各向异性导电片415,ACF结合于连接台412c上。此外,承载基板411背面上设置的连接台412a上设置有将承载基板411安装在母基板上的突出电极416。
另一方面,在半导体组件PK32,PK33上分别设置半导体芯片421,431,各半导体芯片421,431上分别设置电极垫422,432的同时,各电极垫422,432分别露出地,分别设置绝缘膜423,433。并且,各半导体芯片421,431上,各电极垫422,432分别露出地,分别形成应力缓和层424,435,各电极垫422,432上分别形成有在应力缓和层424,435上分别延伸的再配置布线425,435。并且各再配置布线425,435上分别形成焊接抗蚀剂膜426,436,各焊接抗蚀剂膜426,436上在各应力缓和层424,435中分别形成使再配置布线425,435露出的开口部427,437。并且经各开口部427,437分别露出的再配置布线425,435上分别设置将半导体芯片421,431的端部分别保持在半导体芯片413上、各半导体芯片421,431分别面朝下安装在承载基板411上的突出电极428,438。
这里,突出电极428,438可避开半导体芯片413的搭载区域配置,例如将突出电极428,438分别按コ字状、L字状、G字状排列。并且承载基板411上设置的连接台412c上分别结合突出电极428,438,以半导体芯片421,431的端部分别配置在半导体芯片413上的方式,半导体组件PK32,PK33分别安装在承载基板411上。
由此,可将W-CSP层叠在倒片安装半导体芯片413的承载基板411上,即便在半导体芯片413,421,431的种类或大小不同的情况下,也不用在半导体芯片413,421,431之间插入承载基板,可将半导体芯片421,431三维安装在半导体芯片413上。因此,可抑制半导体芯片413,421,431层叠时高度增加,并且缩小安装面积,提高节省空间的有效性。
将半导体组件PK32,PK33安装在承载基板411上时,半导体组件PK32,PK33可紧密结合于半导体芯片413,半导体组件PK32,PK33也可从半导体芯片413离开。另外,将半导体组件PK32,PK33安装在承载基板411上时,可使用例如ACF结合、NCF结合等的粘合剂结合,也可使用焊锡结合、合金结合等的金属结合。作为突出电极414,416,428,438,可使用金块、用焊锡等覆盖的Cu块或Ni块、或焊锡球等。
上述的半导体器件和电子设备可适用于例如液晶显示装置、便携电话、便携信息终端、摄像机、MD(Mini Disc)播放器等的电子仪器,可提高电子仪器的性能,并且实现电子仪器的小型化、轻量化。
上述实施例中,举例说明了安装半导体芯片或半导体组件的方法,但本发明不限定于安装半导体芯片或半导体组件的方法,例如可安装弹性表面波(SAW)元件等的陶瓷元件、光调制器和光开关等的光学元件、磁传感器或生物传感器等的各种传感器类等。
Claims (15)
1.一种半导体器件,其特征在于包括:
矩形的承载基板;
搭载在上述承载基板上的半导体芯片;
沿着在上述承载基板的第一顶点处相交的至少2个边设置的突出电极的未配置区域;
沿着在与上述第一顶点相对的上述承载基板的第二顶点处相交的至少2个边设置的突出电极群。
2.一种半导体器件,其特征在于包括:
矩形的承载基板;
搭载在上述承载基板上的半导体芯片;
沿着上述承载基板的至少第一边设置的突出电极的未配置区域;
沿着与上述第一边相对的上述承载基板的第二边和与上述第二边相交的至少第三边设置的突出电极群。
3.根据权利要求2所述的半导体器件,其特征在于上述突出电极群按コ字状配置。
4.一种半导体器件,其特征在于包括:
承载基板;
避开以搭在上述承载基板的端部上的方式配置的半导体芯片的搭载区域,来配置在上述承载基板上的突出电极。
5.一种半导体器件,其特征在于包括:
承载基板;
搭载在上述承载基板上的半导体芯片;
设置在上述承载基板上的多个连接台电极;
配置在上述多个连接台电极的一部分上的突出电极。
6.一种半导体器件,其特征在于包括:
第一承载基板;
搭载在上述第一承载基板上的第一半导体芯片;
矩形的第二承载基板;
搭载在上述第二承载基板上的第二半导体芯片;
沿着在上述第二承载基板的第一顶点处相交的至少2个边设置的突出电极的未配置区域;
沿着在与上述第一顶点相对的上述第二承载基板的第二顶点处相交的至少2个边设置的,将上述第一半导体芯片配置在上述突出电极的未配置区域下面、结合于上述第一承载基板上的突出电极群。
7.一种半导体器件,其特征在于包括:
第一承载基板;
搭载在上述第一承载基板上的第一半导体芯片;
矩形的第二承载基板;
搭载在上述第二承载基板上的第二半导体芯片;
沿着上述第二承载基板的至少第一边设置的突出电极的未配置区域;
沿着与上述第一边相对的上述第二承载基板的第二边和与上述第二边相交的至少第三边设置的,将上述第一半导体芯片配置在上述突出电极的未配置区域下面、结合于上述第一承载基板上的突出电极群。
8.一种半导体器件,其特征在于包括:
第一承载基板;
搭载在上述第一承载基板上的第一半导体芯片;
矩形的第二半导体芯片;
沿着在上述第二半导体芯片的第一顶点处相交的至少2个边设置的突出电极的未配置区域;
沿着在与上述第一顶点相对的上述第二半导体芯片的第二顶点处相交的至少2个边设置的,将上述第一半导体芯片配置在上述突出电极的未配置区域下面、结合于上述第一承载基板上的突出电极群。
9.一种半导体器件,其特征在于包括:
第一承载基板;
搭载在上述第一承载基板上的第一半导体芯片;
矩形的第二半导体芯片;
沿着上述第二半导体芯片的至少第一边设置的突出电极的未配置区域;
沿着与上述第一边相对的上述第二半导体芯片的第二边和与上述第二边相交的至少第三边设置的,将上述第一半导体芯片配置在上述突出电极的未配置区域下面、结合于上述第一承载基板上的突出电极群。
10.一种电子设备,其特征在于包括:
第一承载基板;
搭载在上述第一承载基板上的第一电子部件;
矩形的第二承载基板;
搭载在上述第二承载基板上的第二电子部件;
沿着在上述第二承载基板的第一顶点处相交的至少2个边设置的突出电极的未配置区域;
沿着在与上述第一顶点相对的上述第二承载基板的第二顶点处相交的至少2个边设置的,将上述第一电子部件配置在上述突出电极的未配置区域下面、结合于上述第一承载基板上的突出电极群。
11.一种电子设备,其特征在于包括:
第一承载基板;
搭载在上述第一承载基板上的第一电子部件;
矩形的第二承载基板;
搭载在上述第二承载基板上的第二电子部件;
沿着上述第二承载基板的至少第一边设置的突出电极的未配置区域;
沿着与上述第一边相对的上述第二承载基板的第二边和与上述第二边相交的至少第三边设置的,将上述第一电子部件配置在上述突出电极的未配置区域下面、结合于上述第一承载基板上的突出电极群。
12.一种电子仪器,其特征在于包括:
第一承载基板;
搭载在上述第一承载基板上的第一半导体芯片;
矩形的第二承载基板;
搭载在上述第二承载基板上的第二半导体芯片;
沿着在上述第二承载基板的第一顶点处相交的至少2个边设置的突出电极的未配置区域;
沿着在与上述第一顶点相对的上述第二承载基板的第二顶点处相交的至少2个边设置的,将上述第一半导体芯片配置在上述突出电极的未配置区域下面、结合于上述第一承载基板上的突出电极群;
搭载上述第一承载基板的母基板。
13.一种电子仪器,其特征在于包括:
第一承载基板;
搭载在上述第一承载基板上的第一半导体芯片;
矩形的第二承载基板;
搭载在上述第二承载基板上的第二半导体芯片;
沿着上述第二承载基板的至少第一边设置的突出电极的未配置区域;
沿着与上述第一边相对的上述第二承载基板的第二边和与上述第二边相交的至少第三边设置的,将上述第一半导体芯片配置在上述突出电极的未配置区域下面、结合于上述第一承载基板上的突出电极群;
搭载上述第一承载基板的母基板。
14.一种半导体器件的制造方法,其特征在于包括:
在第一承载基板上安装第一半导体芯片的工序;
在第二承载基板上安装第二半导体芯片的工序;
避开上述第二承载基板的至少一边的周围来在上述第二承载基板上形成突出电极群的工序;
上述第二承载基板的至少一边配置在上述第一半导体芯片上、上述突出电极群结合于第一承载基板的工序。
15.一种半导体器件的制造方法,其特征在于包括:
在第一承载基板上安装第一半导体芯片的工序;
在第二承载基板上安装第二半导体芯片的工序;
避开上述第二承载基板的至少一顶点的周围来在上述第二承载基板上形成突出电极群的工序;
上述第二承载基板的至少一顶点配置在上述第一半导体芯片上、上述突出电极群结合于第一承载基板的工序。
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TWI528514B (zh) * | 2009-08-20 | 2016-04-01 | 精材科技股份有限公司 | 晶片封裝體及其製造方法 |
JPWO2011036840A1 (ja) * | 2009-09-24 | 2013-02-14 | パナソニック株式会社 | 半導体装置、半導体実装体、および半導体装置の製造方法 |
JP6010880B2 (ja) * | 2011-04-15 | 2016-10-19 | 株式会社ニコン | 位置情報検出センサ、位置情報検出センサの製造方法、エンコーダ、モータ装置及びロボット装置 |
US8704384B2 (en) | 2012-02-17 | 2014-04-22 | Xilinx, Inc. | Stacked die assembly |
US8704364B2 (en) * | 2012-02-08 | 2014-04-22 | Xilinx, Inc. | Reducing stress in multi-die integrated circuit structures |
US8957512B2 (en) | 2012-06-19 | 2015-02-17 | Xilinx, Inc. | Oversized interposer |
US8869088B1 (en) | 2012-06-27 | 2014-10-21 | Xilinx, Inc. | Oversized interposer formed from a multi-pattern region mask |
US9026872B2 (en) | 2012-08-16 | 2015-05-05 | Xilinx, Inc. | Flexible sized die for use in multi-die integrated circuit |
US9547034B2 (en) | 2013-07-03 | 2017-01-17 | Xilinx, Inc. | Monolithic integrated circuit die having modular die regions stitched together |
KR102163723B1 (ko) * | 2013-08-20 | 2020-10-08 | 삼성전자주식회사 | 비대칭 전극 배치 구조를 갖는 반도체 소자 |
JP2015177007A (ja) * | 2014-03-14 | 2015-10-05 | 株式会社東芝 | 半導体装置の製造方法及び半導体装置 |
US9915869B1 (en) | 2014-07-01 | 2018-03-13 | Xilinx, Inc. | Single mask set used for interposer fabrication of multiple products |
KR102181013B1 (ko) * | 2014-09-05 | 2020-11-19 | 삼성전자주식회사 | 반도체 패키지 |
KR102324628B1 (ko) * | 2015-07-24 | 2021-11-10 | 삼성전자주식회사 | 솔리드 스테이트 드라이브 패키지 및 이를 포함하는 데이터 저장 시스템 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5222014A (en) * | 1992-03-02 | 1993-06-22 | Motorola, Inc. | Three-dimensional multi-chip pad array carrier |
US5763939A (en) * | 1994-09-30 | 1998-06-09 | Nec Corporation | Semiconductor device having a perforated base film sheet |
Family Cites Families (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5120678A (en) * | 1990-11-05 | 1992-06-09 | Motorola Inc. | Electrical component package comprising polymer-reinforced solder bump interconnection |
GB9312328D0 (en) * | 1993-06-15 | 1993-07-28 | Lexor Technology Limited | A method of brazing |
JPH08115989A (ja) * | 1994-08-24 | 1996-05-07 | Fujitsu Ltd | 半導体装置及びその製造方法 |
WO1997020347A1 (en) * | 1995-11-28 | 1997-06-05 | Hitachi, Ltd. | Semiconductor device, process for producing the same, and packaged substrate |
JPH10163386A (ja) * | 1996-12-03 | 1998-06-19 | Toshiba Corp | 半導体装置、半導体パッケージおよび実装回路装置 |
US5770477A (en) * | 1997-02-10 | 1998-06-23 | Delco Electronics Corporation | Flip chip-on-flip chip multi-chip module |
US5994166A (en) * | 1997-03-10 | 1999-11-30 | Micron Technology, Inc. | Method of constructing stacked packages |
JP2964983B2 (ja) * | 1997-04-02 | 1999-10-18 | 日本電気株式会社 | 三次元メモリモジュール及びそれを用いた半導体装置 |
JPH10294423A (ja) * | 1997-04-17 | 1998-11-04 | Nec Corp | 半導体装置 |
US6369444B1 (en) * | 1998-05-19 | 2002-04-09 | Agere Systems Guardian Corp. | Packaging silicon on silicon multichip modules |
JP3201353B2 (ja) * | 1998-08-04 | 2001-08-20 | 日本電気株式会社 | 半導体装置とその製造方法 |
US6133634A (en) * | 1998-08-05 | 2000-10-17 | Fairchild Semiconductor Corporation | High performance flip chip package |
TW434767B (en) * | 1998-09-05 | 2001-05-16 | Via Tech Inc | Package architecture of ball grid array integrated circuit device |
US6573119B1 (en) * | 1999-02-17 | 2003-06-03 | Hitachi, Ltd. | Semiconductor device and method of manufacture thereof |
US6034425A (en) * | 1999-03-17 | 2000-03-07 | Chipmos Technologies Inc. | Flat multiple-chip module micro ball grid array packaging |
US6023097A (en) * | 1999-03-17 | 2000-02-08 | Chipmos Technologies, Inc. | Stacked multiple-chip module micro ball grid array packaging |
US6122171A (en) * | 1999-07-30 | 2000-09-19 | Micron Technology, Inc. | Heat sink chip package and method of making |
TW415056B (en) * | 1999-08-05 | 2000-12-11 | Siliconware Precision Industries Co Ltd | Multi-chip packaging structure |
JP2001156212A (ja) * | 1999-09-16 | 2001-06-08 | Nec Corp | 樹脂封止型半導体装置及びその製造方法 |
JP3881488B2 (ja) * | 1999-12-13 | 2007-02-14 | 株式会社東芝 | 回路モジュールの冷却装置およびこの冷却装置を有する電子機器 |
US6369448B1 (en) * | 2000-01-21 | 2002-04-09 | Lsi Logic Corporation | Vertically integrated flip chip semiconductor package |
US6731009B1 (en) * | 2000-03-20 | 2004-05-04 | Cypress Semiconductor Corporation | Multi-die assembly |
JP2001339011A (ja) * | 2000-03-24 | 2001-12-07 | Shinko Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2001352035A (ja) * | 2000-06-07 | 2001-12-21 | Sony Corp | 多層半導体装置の組立治具及び多層半導体装置の製造方法 |
US6461881B1 (en) * | 2000-06-08 | 2002-10-08 | Micron Technology, Inc. | Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures |
JP2002134650A (ja) * | 2000-10-23 | 2002-05-10 | Rohm Co Ltd | 半導体装置およびその製造方法 |
JP2002158312A (ja) * | 2000-11-17 | 2002-05-31 | Oki Electric Ind Co Ltd | 3次元実装用半導体パッケージ、その製造方法、および半導体装置 |
US6734539B2 (en) * | 2000-12-27 | 2004-05-11 | Lucent Technologies Inc. | Stacked module package |
US6686225B2 (en) * | 2001-07-27 | 2004-02-03 | Texas Instruments Incorporated | Method of separating semiconductor dies from a wafer |
US6787916B2 (en) * | 2001-09-13 | 2004-09-07 | Tru-Si Technologies, Inc. | Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity |
JP3866591B2 (ja) * | 2001-10-29 | 2007-01-10 | 富士通株式会社 | 電極間接続構造体の形成方法および電極間接続構造体 |
JP2003218150A (ja) * | 2002-01-23 | 2003-07-31 | Fujitsu Media Device Kk | モジュール部品 |
JP2003318361A (ja) * | 2002-04-19 | 2003-11-07 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6903458B1 (en) * | 2002-06-20 | 2005-06-07 | Richard J. Nathan | Embedded carrier for an integrated circuit chip |
JP4072020B2 (ja) * | 2002-08-09 | 2008-04-02 | 日本電波工業株式会社 | 表面実装水晶発振器 |
JP2004179232A (ja) * | 2002-11-25 | 2004-06-24 | Seiko Epson Corp | 半導体装置及びその製造方法並びに電子機器 |
JP4096774B2 (ja) * | 2003-03-24 | 2008-06-04 | セイコーエプソン株式会社 | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法 |
-
2003
- 2003-02-06 JP JP2003029841A patent/JP3891123B2/ja not_active Expired - Fee Related
-
2004
- 2004-02-02 CN CN2004100032333A patent/CN1519930B/zh not_active Expired - Fee Related
- 2004-02-05 US US10/772,572 patent/US20040195668A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5222014A (en) * | 1992-03-02 | 1993-06-22 | Motorola, Inc. | Three-dimensional multi-chip pad array carrier |
US5763939A (en) * | 1994-09-30 | 1998-06-09 | Nec Corporation | Semiconductor device having a perforated base film sheet |
Also Published As
Publication number | Publication date |
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CN1519930A (zh) | 2004-08-11 |
JP3891123B2 (ja) | 2007-03-14 |
US20040195668A1 (en) | 2004-10-07 |
JP2004241648A (ja) | 2004-08-26 |
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